0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * dts file for Xilinx ZynqMP ZCU104
0004 *
0005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/gpio/gpio.h>
0015 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0016 #include <dt-bindings/phy/phy.h>
0017
0018 / {
0019 model = "ZynqMP ZCU104 RevC";
0020 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
0021
0022 aliases {
0023 ethernet0 = &gem3;
0024 i2c0 = &i2c1;
0025 mmc0 = &sdhci1;
0026 nvmem0 = &eeprom;
0027 rtc0 = &rtc;
0028 serial0 = &uart0;
0029 serial1 = &uart1;
0030 serial2 = &dcc;
0031 spi0 = &qspi;
0032 usb0 = &usb0;
0033 };
0034
0035 chosen {
0036 bootargs = "earlycon";
0037 stdout-path = "serial0:115200n8";
0038 };
0039
0040 memory@0 {
0041 device_type = "memory";
0042 reg = <0x0 0x0 0x0 0x80000000>;
0043 };
0044
0045 ina226 {
0046 compatible = "iio-hwmon";
0047 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
0048 };
0049
0050 clock_8t49n287_5: clk125 {
0051 compatible = "fixed-clock";
0052 #clock-cells = <0>;
0053 clock-frequency = <125000000>;
0054 };
0055
0056 clock_8t49n287_2: clk26 {
0057 compatible = "fixed-clock";
0058 #clock-cells = <0>;
0059 clock-frequency = <26000000>;
0060 };
0061
0062 clock_8t49n287_3: clk27 {
0063 compatible = "fixed-clock";
0064 #clock-cells = <0>;
0065 clock-frequency = <27000000>;
0066 };
0067 };
0068
0069 &can1 {
0070 status = "okay";
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_can1_default>;
0073 };
0074
0075 &dcc {
0076 status = "okay";
0077 };
0078
0079 &fpd_dma_chan1 {
0080 status = "okay";
0081 };
0082
0083 &fpd_dma_chan2 {
0084 status = "okay";
0085 };
0086
0087 &fpd_dma_chan3 {
0088 status = "okay";
0089 };
0090
0091 &fpd_dma_chan4 {
0092 status = "okay";
0093 };
0094
0095 &fpd_dma_chan5 {
0096 status = "okay";
0097 };
0098
0099 &fpd_dma_chan6 {
0100 status = "okay";
0101 };
0102
0103 &fpd_dma_chan7 {
0104 status = "okay";
0105 };
0106
0107 &fpd_dma_chan8 {
0108 status = "okay";
0109 };
0110
0111 &gem3 {
0112 status = "okay";
0113 phy-handle = <&phy0>;
0114 phy-mode = "rgmii-id";
0115 pinctrl-names = "default";
0116 pinctrl-0 = <&pinctrl_gem3_default>;
0117 phy0: ethernet-phy@c {
0118 reg = <0xc>;
0119 ti,rx-internal-delay = <0x8>;
0120 ti,tx-internal-delay = <0xa>;
0121 ti,fifo-depth = <0x1>;
0122 ti,dp83867-rxctrl-strap-quirk;
0123 };
0124 };
0125
0126 &gpio {
0127 status = "okay";
0128 };
0129
0130 &i2c1 {
0131 status = "okay";
0132 clock-frequency = <400000>;
0133 pinctrl-names = "default", "gpio";
0134 pinctrl-0 = <&pinctrl_i2c1_default>;
0135 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0136 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
0137 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
0138
0139 tca6416_u97: gpio@20 {
0140 compatible = "ti,tca6416";
0141 reg = <0x20>;
0142 gpio-controller;
0143 #gpio-cells = <2>;
0144 /*
0145 * IRQ not connected
0146 * Lines:
0147 * 0 - IRPS5401_ALERT_B
0148 * 1 - HDMI_8T49N241_INT_ALM
0149 * 2 - MAX6643_OT_B
0150 * 3 - MAX6643_FANFAIL_B
0151 * 5 - IIC_MUX_RESET_B
0152 * 6 - GEM3_EXP_RESET_B
0153 * 7 - FMC_LPC_PRSNT_M2C_B
0154 * 4, 10 - 17 - not connected
0155 */
0156 };
0157
0158 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
0159 i2c-mux@74 { /* u34 */
0160 compatible = "nxp,pca9548";
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 reg = <0x74>;
0164 i2c@0 {
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 reg = <0>;
0168 /*
0169 * IIC_EEPROM 1kB memory which uses 256B blocks
0170 * where every block has different address.
0171 * 0 - 256B address 0x54
0172 * 256B - 512B address 0x55
0173 * 512B - 768B address 0x56
0174 * 768B - 1024B address 0x57
0175 */
0176 eeprom: eeprom@54 { /* u23 */
0177 compatible = "atmel,24c08";
0178 reg = <0x54>;
0179 #address-cells = <1>;
0180 #size-cells = <1>;
0181 };
0182 };
0183
0184 i2c@1 {
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187 reg = <1>;
0188 /* 8T49N287 - u182 */
0189 };
0190
0191 i2c@2 {
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 reg = <2>;
0195 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
0196 compatible = "infineon,irps5401";
0197 reg = <0x43>; /* pmbus / i2c 0x13 */
0198 };
0199 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
0200 compatible = "infineon,irps5401";
0201 reg = <0x44>; /* pmbus / i2c 0x14 */
0202 };
0203 };
0204
0205 i2c@3 {
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 reg = <3>;
0209 u183: ina226@40 { /* u183 */
0210 compatible = "ti,ina226";
0211 #io-channel-cells = <1>;
0212 reg = <0x40>;
0213 shunt-resistor = <5000>;
0214 };
0215 };
0216
0217 i2c@5 {
0218 #address-cells = <1>;
0219 #size-cells = <0>;
0220 reg = <5>;
0221 };
0222
0223 i2c@7 {
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226 reg = <7>;
0227 };
0228
0229 /* 4, 6 not connected */
0230 };
0231 };
0232
0233 &pinctrl0 {
0234 status = "okay";
0235
0236 pinctrl_can1_default: can1-default {
0237 mux {
0238 function = "can1";
0239 groups = "can1_6_grp";
0240 };
0241
0242 conf {
0243 groups = "can1_6_grp";
0244 slew-rate = <SLEW_RATE_SLOW>;
0245 power-source = <IO_STANDARD_LVCMOS18>;
0246 drive-strength = <12>;
0247 };
0248
0249 conf-rx {
0250 pins = "MIO25";
0251 bias-high-impedance;
0252 };
0253
0254 conf-tx {
0255 pins = "MIO24";
0256 bias-disable;
0257 };
0258 };
0259
0260 pinctrl_i2c1_default: i2c1-default {
0261 mux {
0262 groups = "i2c1_4_grp";
0263 function = "i2c1";
0264 };
0265
0266 conf {
0267 groups = "i2c1_4_grp";
0268 bias-pull-up;
0269 slew-rate = <SLEW_RATE_SLOW>;
0270 power-source = <IO_STANDARD_LVCMOS18>;
0271 drive-strength = <12>;
0272 };
0273 };
0274
0275 pinctrl_i2c1_gpio: i2c1-gpio {
0276 mux {
0277 groups = "gpio0_16_grp", "gpio0_17_grp";
0278 function = "gpio0";
0279 };
0280
0281 conf {
0282 groups = "gpio0_16_grp", "gpio0_17_grp";
0283 slew-rate = <SLEW_RATE_SLOW>;
0284 power-source = <IO_STANDARD_LVCMOS18>;
0285 drive-strength = <12>;
0286 };
0287 };
0288
0289 pinctrl_gem3_default: gem3-default {
0290 mux {
0291 function = "ethernet3";
0292 groups = "ethernet3_0_grp";
0293 };
0294
0295 conf {
0296 groups = "ethernet3_0_grp";
0297 slew-rate = <SLEW_RATE_SLOW>;
0298 power-source = <IO_STANDARD_LVCMOS18>;
0299 drive-strength = <12>;
0300 };
0301
0302 conf-rx {
0303 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0304 "MIO75";
0305 bias-high-impedance;
0306 low-power-disable;
0307 };
0308
0309 conf-tx {
0310 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0311 "MIO69";
0312 bias-disable;
0313 low-power-enable;
0314 };
0315
0316 mux-mdio {
0317 function = "mdio3";
0318 groups = "mdio3_0_grp";
0319 };
0320
0321 conf-mdio {
0322 groups = "mdio3_0_grp";
0323 slew-rate = <SLEW_RATE_SLOW>;
0324 power-source = <IO_STANDARD_LVCMOS18>;
0325 bias-disable;
0326 };
0327 };
0328
0329 pinctrl_sdhci1_default: sdhci1-default {
0330 mux {
0331 groups = "sdio1_0_grp";
0332 function = "sdio1";
0333 };
0334
0335 conf {
0336 groups = "sdio1_0_grp";
0337 slew-rate = <SLEW_RATE_SLOW>;
0338 power-source = <IO_STANDARD_LVCMOS18>;
0339 bias-disable;
0340 drive-strength = <12>;
0341 };
0342
0343 mux-cd {
0344 groups = "sdio1_cd_0_grp";
0345 function = "sdio1_cd";
0346 };
0347
0348 conf-cd {
0349 groups = "sdio1_cd_0_grp";
0350 bias-high-impedance;
0351 bias-pull-up;
0352 slew-rate = <SLEW_RATE_SLOW>;
0353 power-source = <IO_STANDARD_LVCMOS18>;
0354 };
0355 };
0356
0357 pinctrl_uart0_default: uart0-default {
0358 mux {
0359 groups = "uart0_4_grp";
0360 function = "uart0";
0361 };
0362
0363 conf {
0364 groups = "uart0_4_grp";
0365 slew-rate = <SLEW_RATE_SLOW>;
0366 power-source = <IO_STANDARD_LVCMOS18>;
0367 drive-strength = <12>;
0368 };
0369
0370 conf-rx {
0371 pins = "MIO18";
0372 bias-high-impedance;
0373 };
0374
0375 conf-tx {
0376 pins = "MIO19";
0377 bias-disable;
0378 };
0379 };
0380
0381 pinctrl_uart1_default: uart1-default {
0382 mux {
0383 groups = "uart1_5_grp";
0384 function = "uart1";
0385 };
0386
0387 conf {
0388 groups = "uart1_5_grp";
0389 slew-rate = <SLEW_RATE_SLOW>;
0390 power-source = <IO_STANDARD_LVCMOS18>;
0391 drive-strength = <12>;
0392 };
0393
0394 conf-rx {
0395 pins = "MIO21";
0396 bias-high-impedance;
0397 };
0398
0399 conf-tx {
0400 pins = "MIO20";
0401 bias-disable;
0402 };
0403 };
0404
0405 pinctrl_usb0_default: usb0-default {
0406 mux {
0407 groups = "usb0_0_grp";
0408 function = "usb0";
0409 };
0410
0411 conf {
0412 groups = "usb0_0_grp";
0413 slew-rate = <SLEW_RATE_SLOW>;
0414 power-source = <IO_STANDARD_LVCMOS18>;
0415 drive-strength = <12>;
0416 };
0417
0418 conf-rx {
0419 pins = "MIO52", "MIO53", "MIO55";
0420 bias-high-impedance;
0421 };
0422
0423 conf-tx {
0424 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0425 "MIO60", "MIO61", "MIO62", "MIO63";
0426 bias-disable;
0427 };
0428 };
0429 };
0430
0431 &psgtr {
0432 status = "okay";
0433 /* nc, sata, usb3, dp */
0434 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
0435 clock-names = "ref1", "ref2", "ref3";
0436 };
0437
0438 &qspi {
0439 status = "okay";
0440 flash@0 {
0441 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
0442 #address-cells = <1>;
0443 #size-cells = <1>;
0444 reg = <0x0>;
0445 spi-tx-bus-width = <1>;
0446 spi-rx-bus-width = <4>;
0447 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0448 };
0449 };
0450
0451 &rtc {
0452 status = "okay";
0453 };
0454
0455 &sata {
0456 status = "okay";
0457 /* SATA OOB timing settings */
0458 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0459 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0460 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0461 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0462 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0463 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0464 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0465 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0466 phy-names = "sata-phy";
0467 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
0468 };
0469
0470 /* SD1 with level shifter */
0471 &sdhci1 {
0472 status = "okay";
0473 no-1-8-v;
0474 pinctrl-names = "default";
0475 pinctrl-0 = <&pinctrl_sdhci1_default>;
0476 xlnx,mio-bank = <1>;
0477 disable-wp;
0478 };
0479
0480 &uart0 {
0481 status = "okay";
0482 pinctrl-names = "default";
0483 pinctrl-0 = <&pinctrl_uart0_default>;
0484 };
0485
0486 &uart1 {
0487 status = "okay";
0488 pinctrl-names = "default";
0489 pinctrl-0 = <&pinctrl_uart1_default>;
0490 };
0491
0492 /* ULPI SMSC USB3320 */
0493 &usb0 {
0494 status = "okay";
0495 pinctrl-names = "default";
0496 pinctrl-0 = <&pinctrl_usb0_default>;
0497 phy-names = "usb3-phy";
0498 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0499 };
0500
0501 &dwc3_0 {
0502 status = "okay";
0503 dr_mode = "host";
0504 snps,usb3_lpm_capable;
0505 maximum-speed = "super-speed";
0506 };
0507
0508 &watchdog0 {
0509 status = "okay";
0510 };
0511
0512 &zynqmp_dpdma {
0513 status = "okay";
0514 };
0515
0516 &zynqmp_dpsub {
0517 status = "okay";
0518 phy-names = "dp-phy0", "dp-phy1";
0519 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
0520 <&psgtr 0 PHY_TYPE_DP 1 3>;
0521 };
