0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP ZCU104
0004 *
0005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/gpio/gpio.h>
0015 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0016 #include <dt-bindings/phy/phy.h>
0017
0018 / {
0019 model = "ZynqMP ZCU104 RevA";
0020 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
0021
0022 aliases {
0023 ethernet0 = &gem3;
0024 i2c0 = &i2c1;
0025 mmc0 = &sdhci1;
0026 nvmem0 = &eeprom;
0027 rtc0 = &rtc;
0028 serial0 = &uart0;
0029 serial1 = &uart1;
0030 serial2 = &dcc;
0031 spi0 = &qspi;
0032 usb0 = &usb0;
0033 };
0034
0035 chosen {
0036 bootargs = "earlycon";
0037 stdout-path = "serial0:115200n8";
0038 };
0039
0040 memory@0 {
0041 device_type = "memory";
0042 reg = <0x0 0x0 0x0 0x80000000>;
0043 };
0044
0045 clock_8t49n287_5: clk125 {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <125000000>;
0049 };
0050
0051 clock_8t49n287_2: clk26 {
0052 compatible = "fixed-clock";
0053 #clock-cells = <0>;
0054 clock-frequency = <26000000>;
0055 };
0056
0057 clock_8t49n287_3: clk27 {
0058 compatible = "fixed-clock";
0059 #clock-cells = <0>;
0060 clock-frequency = <27000000>;
0061 };
0062 };
0063
0064 &can1 {
0065 status = "okay";
0066 pinctrl-names = "default";
0067 pinctrl-0 = <&pinctrl_can1_default>;
0068 };
0069
0070 &dcc {
0071 status = "okay";
0072 };
0073
0074 &fpd_dma_chan1 {
0075 status = "okay";
0076 };
0077
0078 &fpd_dma_chan2 {
0079 status = "okay";
0080 };
0081
0082 &fpd_dma_chan3 {
0083 status = "okay";
0084 };
0085
0086 &fpd_dma_chan4 {
0087 status = "okay";
0088 };
0089
0090 &fpd_dma_chan5 {
0091 status = "okay";
0092 };
0093
0094 &fpd_dma_chan6 {
0095 status = "okay";
0096 };
0097
0098 &fpd_dma_chan7 {
0099 status = "okay";
0100 };
0101
0102 &fpd_dma_chan8 {
0103 status = "okay";
0104 };
0105
0106 &gem3 {
0107 status = "okay";
0108 phy-handle = <&phy0>;
0109 phy-mode = "rgmii-id";
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_gem3_default>;
0112 phy0: ethernet-phy@c {
0113 reg = <0xc>;
0114 ti,rx-internal-delay = <0x8>;
0115 ti,tx-internal-delay = <0xa>;
0116 ti,fifo-depth = <0x1>;
0117 ti,dp83867-rxctrl-strap-quirk;
0118 };
0119 };
0120
0121 &gpio {
0122 status = "okay";
0123 };
0124
0125 &i2c1 {
0126 status = "okay";
0127 clock-frequency = <400000>;
0128 pinctrl-names = "default", "gpio";
0129 pinctrl-0 = <&pinctrl_i2c1_default>;
0130 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0131 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
0132 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
0133
0134 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
0135 i2c-mux@74 { /* u34 */
0136 compatible = "nxp,pca9548";
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139 reg = <0x74>;
0140 i2c@0 {
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143 reg = <0>;
0144 /*
0145 * IIC_EEPROM 1kB memory which uses 256B blocks
0146 * where every block has different address.
0147 * 0 - 256B address 0x54
0148 * 256B - 512B address 0x55
0149 * 512B - 768B address 0x56
0150 * 768B - 1024B address 0x57
0151 */
0152 eeprom: eeprom@54 { /* u23 */
0153 compatible = "atmel,24c08";
0154 reg = <0x54>;
0155 #address-cells = <1>;
0156 #size-cells = <1>;
0157 };
0158 };
0159
0160 i2c@1 {
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 reg = <1>;
0164 /* 8T49N287 - u182 */
0165 };
0166
0167 i2c@2 {
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170 reg = <2>;
0171 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
0172 compatible = "infineon,irps5401";
0173 reg = <0x43>; /* pmbus / i2c 0x13 */
0174 };
0175 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
0176 compatible = "infineon,irps5401";
0177 reg = <0x44>; /* pmbus / i2c 0x14 */
0178 };
0179 };
0180
0181 i2c@4 {
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184 reg = <4>;
0185 tca6416_u97: gpio@20 {
0186 compatible = "ti,tca6416";
0187 reg = <0x20>;
0188 gpio-controller;
0189 #gpio-cells = <2>;
0190 /*
0191 * IRQ not connected
0192 * Lines:
0193 * 0 - IRPS5401_ALERT_B
0194 * 1 - HDMI_8T49N241_INT_ALM
0195 * 2 - MAX6643_OT_B
0196 * 3 - MAX6643_FANFAIL_B
0197 * 5 - IIC_MUX_RESET_B
0198 * 6 - GEM3_EXP_RESET_B
0199 * 7 - FMC_LPC_PRSNT_M2C_B
0200 * 4, 10 - 17 - not connected
0201 */
0202 };
0203 };
0204
0205 i2c@5 {
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 reg = <5>;
0209 };
0210
0211 i2c@7 {
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 reg = <7>;
0215 };
0216
0217 /* 3, 6 not connected */
0218 };
0219 };
0220
0221 &pinctrl0 {
0222 status = "okay";
0223
0224 pinctrl_can1_default: can1-default {
0225 mux {
0226 function = "can1";
0227 groups = "can1_6_grp";
0228 };
0229
0230 conf {
0231 groups = "can1_6_grp";
0232 slew-rate = <SLEW_RATE_SLOW>;
0233 power-source = <IO_STANDARD_LVCMOS18>;
0234 drive-strength = <12>;
0235 };
0236
0237 conf-rx {
0238 pins = "MIO25";
0239 bias-high-impedance;
0240 };
0241
0242 conf-tx {
0243 pins = "MIO24";
0244 bias-disable;
0245 };
0246 };
0247
0248 pinctrl_i2c1_default: i2c1-default {
0249 mux {
0250 groups = "i2c1_4_grp";
0251 function = "i2c1";
0252 };
0253
0254 conf {
0255 groups = "i2c1_4_grp";
0256 bias-pull-up;
0257 slew-rate = <SLEW_RATE_SLOW>;
0258 power-source = <IO_STANDARD_LVCMOS18>;
0259 drive-strength = <12>;
0260 };
0261 };
0262
0263 pinctrl_i2c1_gpio: i2c1-gpio {
0264 mux {
0265 groups = "gpio0_16_grp", "gpio0_17_grp";
0266 function = "gpio0";
0267 };
0268
0269 conf {
0270 groups = "gpio0_16_grp", "gpio0_17_grp";
0271 slew-rate = <SLEW_RATE_SLOW>;
0272 power-source = <IO_STANDARD_LVCMOS18>;
0273 drive-strength = <12>;
0274 };
0275 };
0276
0277 pinctrl_gem3_default: gem3-default {
0278 mux {
0279 function = "ethernet3";
0280 groups = "ethernet3_0_grp";
0281 };
0282
0283 conf {
0284 groups = "ethernet3_0_grp";
0285 slew-rate = <SLEW_RATE_SLOW>;
0286 power-source = <IO_STANDARD_LVCMOS18>;
0287 drive-strength = <12>;
0288 };
0289
0290 conf-rx {
0291 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0292 "MIO75";
0293 bias-high-impedance;
0294 low-power-disable;
0295 };
0296
0297 conf-tx {
0298 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0299 "MIO69";
0300 bias-disable;
0301 low-power-enable;
0302 };
0303
0304 mux-mdio {
0305 function = "mdio3";
0306 groups = "mdio3_0_grp";
0307 };
0308
0309 conf-mdio {
0310 groups = "mdio3_0_grp";
0311 slew-rate = <SLEW_RATE_SLOW>;
0312 power-source = <IO_STANDARD_LVCMOS18>;
0313 bias-disable;
0314 };
0315 };
0316
0317 pinctrl_sdhci1_default: sdhci1-default {
0318 mux {
0319 groups = "sdio1_0_grp";
0320 function = "sdio1";
0321 };
0322
0323 conf {
0324 groups = "sdio1_0_grp";
0325 slew-rate = <SLEW_RATE_SLOW>;
0326 power-source = <IO_STANDARD_LVCMOS18>;
0327 bias-disable;
0328 drive-strength = <12>;
0329 };
0330
0331 mux-cd {
0332 groups = "sdio1_cd_0_grp";
0333 function = "sdio1_cd";
0334 };
0335
0336 conf-cd {
0337 groups = "sdio1_cd_0_grp";
0338 bias-high-impedance;
0339 bias-pull-up;
0340 slew-rate = <SLEW_RATE_SLOW>;
0341 power-source = <IO_STANDARD_LVCMOS18>;
0342 };
0343 };
0344
0345 pinctrl_uart0_default: uart0-default {
0346 mux {
0347 groups = "uart0_4_grp";
0348 function = "uart0";
0349 };
0350
0351 conf {
0352 groups = "uart0_4_grp";
0353 slew-rate = <SLEW_RATE_SLOW>;
0354 power-source = <IO_STANDARD_LVCMOS18>;
0355 drive-strength = <12>;
0356 };
0357
0358 conf-rx {
0359 pins = "MIO18";
0360 bias-high-impedance;
0361 };
0362
0363 conf-tx {
0364 pins = "MIO19";
0365 bias-disable;
0366 };
0367 };
0368
0369 pinctrl_uart1_default: uart1-default {
0370 mux {
0371 groups = "uart1_5_grp";
0372 function = "uart1";
0373 };
0374
0375 conf {
0376 groups = "uart1_5_grp";
0377 slew-rate = <SLEW_RATE_SLOW>;
0378 power-source = <IO_STANDARD_LVCMOS18>;
0379 drive-strength = <12>;
0380 };
0381
0382 conf-rx {
0383 pins = "MIO21";
0384 bias-high-impedance;
0385 };
0386
0387 conf-tx {
0388 pins = "MIO20";
0389 bias-disable;
0390 };
0391 };
0392
0393 pinctrl_usb0_default: usb0-default {
0394 mux {
0395 groups = "usb0_0_grp";
0396 function = "usb0";
0397 };
0398
0399 conf {
0400 groups = "usb0_0_grp";
0401 slew-rate = <SLEW_RATE_SLOW>;
0402 power-source = <IO_STANDARD_LVCMOS18>;
0403 drive-strength = <12>;
0404 };
0405
0406 conf-rx {
0407 pins = "MIO52", "MIO53", "MIO55";
0408 bias-high-impedance;
0409 };
0410
0411 conf-tx {
0412 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0413 "MIO60", "MIO61", "MIO62", "MIO63";
0414 bias-disable;
0415 };
0416 };
0417 };
0418
0419 &psgtr {
0420 status = "okay";
0421 /* nc, sata, usb3, dp */
0422 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
0423 clock-names = "ref1", "ref2", "ref3";
0424 };
0425
0426 &qspi {
0427 status = "okay";
0428 flash@0 {
0429 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
0430 #address-cells = <1>;
0431 #size-cells = <1>;
0432 reg = <0x0>;
0433 spi-tx-bus-width = <1>;
0434 spi-rx-bus-width = <4>;
0435 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0436 };
0437 };
0438
0439 &rtc {
0440 status = "okay";
0441 };
0442
0443 &sata {
0444 status = "okay";
0445 /* SATA OOB timing settings */
0446 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0447 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0448 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0449 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0450 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0451 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0452 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0453 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0454 phy-names = "sata-phy";
0455 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
0456 };
0457
0458 /* SD1 with level shifter */
0459 &sdhci1 {
0460 status = "okay";
0461 no-1-8-v;
0462 pinctrl-names = "default";
0463 pinctrl-0 = <&pinctrl_sdhci1_default>;
0464 xlnx,mio-bank = <1>;
0465 disable-wp;
0466 };
0467
0468 &uart0 {
0469 status = "okay";
0470 pinctrl-names = "default";
0471 pinctrl-0 = <&pinctrl_uart0_default>;
0472 };
0473
0474 &uart1 {
0475 status = "okay";
0476 pinctrl-names = "default";
0477 pinctrl-0 = <&pinctrl_uart1_default>;
0478 };
0479
0480 /* ULPI SMSC USB3320 */
0481 &usb0 {
0482 status = "okay";
0483 pinctrl-names = "default";
0484 pinctrl-0 = <&pinctrl_usb0_default>;
0485 phy-names = "usb3-phy";
0486 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0487 };
0488
0489 &dwc3_0 {
0490 status = "okay";
0491 dr_mode = "host";
0492 snps,usb3_lpm_capable;
0493 maximum-speed = "super-speed";
0494 };
0495
0496 &watchdog0 {
0497 status = "okay";
0498 };
0499
0500 &zynqmp_dpdma {
0501 status = "okay";
0502 };
0503
0504 &zynqmp_dpsub {
0505 status = "okay";
0506 phy-names = "dp-phy0", "dp-phy1";
0507 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
0508 <&psgtr 0 PHY_TYPE_DP 1 3>;
0509 };
