arm64/xilinx/zynqmp-zcu102-revB.dts

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * dts file for Xilinx ZynqMP ZCU102 RevB
0004  *
0005  * (C) Copyright 2016 - 2021, Xilinx, Inc.
0006  *
0007  * Michal Simek <michal.simek@xilinx.com>
0008  */
0009
0010 #include "zynqmp-zcu102-revA.dts"
0011
0012 / {
0013         model = "ZynqMP ZCU102 RevB";
0014         compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
0015 };
0016
0017 &gem3 {
0018         phy-handle = <&phyc>;
0019         phyc: ethernet-phy@c {
0020                 reg = <0xc>;
0021                 ti,rx-internal-delay = <0x8>;
0022                 ti,tx-internal-delay = <0xa>;
0023                 ti,fifo-depth = <0x1>;
0024                 ti,dp83867-rxctrl-strap-quirk;
0025                 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
0026         };
0027         /* Cleanup from RevA */
0028         /delete-node/ ethernet-phy@21;
0029 };
0030
0031 /* Fix collision with u61 */
0032 &i2c0 {
0033         i2c-mux@75 {
0034                 i2c@2 {
0035                         max15303@1b { /* u8 */
0036                                 compatible = "maxim,max15303";
0037                                 reg = <0x1b>;
0038                         };
0039                         /delete-node/ max15303@20;
0040                 };
0041         };
0042 };