0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP ZCU102 RevA
0004 *
0005 * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/input/input.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0017 #include <dt-bindings/phy/phy.h>
0018
0019 / {
0020 model = "ZynqMP ZCU102 RevA";
0021 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
0022
0023 aliases {
0024 ethernet0 = &gem3;
0025 i2c0 = &i2c0;
0026 i2c1 = &i2c1;
0027 mmc0 = &sdhci1;
0028 nvmem0 = &eeprom;
0029 rtc0 = &rtc;
0030 serial0 = &uart0;
0031 serial1 = &uart1;
0032 serial2 = &dcc;
0033 spi0 = &qspi;
0034 usb0 = &usb0;
0035 };
0036
0037 chosen {
0038 bootargs = "earlycon";
0039 stdout-path = "serial0:115200n8";
0040 };
0041
0042 memory@0 {
0043 device_type = "memory";
0044 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0045 };
0046
0047 gpio-keys {
0048 compatible = "gpio-keys";
0049 autorepeat;
0050 switch-19 {
0051 label = "sw19";
0052 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
0053 linux,code = <KEY_DOWN>;
0054 wakeup-source;
0055 autorepeat;
0056 };
0057 };
0058
0059 leds {
0060 compatible = "gpio-leds";
0061 heartbeat-led {
0062 label = "heartbeat";
0063 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
0064 linux,default-trigger = "heartbeat";
0065 };
0066 };
0067
0068 ina226-u76 {
0069 compatible = "iio-hwmon";
0070 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
0071 };
0072 ina226-u77 {
0073 compatible = "iio-hwmon";
0074 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
0075 };
0076 ina226-u78 {
0077 compatible = "iio-hwmon";
0078 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
0079 };
0080 ina226-u87 {
0081 compatible = "iio-hwmon";
0082 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
0083 };
0084 ina226-u85 {
0085 compatible = "iio-hwmon";
0086 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
0087 };
0088 ina226-u86 {
0089 compatible = "iio-hwmon";
0090 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
0091 };
0092 ina226-u93 {
0093 compatible = "iio-hwmon";
0094 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
0095 };
0096 ina226-u88 {
0097 compatible = "iio-hwmon";
0098 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
0099 };
0100 ina226-u15 {
0101 compatible = "iio-hwmon";
0102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
0103 };
0104 ina226-u92 {
0105 compatible = "iio-hwmon";
0106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
0107 };
0108 ina226-u79 {
0109 compatible = "iio-hwmon";
0110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
0111 };
0112 ina226-u81 {
0113 compatible = "iio-hwmon";
0114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
0115 };
0116 ina226-u80 {
0117 compatible = "iio-hwmon";
0118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
0119 };
0120 ina226-u84 {
0121 compatible = "iio-hwmon";
0122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
0123 };
0124 ina226-u16 {
0125 compatible = "iio-hwmon";
0126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
0127 };
0128 ina226-u65 {
0129 compatible = "iio-hwmon";
0130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
0131 };
0132 ina226-u74 {
0133 compatible = "iio-hwmon";
0134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
0135 };
0136 ina226-u75 {
0137 compatible = "iio-hwmon";
0138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
0139 };
0140
0141 /* 48MHz reference crystal */
0142 ref48: ref48M {
0143 compatible = "fixed-clock";
0144 #clock-cells = <0>;
0145 clock-frequency = <48000000>;
0146 };
0147
0148 refhdmi: refhdmi {
0149 compatible = "fixed-clock";
0150 #clock-cells = <0>;
0151 clock-frequency = <114285000>;
0152 };
0153 };
0154
0155 &can1 {
0156 status = "okay";
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_can1_default>;
0159 };
0160
0161 &dcc {
0162 status = "okay";
0163 };
0164
0165 &fpd_dma_chan1 {
0166 status = "okay";
0167 };
0168
0169 &fpd_dma_chan2 {
0170 status = "okay";
0171 };
0172
0173 &fpd_dma_chan3 {
0174 status = "okay";
0175 };
0176
0177 &fpd_dma_chan4 {
0178 status = "okay";
0179 };
0180
0181 &fpd_dma_chan5 {
0182 status = "okay";
0183 };
0184
0185 &fpd_dma_chan6 {
0186 status = "okay";
0187 };
0188
0189 &fpd_dma_chan7 {
0190 status = "okay";
0191 };
0192
0193 &fpd_dma_chan8 {
0194 status = "okay";
0195 };
0196
0197 &gem3 {
0198 status = "okay";
0199 phy-handle = <&phy0>;
0200 phy-mode = "rgmii-id";
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_gem3_default>;
0203 phy0: ethernet-phy@21 {
0204 reg = <21>;
0205 ti,rx-internal-delay = <0x8>;
0206 ti,tx-internal-delay = <0xa>;
0207 ti,fifo-depth = <0x1>;
0208 ti,dp83867-rxctrl-strap-quirk;
0209 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
0210 };
0211 };
0212
0213 &gpio {
0214 status = "okay";
0215 pinctrl-names = "default";
0216 pinctrl-0 = <&pinctrl_gpio_default>;
0217 };
0218
0219 &i2c0 {
0220 status = "okay";
0221 clock-frequency = <400000>;
0222 pinctrl-names = "default", "gpio";
0223 pinctrl-0 = <&pinctrl_i2c0_default>;
0224 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0225 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
0226 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
0227
0228 tca6416_u97: gpio@20 {
0229 compatible = "ti,tca6416";
0230 reg = <0x20>;
0231 gpio-controller; /* IRQ not connected */
0232 #gpio-cells = <2>;
0233 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
0234 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
0235 "", "", "", "", "", "", "", "", "";
0236 gtr-sel0-hog {
0237 gpio-hog;
0238 gpios = <0 0>;
0239 output-low; /* PCIE = 0, DP = 1 */
0240 line-name = "sel0";
0241 };
0242 gtr-sel1-hog {
0243 gpio-hog;
0244 gpios = <1 0>;
0245 output-high; /* PCIE = 0, DP = 1 */
0246 line-name = "sel1";
0247 };
0248 gtr-sel2-hog {
0249 gpio-hog;
0250 gpios = <2 0>;
0251 output-high; /* PCIE = 0, USB0 = 1 */
0252 line-name = "sel2";
0253 };
0254 gtr-sel3-hog {
0255 gpio-hog;
0256 gpios = <3 0>;
0257 output-high; /* PCIE = 0, SATA = 1 */
0258 line-name = "sel3";
0259 };
0260 };
0261
0262 tca6416_u61: gpio@21 {
0263 compatible = "ti,tca6416";
0264 reg = <0x21>;
0265 gpio-controller; /* IRQ not connected */
0266 #gpio-cells = <2>;
0267 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
0268 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
0269 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
0270 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
0271 };
0272
0273 i2c-mux@75 { /* u60 */
0274 compatible = "nxp,pca9544";
0275 #address-cells = <1>;
0276 #size-cells = <0>;
0277 reg = <0x75>;
0278 i2c@0 {
0279 #address-cells = <1>;
0280 #size-cells = <0>;
0281 reg = <0>;
0282 /* PS_PMBUS */
0283 u76: ina226@40 { /* u76 */
0284 compatible = "ti,ina226";
0285 #io-channel-cells = <1>;
0286 label = "ina226-u76";
0287 reg = <0x40>;
0288 shunt-resistor = <5000>;
0289 };
0290 u77: ina226@41 { /* u77 */
0291 compatible = "ti,ina226";
0292 #io-channel-cells = <1>;
0293 label = "ina226-u77";
0294 reg = <0x41>;
0295 shunt-resistor = <5000>;
0296 };
0297 u78: ina226@42 { /* u78 */
0298 compatible = "ti,ina226";
0299 #io-channel-cells = <1>;
0300 label = "ina226-u78";
0301 reg = <0x42>;
0302 shunt-resistor = <5000>;
0303 };
0304 u87: ina226@43 { /* u87 */
0305 compatible = "ti,ina226";
0306 #io-channel-cells = <1>;
0307 label = "ina226-u87";
0308 reg = <0x43>;
0309 shunt-resistor = <5000>;
0310 };
0311 u85: ina226@44 { /* u85 */
0312 compatible = "ti,ina226";
0313 #io-channel-cells = <1>;
0314 label = "ina226-u85";
0315 reg = <0x44>;
0316 shunt-resistor = <5000>;
0317 };
0318 u86: ina226@45 { /* u86 */
0319 compatible = "ti,ina226";
0320 #io-channel-cells = <1>;
0321 label = "ina226-u86";
0322 reg = <0x45>;
0323 shunt-resistor = <5000>;
0324 };
0325 u93: ina226@46 { /* u93 */
0326 compatible = "ti,ina226";
0327 #io-channel-cells = <1>;
0328 label = "ina226-u93";
0329 reg = <0x46>;
0330 shunt-resistor = <5000>;
0331 };
0332 u88: ina226@47 { /* u88 */
0333 compatible = "ti,ina226";
0334 #io-channel-cells = <1>;
0335 label = "ina226-u88";
0336 reg = <0x47>;
0337 shunt-resistor = <5000>;
0338 };
0339 u15: ina226@4a { /* u15 */
0340 compatible = "ti,ina226";
0341 #io-channel-cells = <1>;
0342 label = "ina226-u15";
0343 reg = <0x4a>;
0344 shunt-resistor = <5000>;
0345 };
0346 u92: ina226@4b { /* u92 */
0347 compatible = "ti,ina226";
0348 #io-channel-cells = <1>;
0349 label = "ina226-u92";
0350 reg = <0x4b>;
0351 shunt-resistor = <5000>;
0352 };
0353 };
0354 i2c@1 {
0355 #address-cells = <1>;
0356 #size-cells = <0>;
0357 reg = <1>;
0358 /* PL_PMBUS */
0359 u79: ina226@40 { /* u79 */
0360 compatible = "ti,ina226";
0361 #io-channel-cells = <1>;
0362 label = "ina226-u79";
0363 reg = <0x40>;
0364 shunt-resistor = <2000>;
0365 };
0366 u81: ina226@41 { /* u81 */
0367 compatible = "ti,ina226";
0368 #io-channel-cells = <1>;
0369 label = "ina226-u81";
0370 reg = <0x41>;
0371 shunt-resistor = <5000>;
0372 };
0373 u80: ina226@42 { /* u80 */
0374 compatible = "ti,ina226";
0375 #io-channel-cells = <1>;
0376 label = "ina226-u80";
0377 reg = <0x42>;
0378 shunt-resistor = <5000>;
0379 };
0380 u84: ina226@43 { /* u84 */
0381 compatible = "ti,ina226";
0382 #io-channel-cells = <1>;
0383 label = "ina226-u84";
0384 reg = <0x43>;
0385 shunt-resistor = <5000>;
0386 };
0387 u16: ina226@44 { /* u16 */
0388 compatible = "ti,ina226";
0389 #io-channel-cells = <1>;
0390 label = "ina226-u16";
0391 reg = <0x44>;
0392 shunt-resistor = <5000>;
0393 };
0394 u65: ina226@45 { /* u65 */
0395 compatible = "ti,ina226";
0396 #io-channel-cells = <1>;
0397 label = "ina226-u65";
0398 reg = <0x45>;
0399 shunt-resistor = <5000>;
0400 };
0401 u74: ina226@46 { /* u74 */
0402 compatible = "ti,ina226";
0403 #io-channel-cells = <1>;
0404 label = "ina226-u74";
0405 reg = <0x46>;
0406 shunt-resistor = <5000>;
0407 };
0408 u75: ina226@47 { /* u75 */
0409 compatible = "ti,ina226";
0410 #io-channel-cells = <1>;
0411 label = "ina226-u75";
0412 reg = <0x47>;
0413 shunt-resistor = <5000>;
0414 };
0415 };
0416 i2c@2 {
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 reg = <2>;
0420 /* MAXIM_PMBUS - 00 */
0421 max15301@a { /* u46 */
0422 compatible = "maxim,max15301";
0423 reg = <0xa>;
0424 };
0425 max15303@b { /* u4 */
0426 compatible = "maxim,max15303";
0427 reg = <0xb>;
0428 };
0429 max15303@10 { /* u13 */
0430 compatible = "maxim,max15303";
0431 reg = <0x10>;
0432 };
0433 max15301@13 { /* u47 */
0434 compatible = "maxim,max15301";
0435 reg = <0x13>;
0436 };
0437 max15303@14 { /* u7 */
0438 compatible = "maxim,max15303";
0439 reg = <0x14>;
0440 };
0441 max15303@15 { /* u6 */
0442 compatible = "maxim,max15303";
0443 reg = <0x15>;
0444 };
0445 max15303@16 { /* u10 */
0446 compatible = "maxim,max15303";
0447 reg = <0x16>;
0448 };
0449 max15303@17 { /* u9 */
0450 compatible = "maxim,max15303";
0451 reg = <0x17>;
0452 };
0453 max15301@18 { /* u63 */
0454 compatible = "maxim,max15301";
0455 reg = <0x18>;
0456 };
0457 max15303@1a { /* u49 */
0458 compatible = "maxim,max15303";
0459 reg = <0x1a>;
0460 };
0461 max15303@1d { /* u18 */
0462 compatible = "maxim,max15303";
0463 reg = <0x1d>;
0464 };
0465 max15303@20 { /* u8 */
0466 compatible = "maxim,max15303";
0467 status = "disabled"; /* unreachable */
0468 reg = <0x20>;
0469 };
0470 max20751@72 { /* u95 */
0471 compatible = "maxim,max20751";
0472 reg = <0x72>;
0473 };
0474 max20751@73 { /* u96 */
0475 compatible = "maxim,max20751";
0476 reg = <0x73>;
0477 };
0478 };
0479 /* Bus 3 is not connected */
0480 };
0481 };
0482
0483 &i2c1 {
0484 status = "okay";
0485 clock-frequency = <400000>;
0486 pinctrl-names = "default", "gpio";
0487 pinctrl-0 = <&pinctrl_i2c1_default>;
0488 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0489 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
0490 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
0491
0492 /* PL i2c via PCA9306 - u45 */
0493 i2c-mux@74 { /* u34 */
0494 compatible = "nxp,pca9548";
0495 #address-cells = <1>;
0496 #size-cells = <0>;
0497 reg = <0x74>;
0498 i2c@0 {
0499 #address-cells = <1>;
0500 #size-cells = <0>;
0501 reg = <0>;
0502 /*
0503 * IIC_EEPROM 1kB memory which uses 256B blocks
0504 * where every block has different address.
0505 * 0 - 256B address 0x54
0506 * 256B - 512B address 0x55
0507 * 512B - 768B address 0x56
0508 * 768B - 1024B address 0x57
0509 */
0510 eeprom: eeprom@54 { /* u23 */
0511 compatible = "atmel,24c08";
0512 reg = <0x54>;
0513 };
0514 };
0515 i2c@1 {
0516 #address-cells = <1>;
0517 #size-cells = <0>;
0518 reg = <1>;
0519 si5341: clock-generator@36 { /* SI5341 - u69 */
0520 compatible = "silabs,si5341";
0521 reg = <0x36>;
0522 #clock-cells = <2>;
0523 #address-cells = <1>;
0524 #size-cells = <0>;
0525 clocks = <&ref48>;
0526 clock-names = "xtal";
0527 clock-output-names = "si5341";
0528
0529 si5341_0: out@0 {
0530 /* refclk0 for PS-GT, used for DP */
0531 reg = <0>;
0532 always-on;
0533 };
0534 si5341_2: out@2 {
0535 /* refclk2 for PS-GT, used for USB3 */
0536 reg = <2>;
0537 always-on;
0538 };
0539 si5341_3: out@3 {
0540 /* refclk3 for PS-GT, used for SATA */
0541 reg = <3>;
0542 always-on;
0543 };
0544 si5341_4: out@4 {
0545 /* refclk4 for PS-GT, used for PCIE slot */
0546 reg = <4>;
0547 always-on;
0548 };
0549 si5341_5: out@5 {
0550 /* refclk5 for PS-GT, used for PCIE */
0551 reg = <5>;
0552 always-on;
0553 };
0554 si5341_6: out@6 {
0555 /* refclk6 PL CLK125 */
0556 reg = <6>;
0557 always-on;
0558 };
0559 si5341_7: out@7 {
0560 /* refclk7 PL CLK74 */
0561 reg = <7>;
0562 always-on;
0563 };
0564 si5341_9: out@9 {
0565 /* refclk9 used for PS_REF_CLK 33.3 MHz */
0566 reg = <9>;
0567 always-on;
0568 };
0569 };
0570 };
0571 i2c@2 {
0572 #address-cells = <1>;
0573 #size-cells = <0>;
0574 reg = <2>;
0575 si570_1: clock-generator@5d { /* USER SI570 - u42 */
0576 #clock-cells = <0>;
0577 compatible = "silabs,si570";
0578 reg = <0x5d>;
0579 temperature-stability = <50>;
0580 factory-fout = <300000000>;
0581 clock-frequency = <300000000>;
0582 clock-output-names = "si570_user";
0583 };
0584 };
0585 i2c@3 {
0586 #address-cells = <1>;
0587 #size-cells = <0>;
0588 reg = <3>;
0589 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
0590 #clock-cells = <0>;
0591 compatible = "silabs,si570";
0592 reg = <0x5d>;
0593 temperature-stability = <50>; /* copy from zc702 */
0594 factory-fout = <156250000>;
0595 clock-frequency = <148500000>;
0596 clock-output-names = "si570_mgt";
0597 };
0598 };
0599 i2c@4 {
0600 #address-cells = <1>;
0601 #size-cells = <0>;
0602 reg = <4>;
0603 /* SI5328 - u20 */
0604 };
0605 /* 5 - 7 unconnected */
0606 };
0607
0608 i2c-mux@75 {
0609 compatible = "nxp,pca9548"; /* u135 */
0610 #address-cells = <1>;
0611 #size-cells = <0>;
0612 reg = <0x75>;
0613
0614 i2c@0 {
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 reg = <0>;
0618 /* HPC0_IIC */
0619 };
0620 i2c@1 {
0621 #address-cells = <1>;
0622 #size-cells = <0>;
0623 reg = <1>;
0624 /* HPC1_IIC */
0625 };
0626 i2c@2 {
0627 #address-cells = <1>;
0628 #size-cells = <0>;
0629 reg = <2>;
0630 /* SYSMON */
0631 };
0632 i2c@3 {
0633 #address-cells = <1>;
0634 #size-cells = <0>;
0635 reg = <3>;
0636 /* DDR4 SODIMM */
0637 };
0638 i2c@4 {
0639 #address-cells = <1>;
0640 #size-cells = <0>;
0641 reg = <4>;
0642 /* SEP 3 */
0643 };
0644 i2c@5 {
0645 #address-cells = <1>;
0646 #size-cells = <0>;
0647 reg = <5>;
0648 /* SEP 2 */
0649 };
0650 i2c@6 {
0651 #address-cells = <1>;
0652 #size-cells = <0>;
0653 reg = <6>;
0654 /* SEP 1 */
0655 };
0656 i2c@7 {
0657 #address-cells = <1>;
0658 #size-cells = <0>;
0659 reg = <7>;
0660 /* SEP 0 */
0661 };
0662 };
0663 };
0664
0665 &pinctrl0 {
0666 status = "okay";
0667 pinctrl_i2c0_default: i2c0-default {
0668 mux {
0669 groups = "i2c0_3_grp";
0670 function = "i2c0";
0671 };
0672
0673 conf {
0674 groups = "i2c0_3_grp";
0675 bias-pull-up;
0676 slew-rate = <SLEW_RATE_SLOW>;
0677 power-source = <IO_STANDARD_LVCMOS18>;
0678 };
0679 };
0680
0681 pinctrl_i2c0_gpio: i2c0-gpio {
0682 mux {
0683 groups = "gpio0_14_grp", "gpio0_15_grp";
0684 function = "gpio0";
0685 };
0686
0687 conf {
0688 groups = "gpio0_14_grp", "gpio0_15_grp";
0689 slew-rate = <SLEW_RATE_SLOW>;
0690 power-source = <IO_STANDARD_LVCMOS18>;
0691 };
0692 };
0693
0694 pinctrl_i2c1_default: i2c1-default {
0695 mux {
0696 groups = "i2c1_4_grp";
0697 function = "i2c1";
0698 };
0699
0700 conf {
0701 groups = "i2c1_4_grp";
0702 bias-pull-up;
0703 slew-rate = <SLEW_RATE_SLOW>;
0704 power-source = <IO_STANDARD_LVCMOS18>;
0705 };
0706 };
0707
0708 pinctrl_i2c1_gpio: i2c1-gpio {
0709 mux {
0710 groups = "gpio0_16_grp", "gpio0_17_grp";
0711 function = "gpio0";
0712 };
0713
0714 conf {
0715 groups = "gpio0_16_grp", "gpio0_17_grp";
0716 slew-rate = <SLEW_RATE_SLOW>;
0717 power-source = <IO_STANDARD_LVCMOS18>;
0718 };
0719 };
0720
0721 pinctrl_uart0_default: uart0-default {
0722 mux {
0723 groups = "uart0_4_grp";
0724 function = "uart0";
0725 };
0726
0727 conf {
0728 groups = "uart0_4_grp";
0729 slew-rate = <SLEW_RATE_SLOW>;
0730 power-source = <IO_STANDARD_LVCMOS18>;
0731 };
0732
0733 conf-rx {
0734 pins = "MIO18";
0735 bias-high-impedance;
0736 };
0737
0738 conf-tx {
0739 pins = "MIO19";
0740 bias-disable;
0741 };
0742 };
0743
0744 pinctrl_uart1_default: uart1-default {
0745 mux {
0746 groups = "uart1_5_grp";
0747 function = "uart1";
0748 };
0749
0750 conf {
0751 groups = "uart1_5_grp";
0752 slew-rate = <SLEW_RATE_SLOW>;
0753 power-source = <IO_STANDARD_LVCMOS18>;
0754 };
0755
0756 conf-rx {
0757 pins = "MIO21";
0758 bias-high-impedance;
0759 };
0760
0761 conf-tx {
0762 pins = "MIO20";
0763 bias-disable;
0764 };
0765 };
0766
0767 pinctrl_usb0_default: usb0-default {
0768 mux {
0769 groups = "usb0_0_grp";
0770 function = "usb0";
0771 };
0772
0773 conf {
0774 groups = "usb0_0_grp";
0775 slew-rate = <SLEW_RATE_SLOW>;
0776 power-source = <IO_STANDARD_LVCMOS18>;
0777 };
0778
0779 conf-rx {
0780 pins = "MIO52", "MIO53", "MIO55";
0781 bias-high-impedance;
0782 };
0783
0784 conf-tx {
0785 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0786 "MIO60", "MIO61", "MIO62", "MIO63";
0787 bias-disable;
0788 };
0789 };
0790
0791 pinctrl_gem3_default: gem3-default {
0792 mux {
0793 function = "ethernet3";
0794 groups = "ethernet3_0_grp";
0795 };
0796
0797 conf {
0798 groups = "ethernet3_0_grp";
0799 slew-rate = <SLEW_RATE_SLOW>;
0800 power-source = <IO_STANDARD_LVCMOS18>;
0801 };
0802
0803 conf-rx {
0804 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0805 "MIO75";
0806 bias-high-impedance;
0807 low-power-disable;
0808 };
0809
0810 conf-tx {
0811 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0812 "MIO69";
0813 bias-disable;
0814 low-power-enable;
0815 };
0816
0817 mux-mdio {
0818 function = "mdio3";
0819 groups = "mdio3_0_grp";
0820 };
0821
0822 conf-mdio {
0823 groups = "mdio3_0_grp";
0824 slew-rate = <SLEW_RATE_SLOW>;
0825 power-source = <IO_STANDARD_LVCMOS18>;
0826 bias-disable;
0827 };
0828 };
0829
0830 pinctrl_can1_default: can1-default {
0831 mux {
0832 function = "can1";
0833 groups = "can1_6_grp";
0834 };
0835
0836 conf {
0837 groups = "can1_6_grp";
0838 slew-rate = <SLEW_RATE_SLOW>;
0839 power-source = <IO_STANDARD_LVCMOS18>;
0840 };
0841
0842 conf-rx {
0843 pins = "MIO25";
0844 bias-high-impedance;
0845 };
0846
0847 conf-tx {
0848 pins = "MIO24";
0849 bias-disable;
0850 };
0851 };
0852
0853 pinctrl_sdhci1_default: sdhci1-default {
0854 mux {
0855 groups = "sdio1_0_grp";
0856 function = "sdio1";
0857 };
0858
0859 conf {
0860 groups = "sdio1_0_grp";
0861 slew-rate = <SLEW_RATE_SLOW>;
0862 power-source = <IO_STANDARD_LVCMOS18>;
0863 bias-disable;
0864 };
0865
0866 mux-cd {
0867 groups = "sdio1_cd_0_grp";
0868 function = "sdio1_cd";
0869 };
0870
0871 conf-cd {
0872 groups = "sdio1_cd_0_grp";
0873 bias-high-impedance;
0874 bias-pull-up;
0875 slew-rate = <SLEW_RATE_SLOW>;
0876 power-source = <IO_STANDARD_LVCMOS18>;
0877 };
0878
0879 mux-wp {
0880 groups = "sdio1_wp_0_grp";
0881 function = "sdio1_wp";
0882 };
0883
0884 conf-wp {
0885 groups = "sdio1_wp_0_grp";
0886 bias-high-impedance;
0887 bias-pull-up;
0888 slew-rate = <SLEW_RATE_SLOW>;
0889 power-source = <IO_STANDARD_LVCMOS18>;
0890 };
0891 };
0892
0893 pinctrl_gpio_default: gpio-default {
0894 mux-sw {
0895 function = "gpio0";
0896 groups = "gpio0_22_grp", "gpio0_23_grp";
0897 };
0898
0899 conf-sw {
0900 groups = "gpio0_22_grp", "gpio0_23_grp";
0901 slew-rate = <SLEW_RATE_SLOW>;
0902 power-source = <IO_STANDARD_LVCMOS18>;
0903 };
0904
0905 mux-msp {
0906 function = "gpio0";
0907 groups = "gpio0_13_grp", "gpio0_38_grp";
0908 };
0909
0910 conf-msp {
0911 groups = "gpio0_13_grp", "gpio0_38_grp";
0912 slew-rate = <SLEW_RATE_SLOW>;
0913 power-source = <IO_STANDARD_LVCMOS18>;
0914 };
0915
0916 conf-pull-up {
0917 pins = "MIO22", "MIO23";
0918 bias-pull-up;
0919 };
0920
0921 conf-pull-none {
0922 pins = "MIO13", "MIO38";
0923 bias-disable;
0924 };
0925 };
0926 };
0927
0928 &pcie {
0929 status = "okay";
0930 };
0931
0932 &psgtr {
0933 status = "okay";
0934 /* pcie, sata, usb3, dp */
0935 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
0936 clock-names = "ref0", "ref1", "ref2", "ref3";
0937 };
0938
0939 &qspi {
0940 status = "okay";
0941 flash@0 {
0942 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
0943 #address-cells = <1>;
0944 #size-cells = <1>;
0945 reg = <0x0>;
0946 spi-tx-bus-width = <1>;
0947 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
0948 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0949 };
0950 };
0951
0952 &rtc {
0953 status = "okay";
0954 };
0955
0956 &sata {
0957 status = "okay";
0958 /* SATA OOB timing settings */
0959 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0960 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0961 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0962 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0963 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0964 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0965 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0966 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0967 phy-names = "sata-phy";
0968 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
0969 };
0970
0971 /* SD1 with level shifter */
0972 &sdhci1 {
0973 status = "okay";
0974 /*
0975 * 1.0 revision has level shifter and this property should be
0976 * removed for supporting UHS mode
0977 */
0978 no-1-8-v;
0979 pinctrl-names = "default";
0980 pinctrl-0 = <&pinctrl_sdhci1_default>;
0981 xlnx,mio-bank = <1>;
0982 };
0983
0984 &uart0 {
0985 status = "okay";
0986 pinctrl-names = "default";
0987 pinctrl-0 = <&pinctrl_uart0_default>;
0988 };
0989
0990 &uart1 {
0991 status = "okay";
0992 pinctrl-names = "default";
0993 pinctrl-0 = <&pinctrl_uart1_default>;
0994 };
0995
0996 /* ULPI SMSC USB3320 */
0997 &usb0 {
0998 status = "okay";
0999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_usb0_default>;
1001 phy-names = "usb3-phy";
1002 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1003 };
1004
1005 &dwc3_0 {
1006 status = "okay";
1007 dr_mode = "host";
1008 snps,usb3_lpm_capable;
1009 maximum-speed = "super-speed";
1010 };
1011
1012 &watchdog0 {
1013 status = "okay";
1014 };
1015
1016 &zynqmp_dpdma {
1017 status = "okay";
1018 };
1019
1020 &zynqmp_dpsub {
1021 status = "okay";
1022 phy-names = "dp-phy0";
1023 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1024 };
