0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
0004 *
0005 * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006 *
0007 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
0008 * Michal Simek <michal.simek@xilinx.com>
0009 */
0010
0011 /dts-v1/;
0012
0013 #include "zynqmp.dtsi"
0014 #include "zynqmp-clk-ccf.dtsi"
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0017
0018 / {
0019 model = "ZynqMP zc1751-xm019-dc5 RevA";
0020 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
0021
0022 aliases {
0023 ethernet0 = &gem1;
0024 i2c0 = &i2c0;
0025 i2c1 = &i2c1;
0026 mmc0 = &sdhci0;
0027 serial0 = &uart0;
0028 serial1 = &uart1;
0029 };
0030
0031 chosen {
0032 bootargs = "earlycon";
0033 stdout-path = "serial0:115200n8";
0034 };
0035
0036 memory@0 {
0037 device_type = "memory";
0038 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0039 };
0040 };
0041
0042 &fpd_dma_chan1 {
0043 status = "okay";
0044 };
0045
0046 &fpd_dma_chan2 {
0047 status = "okay";
0048 };
0049
0050 &fpd_dma_chan3 {
0051 status = "okay";
0052 };
0053
0054 &fpd_dma_chan4 {
0055 status = "okay";
0056 };
0057
0058 &fpd_dma_chan5 {
0059 status = "okay";
0060 };
0061
0062 &fpd_dma_chan6 {
0063 status = "okay";
0064 };
0065
0066 &fpd_dma_chan7 {
0067 status = "okay";
0068 };
0069
0070 &fpd_dma_chan8 {
0071 status = "okay";
0072 };
0073
0074 &gem1 {
0075 status = "okay";
0076 phy-handle = <&phy0>;
0077 phy-mode = "rgmii-id";
0078 pinctrl-names = "default";
0079 pinctrl-0 = <&pinctrl_gem1_default>;
0080 phy0: ethernet-phy@0 {
0081 reg = <0>;
0082 };
0083 };
0084
0085 &gpio {
0086 status = "okay";
0087 };
0088
0089 &i2c0 {
0090 status = "okay";
0091 pinctrl-names = "default", "gpio";
0092 pinctrl-0 = <&pinctrl_i2c0_default>;
0093 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0094 scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
0095 sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
0096 };
0097
0098 &i2c1 {
0099 status = "okay";
0100 pinctrl-names = "default", "gpio";
0101 pinctrl-0 = <&pinctrl_i2c1_default>;
0102 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0103 scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
0104 sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
0105
0106 };
0107
0108 &pinctrl0 {
0109 status = "okay";
0110 pinctrl_i2c0_default: i2c0-default {
0111 mux {
0112 groups = "i2c0_18_grp";
0113 function = "i2c0";
0114 };
0115
0116 conf {
0117 groups = "i2c0_18_grp";
0118 bias-pull-up;
0119 slew-rate = <SLEW_RATE_SLOW>;
0120 power-source = <IO_STANDARD_LVCMOS18>;
0121 };
0122 };
0123
0124 pinctrl_i2c0_gpio: i2c0-gpio {
0125 mux {
0126 groups = "gpio0_74_grp", "gpio0_75_grp";
0127 function = "gpio0";
0128 };
0129
0130 conf {
0131 groups = "gpio0_74_grp", "gpio0_75_grp";
0132 slew-rate = <SLEW_RATE_SLOW>;
0133 power-source = <IO_STANDARD_LVCMOS18>;
0134 };
0135 };
0136
0137 pinctrl_i2c1_default: i2c1-default {
0138 mux {
0139 groups = "i2c1_19_grp";
0140 function = "i2c1";
0141 };
0142
0143 conf {
0144 groups = "i2c1_19_grp";
0145 bias-pull-up;
0146 slew-rate = <SLEW_RATE_SLOW>;
0147 power-source = <IO_STANDARD_LVCMOS18>;
0148 };
0149 };
0150
0151 pinctrl_i2c1_gpio: i2c1-gpio {
0152 mux {
0153 groups = "gpio0_76_grp", "gpio0_77_grp";
0154 function = "gpio0";
0155 };
0156
0157 conf {
0158 groups = "gpio0_76_grp", "gpio0_77_grp";
0159 slew-rate = <SLEW_RATE_SLOW>;
0160 power-source = <IO_STANDARD_LVCMOS18>;
0161 };
0162 };
0163
0164 pinctrl_uart0_default: uart0-default {
0165 mux {
0166 groups = "uart0_17_grp";
0167 function = "uart0";
0168 };
0169
0170 conf {
0171 groups = "uart0_17_grp";
0172 slew-rate = <SLEW_RATE_SLOW>;
0173 power-source = <IO_STANDARD_LVCMOS18>;
0174 };
0175
0176 conf-rx {
0177 pins = "MIO70";
0178 bias-high-impedance;
0179 };
0180
0181 conf-tx {
0182 pins = "MIO71";
0183 bias-disable;
0184 };
0185 };
0186
0187 pinctrl_uart1_default: uart1-default {
0188 mux {
0189 groups = "uart1_18_grp";
0190 function = "uart1";
0191 };
0192
0193 conf {
0194 groups = "uart1_18_grp";
0195 slew-rate = <SLEW_RATE_SLOW>;
0196 power-source = <IO_STANDARD_LVCMOS18>;
0197 };
0198
0199 conf-rx {
0200 pins = "MIO73";
0201 bias-high-impedance;
0202 };
0203
0204 conf-tx {
0205 pins = "MIO72";
0206 bias-disable;
0207 };
0208 };
0209
0210 pinctrl_gem1_default: gem1-default {
0211 mux {
0212 function = "ethernet1";
0213 groups = "ethernet1_0_grp";
0214 };
0215
0216 conf {
0217 groups = "ethernet1_0_grp";
0218 slew-rate = <SLEW_RATE_SLOW>;
0219 power-source = <IO_STANDARD_LVCMOS18>;
0220 };
0221
0222 conf-rx {
0223 pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
0224 "MIO49";
0225 bias-high-impedance;
0226 low-power-disable;
0227 };
0228
0229 conf-tx {
0230 pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
0231 "MIO43";
0232 bias-disable;
0233 low-power-enable;
0234 };
0235
0236 mux-mdio {
0237 function = "mdio1";
0238 groups = "mdio1_0_grp";
0239 };
0240
0241 conf-mdio {
0242 groups = "mdio1_0_grp";
0243 slew-rate = <SLEW_RATE_SLOW>;
0244 power-source = <IO_STANDARD_LVCMOS18>;
0245 bias-disable;
0246 };
0247 };
0248
0249 pinctrl_sdhci0_default: sdhci0-default {
0250 mux {
0251 groups = "sdio0_0_grp";
0252 function = "sdio0";
0253 };
0254
0255 conf {
0256 groups = "sdio0_0_grp";
0257 slew-rate = <SLEW_RATE_SLOW>;
0258 power-source = <IO_STANDARD_LVCMOS18>;
0259 bias-disable;
0260 };
0261
0262 mux-cd {
0263 groups = "sdio0_cd_0_grp";
0264 function = "sdio0_cd";
0265 };
0266
0267 conf-cd {
0268 groups = "sdio0_cd_0_grp";
0269 bias-high-impedance;
0270 bias-pull-up;
0271 slew-rate = <SLEW_RATE_SLOW>;
0272 power-source = <IO_STANDARD_LVCMOS18>;
0273 };
0274
0275 mux-wp {
0276 groups = "sdio0_wp_0_grp";
0277 function = "sdio0_wp";
0278 };
0279
0280 conf-wp {
0281 groups = "sdio0_wp_0_grp";
0282 bias-high-impedance;
0283 bias-pull-up;
0284 slew-rate = <SLEW_RATE_SLOW>;
0285 power-source = <IO_STANDARD_LVCMOS18>;
0286 };
0287 };
0288
0289 pinctrl_watchdog0_default: watchdog0-default {
0290 mux-clk {
0291 groups = "swdt0_clk_1_grp";
0292 function = "swdt0_clk";
0293 };
0294
0295 conf-clk {
0296 groups = "swdt0_clk_1_grp";
0297 bias-pull-up;
0298 };
0299
0300 mux-rst {
0301 groups = "swdt0_rst_1_grp";
0302 function = "swdt0_rst";
0303 };
0304
0305 conf-rst {
0306 groups = "swdt0_rst_1_grp";
0307 bias-disable;
0308 slew-rate = <SLEW_RATE_SLOW>;
0309 };
0310 };
0311
0312 pinctrl_ttc0_default: ttc0-default {
0313 mux-clk {
0314 groups = "ttc0_clk_0_grp";
0315 function = "ttc0_clk";
0316 };
0317
0318 conf-clk {
0319 groups = "ttc0_clk_0_grp";
0320 bias-pull-up;
0321 };
0322
0323 mux-wav {
0324 groups = "ttc0_wav_0_grp";
0325 function = "ttc0_wav";
0326 };
0327
0328 conf-wav {
0329 groups = "ttc0_wav_0_grp";
0330 bias-disable;
0331 slew-rate = <SLEW_RATE_SLOW>;
0332 };
0333 };
0334
0335 pinctrl_ttc1_default: ttc1-default {
0336 mux-clk {
0337 groups = "ttc1_clk_0_grp";
0338 function = "ttc1_clk";
0339 };
0340
0341 conf-clk {
0342 groups = "ttc1_clk_0_grp";
0343 bias-pull-up;
0344 };
0345
0346 mux-wav {
0347 groups = "ttc1_wav_0_grp";
0348 function = "ttc1_wav";
0349 };
0350
0351 conf-wav {
0352 groups = "ttc1_wav_0_grp";
0353 bias-disable;
0354 slew-rate = <SLEW_RATE_SLOW>;
0355 };
0356 };
0357
0358 pinctrl_ttc2_default: ttc2-default {
0359 mux-clk {
0360 groups = "ttc2_clk_0_grp";
0361 function = "ttc2_clk";
0362 };
0363
0364 conf-clk {
0365 groups = "ttc2_clk_0_grp";
0366 bias-pull-up;
0367 };
0368
0369 mux-wav {
0370 groups = "ttc2_wav_0_grp";
0371 function = "ttc2_wav";
0372 };
0373
0374 conf-wav {
0375 groups = "ttc2_wav_0_grp";
0376 bias-disable;
0377 slew-rate = <SLEW_RATE_SLOW>;
0378 };
0379 };
0380
0381 pinctrl_ttc3_default: ttc3-default {
0382 mux-clk {
0383 groups = "ttc3_clk_0_grp";
0384 function = "ttc3_clk";
0385 };
0386
0387 conf-clk {
0388 groups = "ttc3_clk_0_grp";
0389 bias-pull-up;
0390 };
0391
0392 mux-wav {
0393 groups = "ttc3_wav_0_grp";
0394 function = "ttc3_wav";
0395 };
0396
0397 conf-wav {
0398 groups = "ttc3_wav_0_grp";
0399 bias-disable;
0400 slew-rate = <SLEW_RATE_SLOW>;
0401 };
0402 };
0403 };
0404
0405 &sdhci0 {
0406 status = "okay";
0407 pinctrl-names = "default";
0408 pinctrl-0 = <&pinctrl_sdhci0_default>;
0409 no-1-8-v;
0410 xlnx,mio-bank = <0>;
0411 };
0412
0413 &ttc0 {
0414 status = "okay";
0415 pinctrl-names = "default";
0416 pinctrl-0 = <&pinctrl_ttc0_default>;
0417 };
0418
0419 &ttc1 {
0420 status = "okay";
0421 pinctrl-names = "default";
0422 pinctrl-0 = <&pinctrl_ttc1_default>;
0423 };
0424
0425 &ttc2 {
0426 status = "okay";
0427 pinctrl-names = "default";
0428 pinctrl-0 = <&pinctrl_ttc2_default>;
0429 };
0430
0431 &ttc3 {
0432 status = "okay";
0433 pinctrl-names = "default";
0434 pinctrl-0 = <&pinctrl_ttc3_default>;
0435 };
0436
0437 &uart0 {
0438 status = "okay";
0439 pinctrl-names = "default";
0440 pinctrl-0 = <&pinctrl_uart0_default>;
0441 };
0442
0443 &uart1 {
0444 status = "okay";
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&pinctrl_uart1_default>;
0447 };
0448
0449 &watchdog0 {
0450 status = "okay";
0451 pinctrl-names = "default";
0452 pinctrl-0 = <&pinctrl_watchdog0_default>;
0453 };
