arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
0004  *
0005  * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006  *
0007  * Michal Simek <michal.simek@xilinx.com>
0008  */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014
0015 / {
0016         model = "ZynqMP zc1751-xm018-dc4";
0017         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
0018
0019         aliases {
0020                 ethernet0 = &gem0;
0021                 ethernet1 = &gem1;
0022                 ethernet2 = &gem2;
0023                 ethernet3 = &gem3;
0024                 i2c0 = &i2c0;
0025                 i2c1 = &i2c1;
0026                 rtc0 = &rtc;
0027                 serial0 = &uart0;
0028                 serial1 = &uart1;
0029                 spi0 = &qspi;
0030         };
0031
0032         chosen {
0033                 bootargs = "earlycon";
0034                 stdout-path = "serial0:115200n8";
0035         };
0036
0037         memory@0 {
0038                 device_type = "memory";
0039                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0040         };
0041 };
0042
0043 &can0 {
0044         status = "okay";
0045 };
0046
0047 &can1 {
0048         status = "okay";
0049 };
0050
0051 &fpd_dma_chan1 {
0052         status = "okay";
0053 };
0054
0055 &fpd_dma_chan2 {
0056         status = "okay";
0057 };
0058
0059 &fpd_dma_chan3 {
0060         status = "okay";
0061 };
0062
0063 &fpd_dma_chan4 {
0064         status = "okay";
0065 };
0066
0067 &fpd_dma_chan5 {
0068         status = "okay";
0069 };
0070
0071 &fpd_dma_chan6 {
0072         status = "okay";
0073 };
0074
0075 &fpd_dma_chan7 {
0076         status = "okay";
0077 };
0078
0079 &fpd_dma_chan8 {
0080         status = "okay";
0081 };
0082
0083 &lpd_dma_chan1 {
0084         status = "okay";
0085 };
0086
0087 &lpd_dma_chan2 {
0088         status = "okay";
0089 };
0090
0091 &lpd_dma_chan3 {
0092         status = "okay";
0093 };
0094
0095 &lpd_dma_chan4 {
0096         status = "okay";
0097 };
0098
0099 &lpd_dma_chan5 {
0100         status = "okay";
0101 };
0102
0103 &lpd_dma_chan6 {
0104         status = "okay";
0105 };
0106
0107 &lpd_dma_chan7 {
0108         status = "okay";
0109 };
0110
0111 &lpd_dma_chan8 {
0112         status = "okay";
0113 };
0114
0115 &gem0 {
0116         status = "okay";
0117         phy-mode = "rgmii-id";
0118         phy-handle = <&ethernet_phy0>;
0119         ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
0120                 reg = <0>;
0121         };
0122         ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
0123                 reg = <7>;
0124         };
0125         ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
0126                 reg = <3>;
0127         };
0128         ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
0129                 reg = <8>;
0130         };
0131 };
0132
0133 &gem1 {
0134         status = "okay";
0135         phy-mode = "rgmii-id";
0136         phy-handle = <&ethernet_phy7>;
0137 };
0138
0139 &gem2 {
0140         status = "okay";
0141         phy-mode = "rgmii-id";
0142         phy-handle = <&ethernet_phy3>;
0143 };
0144
0145 &gem3 {
0146         status = "okay";
0147         phy-mode = "rgmii-id";
0148         phy-handle = <&ethernet_phy8>;
0149 };
0150
0151 &gpio {
0152         status = "okay";
0153 };
0154
0155 &i2c0 {
0156         clock-frequency = <400000>;
0157         status = "okay";
0158 };
0159
0160 &i2c1 {
0161         clock-frequency = <400000>;
0162         status = "okay";
0163 };
0164
0165 &qspi {
0166         status = "okay";
0167         flash@0 {
0168                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
0169                 #address-cells = <1>;
0170                 #size-cells = <1>;
0171                 reg = <0x0>;
0172                 spi-tx-bus-width = <1>;
0173                 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
0174                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0175         };
0176 };
0177
0178 &rtc {
0179         status = "okay";
0180 };
0181
0182 &uart0 {
0183         status = "okay";
0184 };
0185
0186 &uart1 {
0187         status = "okay";
0188 };
0189
0190 &watchdog0 {
0191         status = "okay";
0192 };
0193
0194 &zynqmp_dpdma {
0195         status = "okay";
0196 };
0197
0198 &zynqmp_dpsub {
0199         status = "okay";
0200 };