0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
0004 *
0005 * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/phy/phy.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0017
0018 / {
0019 model = "ZynqMP zc1751-xm015-dc1 RevA";
0020 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
0021
0022 aliases {
0023 ethernet0 = &gem3;
0024 i2c0 = &i2c1;
0025 mmc0 = &sdhci0;
0026 mmc1 = &sdhci1;
0027 rtc0 = &rtc;
0028 serial0 = &uart0;
0029 spi0 = &qspi;
0030 usb0 = &usb0;
0031 };
0032
0033 chosen {
0034 bootargs = "earlycon";
0035 stdout-path = "serial0:115200n8";
0036 };
0037
0038 memory@0 {
0039 device_type = "memory";
0040 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0041 };
0042
0043 clock_si5338_0: clk27 { /* u55 SI5338-GM */
0044 compatible = "fixed-clock";
0045 #clock-cells = <0>;
0046 clock-frequency = <27000000>;
0047 };
0048
0049 clock_si5338_2: clk26 {
0050 compatible = "fixed-clock";
0051 #clock-cells = <0>;
0052 clock-frequency = <26000000>;
0053 };
0054
0055 clock_si5338_3: clk150 {
0056 compatible = "fixed-clock";
0057 #clock-cells = <0>;
0058 clock-frequency = <150000000>;
0059 };
0060 };
0061
0062 &fpd_dma_chan1 {
0063 status = "okay";
0064 };
0065
0066 &fpd_dma_chan2 {
0067 status = "okay";
0068 };
0069
0070 &fpd_dma_chan3 {
0071 status = "okay";
0072 };
0073
0074 &fpd_dma_chan4 {
0075 status = "okay";
0076 };
0077
0078 &fpd_dma_chan5 {
0079 status = "okay";
0080 };
0081
0082 &fpd_dma_chan6 {
0083 status = "okay";
0084 };
0085
0086 &fpd_dma_chan7 {
0087 status = "okay";
0088 };
0089
0090 &fpd_dma_chan8 {
0091 status = "okay";
0092 };
0093
0094 &gem3 {
0095 status = "okay";
0096 phy-handle = <&phy0>;
0097 phy-mode = "rgmii-id";
0098 pinctrl-names = "default";
0099 pinctrl-0 = <&pinctrl_gem3_default>;
0100 phy0: ethernet-phy@0 {
0101 reg = <0>;
0102 };
0103 };
0104
0105 &gpio {
0106 status = "okay";
0107 pinctrl-names = "default";
0108 pinctrl-0 = <&pinctrl_gpio_default>;
0109 };
0110
0111
0112 &i2c1 {
0113 status = "okay";
0114 clock-frequency = <400000>;
0115 pinctrl-names = "default", "gpio";
0116 pinctrl-0 = <&pinctrl_i2c1_default>;
0117 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0118 scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
0119 sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
0120
0121 eeprom: eeprom@55 {
0122 compatible = "atmel,24c64"; /* 24AA64 */
0123 reg = <0x55>;
0124 };
0125 };
0126
0127 &pinctrl0 {
0128 status = "okay";
0129 pinctrl_i2c1_default: i2c1-default {
0130 mux {
0131 groups = "i2c1_9_grp";
0132 function = "i2c1";
0133 };
0134
0135 conf {
0136 groups = "i2c1_9_grp";
0137 bias-pull-up;
0138 slew-rate = <SLEW_RATE_SLOW>;
0139 power-source = <IO_STANDARD_LVCMOS18>;
0140 };
0141 };
0142
0143 pinctrl_i2c1_gpio: i2c1-gpio {
0144 mux {
0145 groups = "gpio0_36_grp", "gpio0_37_grp";
0146 function = "gpio0";
0147 };
0148
0149 conf {
0150 groups = "gpio0_36_grp", "gpio0_37_grp";
0151 slew-rate = <SLEW_RATE_SLOW>;
0152 power-source = <IO_STANDARD_LVCMOS18>;
0153 };
0154 };
0155
0156 pinctrl_uart0_default: uart0-default {
0157 mux {
0158 groups = "uart0_8_grp";
0159 function = "uart0";
0160 };
0161
0162 conf {
0163 groups = "uart0_8_grp";
0164 slew-rate = <SLEW_RATE_SLOW>;
0165 power-source = <IO_STANDARD_LVCMOS18>;
0166 };
0167
0168 conf-rx {
0169 pins = "MIO34";
0170 bias-high-impedance;
0171 };
0172
0173 conf-tx {
0174 pins = "MIO35";
0175 bias-disable;
0176 };
0177 };
0178
0179 pinctrl_usb0_default: usb0-default {
0180 mux {
0181 groups = "usb0_0_grp";
0182 function = "usb0";
0183 };
0184
0185 conf {
0186 groups = "usb0_0_grp";
0187 slew-rate = <SLEW_RATE_SLOW>;
0188 power-source = <IO_STANDARD_LVCMOS18>;
0189 };
0190
0191 conf-rx {
0192 pins = "MIO52", "MIO53", "MIO55";
0193 bias-high-impedance;
0194 };
0195
0196 conf-tx {
0197 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0198 "MIO60", "MIO61", "MIO62", "MIO63";
0199 bias-disable;
0200 };
0201 };
0202
0203 pinctrl_gem3_default: gem3-default {
0204 mux {
0205 function = "ethernet3";
0206 groups = "ethernet3_0_grp";
0207 };
0208
0209 conf {
0210 groups = "ethernet3_0_grp";
0211 slew-rate = <SLEW_RATE_SLOW>;
0212 power-source = <IO_STANDARD_LVCMOS18>;
0213 };
0214
0215 conf-rx {
0216 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
0217 "MIO75";
0218 bias-high-impedance;
0219 low-power-disable;
0220 };
0221
0222 conf-tx {
0223 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
0224 "MIO69";
0225 bias-disable;
0226 low-power-enable;
0227 };
0228
0229 mux-mdio {
0230 function = "mdio3";
0231 groups = "mdio3_0_grp";
0232 };
0233
0234 conf-mdio {
0235 groups = "mdio3_0_grp";
0236 slew-rate = <SLEW_RATE_SLOW>;
0237 power-source = <IO_STANDARD_LVCMOS18>;
0238 bias-disable;
0239 };
0240 };
0241
0242 pinctrl_sdhci0_default: sdhci0-default {
0243 mux {
0244 groups = "sdio0_0_grp";
0245 function = "sdio0";
0246 };
0247
0248 conf {
0249 groups = "sdio0_0_grp";
0250 slew-rate = <SLEW_RATE_SLOW>;
0251 power-source = <IO_STANDARD_LVCMOS18>;
0252 bias-disable;
0253 };
0254
0255 mux-cd {
0256 groups = "sdio0_cd_0_grp";
0257 function = "sdio0_cd";
0258 };
0259
0260 conf-cd {
0261 groups = "sdio0_cd_0_grp";
0262 bias-high-impedance;
0263 bias-pull-up;
0264 slew-rate = <SLEW_RATE_SLOW>;
0265 power-source = <IO_STANDARD_LVCMOS18>;
0266 };
0267
0268 mux-wp {
0269 groups = "sdio0_wp_0_grp";
0270 function = "sdio0_wp";
0271 };
0272
0273 conf-wp {
0274 groups = "sdio0_wp_0_grp";
0275 bias-high-impedance;
0276 bias-pull-up;
0277 slew-rate = <SLEW_RATE_SLOW>;
0278 power-source = <IO_STANDARD_LVCMOS18>;
0279 };
0280 };
0281
0282 pinctrl_sdhci1_default: sdhci1-default {
0283 mux {
0284 groups = "sdio1_0_grp";
0285 function = "sdio1";
0286 };
0287
0288 conf {
0289 groups = "sdio1_0_grp";
0290 slew-rate = <SLEW_RATE_SLOW>;
0291 power-source = <IO_STANDARD_LVCMOS18>;
0292 bias-disable;
0293 };
0294
0295 mux-cd {
0296 groups = "sdio1_cd_0_grp";
0297 function = "sdio1_cd";
0298 };
0299
0300 conf-cd {
0301 groups = "sdio1_cd_0_grp";
0302 bias-high-impedance;
0303 bias-pull-up;
0304 slew-rate = <SLEW_RATE_SLOW>;
0305 power-source = <IO_STANDARD_LVCMOS18>;
0306 };
0307
0308 mux-wp {
0309 groups = "sdio1_wp_0_grp";
0310 function = "sdio1_wp";
0311 };
0312
0313 conf-wp {
0314 groups = "sdio1_wp_0_grp";
0315 bias-high-impedance;
0316 bias-pull-up;
0317 slew-rate = <SLEW_RATE_SLOW>;
0318 power-source = <IO_STANDARD_LVCMOS18>;
0319 };
0320 };
0321
0322 pinctrl_gpio_default: gpio-default {
0323 mux {
0324 function = "gpio0";
0325 groups = "gpio0_38_grp";
0326 };
0327
0328 conf {
0329 groups = "gpio0_38_grp";
0330 bias-disable;
0331 slew-rate = <SLEW_RATE_SLOW>;
0332 power-source = <IO_STANDARD_LVCMOS18>;
0333 };
0334 };
0335 };
0336
0337 &psgtr {
0338 status = "okay";
0339 /* dp, usb3, sata */
0340 clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
0341 clock-names = "ref1", "ref2", "ref3";
0342 };
0343
0344 &qspi {
0345 status = "okay";
0346 flash@0 {
0347 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
0348 #address-cells = <1>;
0349 #size-cells = <1>;
0350 reg = <0x0>;
0351 spi-tx-bus-width = <1>;
0352 spi-rx-bus-width = <4>;
0353 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0354 };
0355 };
0356
0357 &rtc {
0358 status = "okay";
0359 };
0360
0361 &sata {
0362 status = "okay";
0363 /* SATA phy OOB timing settings */
0364 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
0365 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
0366 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0367 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0368 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
0369 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
0370 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0371 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0372 phy-names = "sata-phy";
0373 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
0374 };
0375
0376 /* eMMC */
0377 &sdhci0 {
0378 status = "okay";
0379 pinctrl-names = "default";
0380 pinctrl-0 = <&pinctrl_sdhci0_default>;
0381 bus-width = <8>;
0382 xlnx,mio-bank = <0>;
0383 };
0384
0385 /* SD1 with level shifter */
0386 &sdhci1 {
0387 status = "okay";
0388 /*
0389 * This property should be removed for supporting UHS mode
0390 */
0391 no-1-8-v;
0392 pinctrl-names = "default";
0393 pinctrl-0 = <&pinctrl_sdhci1_default>;
0394 xlnx,mio-bank = <1>;
0395 };
0396
0397 &uart0 {
0398 status = "okay";
0399 pinctrl-names = "default";
0400 pinctrl-0 = <&pinctrl_uart0_default>;
0401 };
0402
0403 /* ULPI SMSC USB3320 */
0404 &usb0 {
0405 status = "okay";
0406 pinctrl-names = "default";
0407 pinctrl-0 = <&pinctrl_usb0_default>;
0408 phy-names = "usb3-phy";
0409 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
0410 };
0411
0412 &dwc3_0 {
0413 status = "okay";
0414 dr_mode = "host";
0415 snps,usb3_lpm_capable;
0416 maximum-speed = "super-speed";
0417 };
0418
0419 &zynqmp_dpdma {
0420 status = "okay";
0421 };
0422
0423 &zynqmp_dpsub {
0424 status = "okay";
0425 phy-names = "dp-phy0", "dp-phy1";
0426 phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
0427 <&psgtr 0 PHY_TYPE_DP 1 1>;
0428 };
