arm64/xilinx/zynqmp-zc1254-revA.dts

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * dts file for Xilinx ZynqMP ZC1254
0004  *
0005  * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006  *
0007  * Michal Simek <michal.simek@xilinx.com>
0008  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
0009  */
0010
0011 /dts-v1/;
0012
0013 #include "zynqmp.dtsi"
0014 #include "zynqmp-clk-ccf.dtsi"
0015
0016 / {
0017         model = "ZynqMP ZC1254 RevA";
0018         compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
0019
0020         aliases {
0021                 serial0 = &uart0;
0022                 serial1 = &dcc;
0023                 spi0 = &qspi;
0024         };
0025
0026         chosen {
0027                 bootargs = "earlycon";
0028                 stdout-path = "serial0:115200n8";
0029         };
0030
0031         memory@0 {
0032                 device_type = "memory";
0033                 reg = <0x0 0x0 0x0 0x80000000>;
0034         };
0035 };
0036
0037 &dcc {
0038         status = "okay";
0039 };
0040
0041 &qspi {
0042         status = "okay";
0043         flash@0 {
0044                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
0045                 #address-cells = <1>;
0046                 #size-cells = <1>;
0047                 reg = <0x0>;
0048                 spi-tx-bus-width = <1>;
0049                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
0050                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0051         };
0052 };
0053
0054 &uart0 {
0055         status = "okay";
0056 };