0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP ZC1232
0004 *
0005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014
0015 / {
0016 model = "ZynqMP ZC1232 RevA";
0017 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
0018
0019 aliases {
0020 serial0 = &uart0;
0021 serial1 = &dcc;
0022 spi0 = &qspi;
0023 };
0024
0025 chosen {
0026 bootargs = "earlycon";
0027 stdout-path = "serial0:115200n8";
0028 };
0029
0030 memory@0 {
0031 device_type = "memory";
0032 reg = <0x0 0x0 0x0 0x80000000>;
0033 };
0034 };
0035
0036 &dcc {
0037 status = "okay";
0038 };
0039
0040 &qspi {
0041 status = "okay";
0042 flash@0 {
0043 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 reg = <0x0>;
0047 spi-tx-bus-width = <1>;
0048 spi-rx-bus-width = <4>;
0049 spi-max-frequency = <108000000>; /* Based on DC1 spec */
0050 };
0051 };
0052
0053 &sata {
0054 status = "okay";
0055 /* SATA OOB timing settings */
0056 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0057 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0058 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0059 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0060 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0061 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0062 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0063 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0064 };
0065
0066 &uart0 {
0067 status = "okay";
0068 };
