0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
0004 *
0005 * (C) Copyright 2020 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/input/input.h>
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/phy/phy.h>
0017
0018 / {
0019 model = "ZynqMP SM-K26 Rev1/B/A";
0020 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
0021 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
0022 "xlnx,zynqmp";
0023
0024 aliases {
0025 i2c0 = &i2c0;
0026 i2c1 = &i2c1;
0027 mmc0 = &sdhci0;
0028 mmc1 = &sdhci1;
0029 nvmem0 = &eeprom;
0030 nvmem1 = &eeprom_cc;
0031 rtc0 = &rtc;
0032 serial0 = &uart0;
0033 serial1 = &uart1;
0034 serial2 = &dcc;
0035 spi0 = &qspi;
0036 spi1 = &spi0;
0037 spi2 = &spi1;
0038 usb0 = &usb0;
0039 usb1 = &usb1;
0040 };
0041
0042 chosen {
0043 bootargs = "earlycon";
0044 stdout-path = "serial1:115200n8";
0045 };
0046
0047 memory@0 {
0048 device_type = "memory"; /* 4GB */
0049 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0050 };
0051
0052 gpio-keys {
0053 compatible = "gpio-keys";
0054 autorepeat;
0055 key-fwuen {
0056 label = "fwuen";
0057 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
0058 };
0059 };
0060
0061 leds {
0062 compatible = "gpio-leds";
0063 ds35-led {
0064 label = "heartbeat";
0065 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
0066 linux,default-trigger = "heartbeat";
0067 };
0068
0069 ds36-led {
0070 label = "vbus_det";
0071 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
0072 default-state = "on";
0073 };
0074 };
0075 };
0076
0077 &uart1 { /* MIO36/MIO37 */
0078 status = "okay";
0079 };
0080
0081 &qspi { /* MIO 0-5 - U143 */
0082 status = "okay";
0083 flash@0 { /* MT25QU512A */
0084 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
0085 #address-cells = <1>;
0086 #size-cells = <1>;
0087 reg = <0>;
0088 spi-tx-bus-width = <1>;
0089 spi-rx-bus-width = <4>;
0090 spi-max-frequency = <40000000>; /* 40MHz */
0091 partition@0 {
0092 label = "Image Selector";
0093 reg = <0x0 0x80000>; /* 512KB */
0094 read-only;
0095 lock;
0096 };
0097 partition@80000 {
0098 label = "Image Selector Golden";
0099 reg = <0x80000 0x80000>; /* 512KB */
0100 read-only;
0101 lock;
0102 };
0103 partition@100000 {
0104 label = "Persistent Register";
0105 reg = <0x100000 0x20000>; /* 128KB */
0106 };
0107 partition@120000 {
0108 label = "Persistent Register Backup";
0109 reg = <0x120000 0x20000>; /* 128KB */
0110 };
0111 partition@140000 {
0112 label = "Open_1";
0113 reg = <0x140000 0xC0000>; /* 768KB */
0114 };
0115 partition@200000 {
0116 label = "Image A (FSBL, PMU, ATF, U-Boot)";
0117 reg = <0x200000 0xD00000>; /* 13MB */
0118 };
0119 partition@f00000 {
0120 label = "ImgSel Image A Catch";
0121 reg = <0xF00000 0x80000>; /* 512KB */
0122 read-only;
0123 lock;
0124 };
0125 partition@f80000 {
0126 label = "Image B (FSBL, PMU, ATF, U-Boot)";
0127 reg = <0xF80000 0xD00000>; /* 13MB */
0128 };
0129 partition@1c80000 {
0130 label = "ImgSel Image B Catch";
0131 reg = <0x1C80000 0x80000>; /* 512KB */
0132 read-only;
0133 lock;
0134 };
0135 partition@1d00000 {
0136 label = "Open_2";
0137 reg = <0x1D00000 0x100000>; /* 1MB */
0138 };
0139 partition@1e00000 {
0140 label = "Recovery Image";
0141 reg = <0x1E00000 0x200000>; /* 2MB */
0142 read-only;
0143 lock;
0144 };
0145 partition@2000000 {
0146 label = "Recovery Image Backup";
0147 reg = <0x2000000 0x200000>; /* 2MB */
0148 read-only;
0149 lock;
0150 };
0151 partition@2200000 {
0152 label = "U-Boot storage variables";
0153 reg = <0x2200000 0x20000>; /* 128KB */
0154 };
0155 partition@2220000 {
0156 label = "U-Boot storage variables backup";
0157 reg = <0x2220000 0x20000>; /* 128KB */
0158 };
0159 partition@2240000 {
0160 label = "SHA256";
0161 reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
0162 read-only;
0163 lock;
0164 };
0165 partition@2250000 {
0166 label = "User";
0167 reg = <0x2250000 0x1db0000>; /* 29.5 MB */
0168 };
0169 };
0170 };
0171
0172 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
0173 status = "okay";
0174 non-removable;
0175 disable-wp;
0176 bus-width = <8>;
0177 xlnx,mio-bank = <0>;
0178 };
0179
0180 &spi1 { /* MIO6, 9-11 */
0181 status = "okay";
0182 label = "TPM";
0183 num-cs = <1>;
0184 tpm@0 { /* slm9670 - U144 */
0185 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
0186 reg = <0>;
0187 spi-max-frequency = <18500000>;
0188 };
0189 };
0190
0191 &i2c1 {
0192 status = "okay";
0193 clock-frequency = <400000>;
0194 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
0195 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
0196
0197 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
0198 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
0199 reg = <0x50>;
0200 /* WP pin EE_WP_EN connected to slg7x644092@68 */
0201 };
0202
0203 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
0204 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
0205 reg = <0x51>;
0206 };
0207
0208 /* da9062@30 - u170 - also at address 0x31 */
0209 /* da9131@33 - u167 */
0210 da9131: pmic@33 {
0211 compatible = "dlg,da9131";
0212 reg = <0x33>;
0213 regulators {
0214 da9131_buck1: buck1 {
0215 regulator-name = "da9131_buck1";
0216 regulator-boot-on;
0217 regulator-always-on;
0218 };
0219 da9131_buck2: buck2 {
0220 regulator-name = "da9131_buck2";
0221 regulator-boot-on;
0222 regulator-always-on;
0223 };
0224 };
0225 };
0226
0227 /* da9130@32 - u166 */
0228 da9130: pmic@32 {
0229 compatible = "dlg,da9130";
0230 reg = <0x32>;
0231 regulators {
0232 da9130_buck1: buck1 {
0233 regulator-name = "da9130_buck1";
0234 regulator-boot-on;
0235 regulator-always-on;
0236 };
0237 };
0238 };
0239
0240 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
0241 /*
0242 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
0243 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
0244 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
0245 * With the FW fix, stdp4320 should respond to address 0x73 only.
0246 */
0247 /* slg7x644092@68 - u169 */
0248 /* Also connected via JA1C as C23/C24 */
0249 };
0250
0251 &gpio {
0252 status = "okay";
0253 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
0254 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
0255 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
0256 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
0257 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
0258 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
0259 "", "", "", "", "", /* 30 - 34 */
0260 "", "", "", "", "", /* 35 - 39 */
0261 "", "", "", "", "", /* 40 - 44 */
0262 "", "", "", "", "", /* 45 - 49 */
0263 "", "", "", "", "", /* 50 - 54 */
0264 "", "", "", "", "", /* 55 - 59 */
0265 "", "", "", "", "", /* 60 - 64 */
0266 "", "", "", "", "", /* 65 - 69 */
0267 "", "", "", "", "", /* 70 - 74 */
0268 "", "", "", /* 75 - 77, MIO end and EMIO start */
0269 "", "", /* 78 - 79 */
0270 "", "", "", "", "", /* 80 - 84 */
0271 "", "", "", "", "", /* 85 - 89 */
0272 "", "", "", "", "", /* 90 - 94 */
0273 "", "", "", "", "", /* 95 - 99 */
0274 "", "", "", "", "", /* 100 - 104 */
0275 "", "", "", "", "", /* 105 - 109 */
0276 "", "", "", "", "", /* 110 - 114 */
0277 "", "", "", "", "", /* 115 - 119 */
0278 "", "", "", "", "", /* 120 - 124 */
0279 "", "", "", "", "", /* 125 - 129 */
0280 "", "", "", "", "", /* 130 - 134 */
0281 "", "", "", "", "", /* 135 - 139 */
0282 "", "", "", "", "", /* 140 - 144 */
0283 "", "", "", "", "", /* 145 - 149 */
0284 "", "", "", "", "", /* 150 - 154 */
0285 "", "", "", "", "", /* 155 - 159 */
0286 "", "", "", "", "", /* 160 - 164 */
0287 "", "", "", "", "", /* 165 - 169 */
0288 "", "", "", ""; /* 170 - 173 */
0289 };
