0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * dts file for KV260 revA Carrier Card
0004 *
0005 * (C) Copyright 2020 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/net/ti-dp83867.h>
0012 #include <dt-bindings/phy/phy.h>
0013 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0014
0015 /dts-v1/;
0016 /plugin/;
0017
0018 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021 pinctrl-names = "default", "gpio";
0022 pinctrl-0 = <&pinctrl_i2c1_default>;
0023 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0024 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
0025 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
0026
0027 /* u14 - 0x40 - ina260 */
0028 /* u43 - 0x2d - usb5744 */
0029 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
0030 };
0031
0032 &amba {
0033 si5332_0: si5332_0 { /* u17 */
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <125000000>;
0037 };
0038
0039 si5332_1: si5332_1 { /* u17 */
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <25000000>;
0043 };
0044
0045 si5332_2: si5332_2 { /* u17 */
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <48000000>;
0049 };
0050
0051 si5332_3: si5332_3 { /* u17 */
0052 compatible = "fixed-clock";
0053 #clock-cells = <0>;
0054 clock-frequency = <24000000>;
0055 };
0056
0057 si5332_4: si5332_4 { /* u17 */
0058 compatible = "fixed-clock";
0059 #clock-cells = <0>;
0060 clock-frequency = <26000000>;
0061 };
0062
0063 si5332_5: si5332_5 { /* u17 */
0064 compatible = "fixed-clock";
0065 #clock-cells = <0>;
0066 clock-frequency = <27000000>;
0067 };
0068 };
0069
0070 /* DP/USB 3.0 */
0071 &psgtr {
0072 status = "okay";
0073 /* pcie, usb3, sata */
0074 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
0075 clock-names = "ref0", "ref1", "ref2";
0076 };
0077
0078 &zynqmp_dpsub {
0079 status = "disabled";
0080 phy-names = "dp-phy0", "dp-phy1";
0081 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
0082 };
0083
0084 &zynqmp_dpdma {
0085 status = "okay";
0086 };
0087
0088 &usb0 {
0089 status = "okay";
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&pinctrl_usb0_default>;
0092 phy-names = "usb3-phy";
0093 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
0094 };
0095
0096 &dwc3_0 {
0097 status = "okay";
0098 dr_mode = "host";
0099 snps,usb3_lpm_capable;
0100 maximum-speed = "super-speed";
0101 };
0102
0103 &sdhci1 { /* on CC with tuned parameters */
0104 status = "okay";
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_sdhci1_default>;
0107 /*
0108 * SD 3.0 requires level shifter and this property
0109 * should be removed if the board has level shifter and
0110 * need to work in UHS mode
0111 */
0112 no-1-8-v;
0113 disable-wp;
0114 xlnx,mio-bank = <1>;
0115 clk-phase-sd-hs = <126>, <60>;
0116 clk-phase-uhs-sdr25 = <120>, <60>;
0117 clk-phase-uhs-ddr50 = <126>, <48>;
0118 };
0119
0120 &gem3 { /* required by spec */
0121 status = "okay";
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&pinctrl_gem3_default>;
0124 phy-handle = <&phy0>;
0125 phy-mode = "rgmii-id";
0126
0127 mdio: mdio {
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
0131 reset-delay-us = <2>;
0132
0133 phy0: ethernet-phy@1 {
0134 #phy-cells = <1>;
0135 reg = <1>;
0136 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0137 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
0138 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0139 ti,dp83867-rxctrl-strap-quirk;
0140 };
0141 };
0142 };
0143
0144 &pinctrl0 { /* required by spec */
0145 status = "okay";
0146
0147 pinctrl_uart1_default: uart1-default {
0148 conf {
0149 groups = "uart1_9_grp";
0150 slew-rate = <SLEW_RATE_SLOW>;
0151 power-source = <IO_STANDARD_LVCMOS18>;
0152 drive-strength = <12>;
0153 };
0154
0155 conf-rx {
0156 pins = "MIO37";
0157 bias-high-impedance;
0158 };
0159
0160 conf-tx {
0161 pins = "MIO36";
0162 bias-disable;
0163 };
0164
0165 mux {
0166 groups = "uart1_9_grp";
0167 function = "uart1";
0168 };
0169 };
0170
0171 pinctrl_i2c1_default: i2c1-default {
0172 conf {
0173 groups = "i2c1_6_grp";
0174 bias-pull-up;
0175 slew-rate = <SLEW_RATE_SLOW>;
0176 power-source = <IO_STANDARD_LVCMOS18>;
0177 };
0178
0179 mux {
0180 groups = "i2c1_6_grp";
0181 function = "i2c1";
0182 };
0183 };
0184
0185 pinctrl_i2c1_gpio: i2c1-gpio {
0186 conf {
0187 groups = "gpio0_24_grp", "gpio0_25_grp";
0188 slew-rate = <SLEW_RATE_SLOW>;
0189 power-source = <IO_STANDARD_LVCMOS18>;
0190 };
0191
0192 mux {
0193 groups = "gpio0_24_grp", "gpio0_25_grp";
0194 function = "gpio0";
0195 };
0196 };
0197
0198 pinctrl_gem3_default: gem3-default {
0199 conf {
0200 groups = "ethernet3_0_grp";
0201 slew-rate = <SLEW_RATE_SLOW>;
0202 power-source = <IO_STANDARD_LVCMOS18>;
0203 };
0204
0205 conf-rx {
0206 pins = "MIO70", "MIO72", "MIO74";
0207 bias-high-impedance;
0208 low-power-disable;
0209 };
0210
0211 conf-bootstrap {
0212 pins = "MIO71", "MIO73", "MIO75";
0213 bias-disable;
0214 low-power-disable;
0215 };
0216
0217 conf-tx {
0218 pins = "MIO64", "MIO65", "MIO66",
0219 "MIO67", "MIO68", "MIO69";
0220 bias-disable;
0221 low-power-enable;
0222 };
0223
0224 conf-mdio {
0225 groups = "mdio3_0_grp";
0226 slew-rate = <SLEW_RATE_SLOW>;
0227 power-source = <IO_STANDARD_LVCMOS18>;
0228 bias-disable;
0229 };
0230
0231 mux-mdio {
0232 function = "mdio3";
0233 groups = "mdio3_0_grp";
0234 };
0235
0236 mux {
0237 function = "ethernet3";
0238 groups = "ethernet3_0_grp";
0239 };
0240 };
0241
0242 pinctrl_usb0_default: usb0-default {
0243 conf {
0244 groups = "usb0_0_grp";
0245 slew-rate = <SLEW_RATE_SLOW>;
0246 power-source = <IO_STANDARD_LVCMOS18>;
0247 };
0248
0249 conf-rx {
0250 pins = "MIO52", "MIO53", "MIO55";
0251 bias-high-impedance;
0252 };
0253
0254 conf-tx {
0255 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0256 "MIO60", "MIO61", "MIO62", "MIO63";
0257 bias-disable;
0258 };
0259
0260 mux {
0261 groups = "usb0_0_grp";
0262 function = "usb0";
0263 };
0264 };
0265
0266 pinctrl_sdhci1_default: sdhci1-default {
0267 conf {
0268 groups = "sdio1_0_grp";
0269 slew-rate = <SLEW_RATE_SLOW>;
0270 power-source = <IO_STANDARD_LVCMOS18>;
0271 bias-disable;
0272 };
0273
0274 conf-cd {
0275 groups = "sdio1_cd_0_grp";
0276 bias-high-impedance;
0277 bias-pull-up;
0278 slew-rate = <SLEW_RATE_SLOW>;
0279 power-source = <IO_STANDARD_LVCMOS18>;
0280 };
0281
0282 mux-cd {
0283 groups = "sdio1_cd_0_grp";
0284 function = "sdio1_cd";
0285 };
0286
0287 mux {
0288 groups = "sdio1_0_grp";
0289 function = "sdio1";
0290 };
0291 };
0292 };
0293
0294 &uart1 {
0295 status = "okay";
0296 pinctrl-names = "default";
0297 pinctrl-0 = <&pinctrl_uart1_default>;
0298 };
