0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Clock specification for Xilinx ZynqMP
0004 *
0005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
0011 / {
0012 pss_ref_clk: pss_ref_clk {
0013 compatible = "fixed-clock";
0014 #clock-cells = <0>;
0015 clock-frequency = <33333333>;
0016 };
0017
0018 video_clk: video_clk {
0019 compatible = "fixed-clock";
0020 #clock-cells = <0>;
0021 clock-frequency = <27000000>;
0022 };
0023
0024 pss_alt_ref_clk: pss_alt_ref_clk {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <0>;
0028 };
0029
0030 gt_crx_ref_clk: gt_crx_ref_clk {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <108000000>;
0034 };
0035
0036 aux_ref_clk: aux_ref_clk {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <27000000>;
0040 };
0041 };
0042
0043 &zynqmp_firmware {
0044 zynqmp_clk: clock-controller {
0045 #clock-cells = <1>;
0046 compatible = "xlnx,zynqmp-clk";
0047 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
0048 <&aux_ref_clk>, <>_crx_ref_clk>;
0049 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
0050 "aux_ref_clk", "gt_crx_ref_clk";
0051 };
0052 };
0053
0054 &can0 {
0055 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
0056 };
0057
0058 &can1 {
0059 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
0060 };
0061
0062 &cpu0 {
0063 clocks = <&zynqmp_clk ACPU>;
0064 };
0065
0066 &fpd_dma_chan1 {
0067 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0068 };
0069
0070 &fpd_dma_chan2 {
0071 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0072 };
0073
0074 &fpd_dma_chan3 {
0075 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0076 };
0077
0078 &fpd_dma_chan4 {
0079 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0080 };
0081
0082 &fpd_dma_chan5 {
0083 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0084 };
0085
0086 &fpd_dma_chan6 {
0087 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0088 };
0089
0090 &fpd_dma_chan7 {
0091 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0092 };
0093
0094 &fpd_dma_chan8 {
0095 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0096 };
0097
0098 &lpd_dma_chan1 {
0099 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0100 };
0101
0102 &lpd_dma_chan2 {
0103 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0104 };
0105
0106 &lpd_dma_chan3 {
0107 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0108 };
0109
0110 &lpd_dma_chan4 {
0111 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0112 };
0113
0114 &lpd_dma_chan5 {
0115 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0116 };
0117
0118 &lpd_dma_chan6 {
0119 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0120 };
0121
0122 &lpd_dma_chan7 {
0123 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0124 };
0125
0126 &lpd_dma_chan8 {
0127 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0128 };
0129
0130 &nand0 {
0131 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
0132 };
0133
0134 &gem0 {
0135 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
0136 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
0137 <&zynqmp_clk GEM_TSU>;
0138 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
0139 };
0140
0141 &gem1 {
0142 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
0143 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
0144 <&zynqmp_clk GEM_TSU>;
0145 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
0146 };
0147
0148 &gem2 {
0149 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
0150 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
0151 <&zynqmp_clk GEM_TSU>;
0152 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
0153 };
0154
0155 &gem3 {
0156 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
0157 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
0158 <&zynqmp_clk GEM_TSU>;
0159 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
0160 };
0161
0162 &gpio {
0163 clocks = <&zynqmp_clk LPD_LSBUS>;
0164 };
0165
0166 &i2c0 {
0167 clocks = <&zynqmp_clk I2C0_REF>;
0168 };
0169
0170 &i2c1 {
0171 clocks = <&zynqmp_clk I2C1_REF>;
0172 };
0173
0174 &pcie {
0175 clocks = <&zynqmp_clk PCIE_REF>;
0176 };
0177
0178 &qspi {
0179 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
0180 };
0181
0182 &sata {
0183 clocks = <&zynqmp_clk SATA_REF>;
0184 };
0185
0186 &sdhci0 {
0187 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
0188 };
0189
0190 &sdhci1 {
0191 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
0192 };
0193
0194 &spi0 {
0195 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
0196 };
0197
0198 &spi1 {
0199 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
0200 };
0201
0202 &ttc0 {
0203 clocks = <&zynqmp_clk LPD_LSBUS>;
0204 };
0205
0206 &ttc1 {
0207 clocks = <&zynqmp_clk LPD_LSBUS>;
0208 };
0209
0210 &ttc2 {
0211 clocks = <&zynqmp_clk LPD_LSBUS>;
0212 };
0213
0214 &ttc3 {
0215 clocks = <&zynqmp_clk LPD_LSBUS>;
0216 };
0217
0218 &uart0 {
0219 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
0220 };
0221
0222 &uart1 {
0223 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
0224 };
0225
0226 &dwc3_0 {
0227 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
0228 };
0229
0230 &dwc3_1 {
0231 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
0232 };
0233
0234 &watchdog0 {
0235 clocks = <&zynqmp_clk WDT>;
0236 };
0237
0238 &lpd_watchdog {
0239 clocks = <&zynqmp_clk LPD_WDT>;
0240 };
0241
0242 &xilinx_ams {
0243 clocks = <&zynqmp_clk AMS_REF>;
0244 };
0245
0246 &zynqmp_dpdma {
0247 clocks = <&zynqmp_clk DPDMA_REF>;
0248 };
0249
0250 &zynqmp_dpsub {
0251 clocks = <&zynqmp_clk TOPSW_LSBUS>,
0252 <&zynqmp_clk DP_AUDIO_REF>,
0253 <&zynqmp_clk DP_VIDEO_REF>;
0254 };
