0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Source for the TMPV7708
0004 *
0005 * (C) Copyright 2018 - 2020, Toshiba Corporation.
0006 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
0007 *
0008 */
0009
0010 #include <dt-bindings/clock/toshiba,tmpv770x.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013
0014 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
0015
0016 / {
0017 compatible = "toshiba,tmpv7708";
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu-map {
0026 cluster0 {
0027 core0 {
0028 cpu = <&cpu0>;
0029 };
0030 core1 {
0031 cpu = <&cpu1>;
0032 };
0033 core2 {
0034 cpu = <&cpu2>;
0035 };
0036 core3 {
0037 cpu = <&cpu3>;
0038 };
0039 };
0040
0041 cluster1 {
0042 core0 {
0043 cpu = <&cpu4>;
0044 };
0045 core1 {
0046 cpu = <&cpu5>;
0047 };
0048 core2 {
0049 cpu = <&cpu6>;
0050 };
0051 core3 {
0052 cpu = <&cpu7>;
0053 };
0054 };
0055 };
0056
0057 cpu0: cpu@0 {
0058 compatible = "arm,cortex-a53";
0059 device_type = "cpu";
0060 enable-method = "spin-table";
0061 cpu-release-addr = <0x0 0x81100000>;
0062 reg = <0x00>;
0063 };
0064
0065 cpu1: cpu@1 {
0066 compatible = "arm,cortex-a53";
0067 device_type = "cpu";
0068 enable-method = "spin-table";
0069 cpu-release-addr = <0x0 0x81100000>;
0070 reg = <0x01>;
0071 };
0072
0073 cpu2: cpu@2 {
0074 compatible = "arm,cortex-a53";
0075 device_type = "cpu";
0076 enable-method = "spin-table";
0077 cpu-release-addr = <0x0 0x81100000>;
0078 reg = <0x02>;
0079 };
0080
0081 cpu3: cpu@3 {
0082 compatible = "arm,cortex-a53";
0083 device_type = "cpu";
0084 enable-method = "spin-table";
0085 cpu-release-addr = <0x0 0x81100000>;
0086 reg = <0x03>;
0087 };
0088
0089 cpu4: cpu@100 {
0090 compatible = "arm,cortex-a53";
0091 device_type = "cpu";
0092 enable-method = "spin-table";
0093 cpu-release-addr = <0x0 0x81100000>;
0094 reg = <0x100>;
0095 };
0096
0097 cpu5: cpu@101 {
0098 compatible = "arm,cortex-a53";
0099 device_type = "cpu";
0100 enable-method = "spin-table";
0101 cpu-release-addr = <0x0 0x81100000>;
0102 reg = <0x101>;
0103 };
0104
0105 cpu6: cpu@102 {
0106 compatible = "arm,cortex-a53";
0107 device_type = "cpu";
0108 enable-method = "spin-table";
0109 cpu-release-addr = <0x0 0x81100000>;
0110 reg = <0x102>;
0111 };
0112
0113 cpu7: cpu@103 {
0114 compatible = "arm,cortex-a53";
0115 device_type = "cpu";
0116 enable-method = "spin-table";
0117 cpu-release-addr = <0x0 0x81100000>;
0118 reg = <0x103>;
0119 };
0120 };
0121
0122 timer {
0123 compatible = "arm,armv8-timer";
0124 interrupt-parent = <&gic>;
0125 interrupts =
0126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0130 };
0131
0132 extclk100mhz: extclk100mhz {
0133 compatible = "fixed-clock";
0134 #clock-cells = <0>;
0135 clock-frequency = <100000000>;
0136 clock-output-names = "extclk100mhz";
0137 };
0138
0139 osc2_clk: osc2-clk {
0140 compatible = "fixed-clock";
0141 clock-frequency = <20000000>;
0142 #clock-cells = <0>;
0143 };
0144
0145 soc {
0146 #address-cells = <2>;
0147 #size-cells = <2>;
0148 compatible = "simple-bus";
0149 interrupt-parent = <&gic>;
0150 ranges;
0151
0152 gic: interrupt-controller@24001000 {
0153 compatible = "arm,gic-400";
0154 interrupt-controller;
0155 #interrupt-cells = <3>;
0156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0157 reg = <0 0x24001000 0 0x1000>,
0158 <0 0x24002000 0 0x2000>,
0159 <0 0x24004000 0 0x2000>,
0160 <0 0x24006000 0 0x2000>;
0161 };
0162
0163 pmux: pmux@24190000 {
0164 compatible = "toshiba,tmpv7708-pinctrl";
0165 reg = <0 0x24190000 0 0x10000>;
0166 };
0167
0168 gpio: gpio@28020000 {
0169 compatible = "toshiba,gpio-tmpv7708";
0170 reg = <0 0x28020000 0 0x1000>;
0171 #gpio-cells = <0x2>;
0172 gpio-ranges = <&pmux 0 0 32>;
0173 gpio-controller;
0174 interrupt-controller;
0175 #interrupt-cells = <2>;
0176 interrupt-parent = <&gic>;
0177 };
0178
0179 pipllct: clock-controller@24220000 {
0180 compatible = "toshiba,tmpv7708-pipllct";
0181 reg = <0 0x24220000 0 0x820>;
0182 #clock-cells = <1>;
0183 clocks = <&osc2_clk>;
0184 };
0185
0186 pismu: syscon@24200000 {
0187 compatible = "toshiba,tmpv7708-pismu", "syscon";
0188 reg = <0 0x24200000 0 0x2140>;
0189 #clock-cells = <1>;
0190 #reset-cells = <1>;
0191 };
0192
0193 uart0: serial@28200000 {
0194 compatible = "arm,pl011", "arm,primecell";
0195 reg = <0 0x28200000 0 0x1000>;
0196 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&uart0_pins>;
0199 clocks = <&pismu TMPV770X_CLK_PIUART0>;
0200 clock-names = "apb_pclk";
0201 status = "disabled";
0202 };
0203
0204 uart1: serial@28201000 {
0205 compatible = "arm,pl011", "arm,primecell";
0206 reg = <0 0x28201000 0 0x1000>;
0207 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&uart1_pins>;
0210 clocks = <&pismu TMPV770X_CLK_PIUART1>;
0211 clock-names = "apb_pclk";
0212 status = "disabled";
0213 };
0214
0215 uart2: serial@28202000 {
0216 compatible = "arm,pl011", "arm,primecell";
0217 reg = <0 0x28202000 0 0x1000>;
0218 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&uart2_pins>;
0221 clocks = <&pismu TMPV770X_CLK_PIUART2>;
0222 clock-names = "apb_pclk";
0223 status = "disabled";
0224 };
0225
0226 uart3: serial@28203000 {
0227 compatible = "arm,pl011", "arm,primecell";
0228 reg = <0 0x28203000 0 0x1000>;
0229 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&uart3_pins>;
0232 clocks = <&pismu TMPV770X_CLK_PIUART2>;
0233 clock-names = "apb_pclk";
0234 status = "disabled";
0235 };
0236
0237 i2c0: i2c@28030000 {
0238 compatible = "snps,designware-i2c";
0239 reg = <0 0x28030000 0 0x1000>;
0240 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0241 pinctrl-names = "default";
0242 pinctrl-0 = <&i2c0_pins>;
0243 clock-frequency = <400000>;
0244 #address-cells = <1>;
0245 #size-cells = <0>;
0246 clocks = <&pismu TMPV770X_CLK_PII2C0>;
0247 status = "disabled";
0248 };
0249
0250 i2c1: i2c@28031000 {
0251 compatible = "snps,designware-i2c";
0252 reg = <0 0x28031000 0 0x1000>;
0253 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0254 pinctrl-names = "default";
0255 pinctrl-0 = <&i2c1_pins>;
0256 clock-frequency = <400000>;
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259 clocks = <&pismu TMPV770X_CLK_PII2C1>;
0260 status = "disabled";
0261 };
0262
0263 i2c2: i2c@28032000 {
0264 compatible = "snps,designware-i2c";
0265 reg = <0 0x28032000 0 0x1000>;
0266 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0267 pinctrl-names = "default";
0268 pinctrl-0 = <&i2c2_pins>;
0269 clock-frequency = <400000>;
0270 #address-cells = <1>;
0271 #size-cells = <0>;
0272 clocks = <&pismu TMPV770X_CLK_PII2C2>;
0273 status = "disabled";
0274 };
0275
0276 i2c3: i2c@28033000 {
0277 compatible = "snps,designware-i2c";
0278 reg = <0 0x28033000 0 0x1000>;
0279 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0280 pinctrl-names = "default";
0281 pinctrl-0 = <&i2c3_pins>;
0282 clock-frequency = <400000>;
0283 #address-cells = <1>;
0284 #size-cells = <0>;
0285 clocks = <&pismu TMPV770X_CLK_PII2C3>;
0286 status = "disabled";
0287 };
0288
0289 i2c4: i2c@28034000 {
0290 compatible = "snps,designware-i2c";
0291 reg = <0 0x28034000 0 0x1000>;
0292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&i2c4_pins>;
0295 clock-frequency = <400000>;
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 clocks = <&pismu TMPV770X_CLK_PII2C4>;
0299 status = "disabled";
0300 };
0301
0302 i2c5: i2c@28035000 {
0303 compatible = "snps,designware-i2c";
0304 reg = <0 0x28035000 0 0x1000>;
0305 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&i2c5_pins>;
0308 clock-frequency = <400000>;
0309 #address-cells = <1>;
0310 #size-cells = <0>;
0311 clocks = <&pismu TMPV770X_CLK_PII2C5>;
0312 status = "disabled";
0313 };
0314
0315 i2c6: i2c@28036000 {
0316 compatible = "snps,designware-i2c";
0317 reg = <0 0x28036000 0 0x1000>;
0318 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0319 pinctrl-names = "default";
0320 pinctrl-0 = <&i2c6_pins>;
0321 clock-frequency = <400000>;
0322 #address-cells = <1>;
0323 #size-cells = <0>;
0324 clocks = <&pismu TMPV770X_CLK_PII2C6>;
0325 status = "disabled";
0326 };
0327
0328 i2c7: i2c@28037000 {
0329 compatible = "snps,designware-i2c";
0330 reg = <0 0x28037000 0 0x1000>;
0331 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0332 pinctrl-names = "default";
0333 pinctrl-0 = <&i2c7_pins>;
0334 clock-frequency = <400000>;
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337 clocks = <&pismu TMPV770X_CLK_PII2C7>;
0338 status = "disabled";
0339 };
0340
0341 i2c8: i2c@28038000 {
0342 compatible = "snps,designware-i2c";
0343 reg = <0 0x28038000 0 0x1000>;
0344 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0345 pinctrl-names = "default";
0346 pinctrl-0 = <&i2c8_pins>;
0347 clock-frequency = <400000>;
0348 #address-cells = <1>;
0349 #size-cells = <0>;
0350 clocks = <&pismu TMPV770X_CLK_PII2C8>;
0351 status = "disabled";
0352 };
0353
0354 spi0: spi@28140000 {
0355 compatible = "arm,pl022", "arm,primecell";
0356 reg = <0 0x28140000 0 0x1000>;
0357 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0358 pinctrl-names = "default";
0359 pinctrl-0 = <&spi0_pins>;
0360 num-cs = <1>;
0361 #address-cells = <1>;
0362 #size-cells = <0>;
0363 clocks = <&pismu TMPV770X_CLK_PISPI1>;
0364 clock-names = "apb_pclk";
0365 status = "disabled";
0366 };
0367
0368 spi1: spi@28141000 {
0369 compatible = "arm,pl022", "arm,primecell";
0370 reg = <0 0x28141000 0 0x1000>;
0371 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0372 pinctrl-names = "default";
0373 pinctrl-0 = <&spi1_pins>;
0374 num-cs = <1>;
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 clocks = <&pismu TMPV770X_CLK_PISPI1>;
0378 clock-names = "apb_pclk";
0379 status = "disabled";
0380 };
0381
0382 spi2: spi@28142000 {
0383 compatible = "arm,pl022", "arm,primecell";
0384 reg = <0 0x28142000 0 0x1000>;
0385 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0386 pinctrl-names = "default";
0387 pinctrl-0 = <&spi2_pins>;
0388 num-cs = <1>;
0389 #address-cells = <1>;
0390 #size-cells = <0>;
0391 clocks = <&pismu TMPV770X_CLK_PISPI2>;
0392 clock-names = "apb_pclk";
0393 status = "disabled";
0394 };
0395
0396 spi3: spi@28143000 {
0397 compatible = "arm,pl022", "arm,primecell";
0398 reg = <0 0x28143000 0 0x1000>;
0399 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&spi3_pins>;
0402 num-cs = <1>;
0403 #address-cells = <1>;
0404 #size-cells = <0>;
0405 clocks = <&pismu TMPV770X_CLK_PISPI3>;
0406 clock-names = "apb_pclk";
0407 status = "disabled";
0408 };
0409
0410 spi4: spi@28144000 {
0411 compatible = "arm,pl022", "arm,primecell";
0412 reg = <0 0x28144000 0 0x1000>;
0413 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0414 pinctrl-names = "default";
0415 pinctrl-0 = <&spi4_pins>;
0416 num-cs = <1>;
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 clocks = <&pismu TMPV770X_CLK_PISPI4>;
0420 clock-names = "apb_pclk";
0421 status = "disabled";
0422 };
0423
0424 spi5: spi@28145000 {
0425 compatible = "arm,pl022", "arm,primecell";
0426 reg = <0 0x28145000 0 0x1000>;
0427 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&spi5_pins>;
0430 num-cs = <1>;
0431 #address-cells = <1>;
0432 #size-cells = <0>;
0433 clocks = <&pismu TMPV770X_CLK_PISPI5>;
0434 clock-names = "apb_pclk";
0435 status = "disabled";
0436 };
0437
0438 spi6: spi@28146000 {
0439 compatible = "arm,pl022", "arm,primecell";
0440 reg = <0 0x28146000 0 0x1000>;
0441 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
0442 pinctrl-names = "default";
0443 pinctrl-0 = <&spi6_pins>;
0444 num-cs = <1>;
0445 #address-cells = <1>;
0446 #size-cells = <0>;
0447 clocks = <&pismu TMPV770X_CLK_PISPI6>;
0448 clock-names = "apb_pclk";
0449 status = "disabled";
0450 };
0451
0452 piether: ethernet@28000000 {
0453 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
0454 reg = <0 0x28000000 0 0x10000>;
0455 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0456 interrupt-names = "macirq";
0457 snps,txpbl = <4>;
0458 snps,rxpbl = <4>;
0459 snps,tso;
0460 clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
0461 clock-names = "stmmaceth", "phy_ref_clk";
0462 status = "disabled";
0463 };
0464
0465 wdt: wdt@28330000 {
0466 compatible = "toshiba,visconti-wdt";
0467 reg = <0 0x28330000 0 0x1000>;
0468 clocks = <&pismu TMPV770X_CLK_WDTCLK>;
0469 status = "disabled";
0470 };
0471
0472 pwm: pwm@241c0000 {
0473 compatible = "toshiba,visconti-pwm";
0474 reg = <0 0x241c0000 0 0x1000>;
0475 pinctrl-names = "default";
0476 pinctrl-0 = <&pwm_mux>;
0477 #pwm-cells = <2>;
0478 status = "disabled";
0479 };
0480
0481 pcie: pcie@28400000 {
0482 compatible = "toshiba,visconti-pcie";
0483 reg = <0x0 0x28400000 0x0 0x00400000>,
0484 <0x0 0x70000000 0x0 0x10000000>,
0485 <0x0 0x28050000 0x0 0x00010000>,
0486 <0x0 0x24200000 0x0 0x00002000>,
0487 <0x0 0x24162000 0x0 0x00001000>;
0488 reg-names = "dbi", "config", "ulreg", "smu", "mpu";
0489 device_type = "pci";
0490 bus-range = <0x00 0xff>;
0491 num-lanes = <2>;
0492 num-viewport = <8>;
0493
0494 #address-cells = <3>;
0495 #size-cells = <2>;
0496 #interrupt-cells = <1>;
0497 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
0498 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
0499 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0500 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
0501 interrupt-names = "msi", "intr";
0502 interrupt-map-mask = <0 0 0 7>;
0503 interrupt-map =
0504 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0505 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0506 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0507 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
0508 max-link-speed = <2>;
0509 clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
0510 clock-names = "ref", "core", "aux";
0511 status = "disabled";
0512 };
0513 };
0514 };
0515
0516 #include "tmpv7708_pins.dtsi"
