0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
0004 *
0005 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 &cbass_mcu_wakeup {
0009 sms: system-controller@44083000 {
0010 compatible = "ti,k2g-sci";
0011 ti,host-id = <12>;
0012
0013 mbox-names = "rx", "tx";
0014
0015 mboxes = <&secure_proxy_main 11>,
0016 <&secure_proxy_main 13>;
0017
0018 reg-names = "debug_messages";
0019 reg = <0x00 0x44083000 0x00 0x1000>;
0020
0021 k3_pds: power-controller {
0022 compatible = "ti,sci-pm-domain";
0023 #power-domain-cells = <2>;
0024 };
0025
0026 k3_clks: clock-controller {
0027 compatible = "ti,k2g-sci-clk";
0028 #clock-cells = <2>;
0029 };
0030
0031 k3_reset: reset-controller {
0032 compatible = "ti,sci-reset";
0033 #reset-cells = <2>;
0034 };
0035 };
0036
0037 chipid@43000014 {
0038 compatible = "ti,am654-chipid";
0039 reg = <0x00 0x43000014 0x00 0x4>;
0040 };
0041
0042 mcu_ram: sram@41c00000 {
0043 compatible = "mmio-sram";
0044 reg = <0x00 0x41c00000 0x00 0x100000>;
0045 ranges = <0x00 0x00 0x41c00000 0x100000>;
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 };
0049
0050 wkup_pmx0: pinctrl@4301c000 {
0051 compatible = "pinctrl-single";
0052 /* Proxy 0 addressing */
0053 reg = <0x00 0x4301c000 0x00 0x178>;
0054 #pinctrl-cells = <1>;
0055 pinctrl-single,register-width = <32>;
0056 pinctrl-single,function-mask = <0xffffffff>;
0057 };
0058
0059 wkup_gpio_intr: interrupt-controller@42200000 {
0060 compatible = "ti,sci-intr";
0061 reg = <0x00 0x42200000 0x00 0x400>;
0062 ti,intr-trigger-type = <1>;
0063 interrupt-controller;
0064 interrupt-parent = <&gic500>;
0065 #interrupt-cells = <1>;
0066 ti,sci = <&sms>;
0067 ti,sci-dev-id = <125>;
0068 ti,interrupt-ranges = <16 928 16>;
0069 };
0070
0071 mcu_conf: syscon@40f00000 {
0072 compatible = "syscon", "simple-mfd";
0073 reg = <0x0 0x40f00000 0x0 0x20000>;
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 ranges = <0x0 0x0 0x40f00000 0x20000>;
0077
0078 phy_gmii_sel: phy@4040 {
0079 compatible = "ti,am654-phy-gmii-sel";
0080 reg = <0x4040 0x4>;
0081 #phy-cells = <1>;
0082 };
0083
0084 };
0085
0086 wkup_uart0: serial@42300000 {
0087 compatible = "ti,j721e-uart", "ti,am654-uart";
0088 reg = <0x00 0x42300000 0x00 0x200>;
0089 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
0090 current-speed = <115200>;
0091 clocks = <&k3_clks 359 3>;
0092 clock-names = "fclk";
0093 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
0094 };
0095
0096 mcu_uart0: serial@40a00000 {
0097 compatible = "ti,j721e-uart", "ti,am654-uart";
0098 reg = <0x00 0x40a00000 0x00 0x200>;
0099 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
0100 current-speed = <115200>;
0101 clocks = <&k3_clks 149 3>;
0102 clock-names = "fclk";
0103 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
0104 };
0105
0106 wkup_gpio0: gpio@42110000 {
0107 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0108 reg = <0x00 0x42110000 0x00 0x100>;
0109 gpio-controller;
0110 #gpio-cells = <2>;
0111 interrupt-parent = <&wkup_gpio_intr>;
0112 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
0113 interrupt-controller;
0114 #interrupt-cells = <2>;
0115 ti,ngpio = <89>;
0116 ti,davinci-gpio-unbanked = <0>;
0117 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
0118 clocks = <&k3_clks 115 0>;
0119 clock-names = "gpio";
0120 };
0121
0122 wkup_gpio1: gpio@42100000 {
0123 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0124 reg = <0x00 0x42100000 0x00 0x100>;
0125 gpio-controller;
0126 #gpio-cells = <2>;
0127 interrupt-parent = <&wkup_gpio_intr>;
0128 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
0129 interrupt-controller;
0130 #interrupt-cells = <2>;
0131 ti,ngpio = <89>;
0132 ti,davinci-gpio-unbanked = <0>;
0133 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
0134 clocks = <&k3_clks 116 0>;
0135 clock-names = "gpio";
0136 };
0137
0138 wkup_i2c0: i2c@42120000 {
0139 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0140 reg = <0x00 0x42120000 0x00 0x100>;
0141 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 clocks = <&k3_clks 223 1>;
0145 clock-names = "fck";
0146 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
0147 };
0148
0149 mcu_i2c0: i2c@40b00000 {
0150 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0151 reg = <0x00 0x40b00000 0x00 0x100>;
0152 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 clocks = <&k3_clks 221 1>;
0156 clock-names = "fck";
0157 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
0158 };
0159
0160 mcu_i2c1: i2c@40b10000 {
0161 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0162 reg = <0x00 0x40b10000 0x00 0x100>;
0163 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166 clocks = <&k3_clks 222 1>;
0167 clock-names = "fck";
0168 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
0169 };
0170
0171 mcu_mcan0: can@40528000 {
0172 compatible = "bosch,m_can";
0173 reg = <0x00 0x40528000 0x00 0x200>,
0174 <0x00 0x40500000 0x00 0x8000>;
0175 reg-names = "m_can", "message_ram";
0176 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
0177 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
0178 clock-names = "hclk", "cclk";
0179 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
0180 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
0181 interrupt-names = "int0", "int1";
0182 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0183 };
0184
0185 mcu_mcan1: can@40568000 {
0186 compatible = "bosch,m_can";
0187 reg = <0x00 0x40568000 0x00 0x200>,
0188 <0x00 0x40540000 0x00 0x8000>;
0189 reg-names = "m_can", "message_ram";
0190 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
0191 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
0192 clock-names = "hclk", "cclk";
0193 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
0194 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
0195 interrupt-names = "int0", "int1";
0196 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0197 };
0198
0199 mcu_navss: bus@28380000{
0200 compatible = "simple-mfd";
0201 #address-cells = <2>;
0202 #size-cells = <2>;
0203 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
0204 dma-coherent;
0205 dma-ranges;
0206
0207 ti,sci-dev-id = <267>;
0208
0209 mcu_ringacc: ringacc@2b800000 {
0210 compatible = "ti,am654-navss-ringacc";
0211 reg = <0x0 0x2b800000 0x0 0x400000>,
0212 <0x0 0x2b000000 0x0 0x400000>,
0213 <0x0 0x28590000 0x0 0x100>,
0214 <0x0 0x2a500000 0x0 0x40000>;
0215 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0216 ti,num-rings = <286>;
0217 ti,sci-rm-range-gp-rings = <0x1>;
0218 ti,sci = <&sms>;
0219 ti,sci-dev-id = <272>;
0220 msi-parent = <&main_udmass_inta>;
0221 };
0222
0223 mcu_udmap: dma-controller@285c0000 {
0224 compatible = "ti,j721e-navss-mcu-udmap";
0225 reg = <0x0 0x285c0000 0x0 0x100>,
0226 <0x0 0x2a800000 0x0 0x40000>,
0227 <0x0 0x2aa00000 0x0 0x40000>;
0228 reg-names = "gcfg", "rchanrt", "tchanrt";
0229 msi-parent = <&main_udmass_inta>;
0230 #dma-cells = <1>;
0231
0232 ti,sci = <&sms>;
0233 ti,sci-dev-id = <273>;
0234 ti,ringacc = <&mcu_ringacc>;
0235 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0236 <0x0f>; /* TX_HCHAN */
0237 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0238 <0x0b>; /* RX_HCHAN */
0239 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0240 };
0241 };
0242
0243 mcu_cpsw: ethernet@46000000 {
0244 compatible = "ti,j721e-cpsw-nuss";
0245 #address-cells = <2>;
0246 #size-cells = <2>;
0247 reg = <0x0 0x46000000 0x0 0x200000>;
0248 reg-names = "cpsw_nuss";
0249 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
0250 dma-coherent;
0251 clocks = <&k3_clks 29 28>;
0252 clock-names = "fck";
0253 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
0254
0255 dmas = <&mcu_udmap 0xf000>,
0256 <&mcu_udmap 0xf001>,
0257 <&mcu_udmap 0xf002>,
0258 <&mcu_udmap 0xf003>,
0259 <&mcu_udmap 0xf004>,
0260 <&mcu_udmap 0xf005>,
0261 <&mcu_udmap 0xf006>,
0262 <&mcu_udmap 0xf007>,
0263 <&mcu_udmap 0x7000>;
0264 dma-names = "tx0", "tx1", "tx2", "tx3",
0265 "tx4", "tx5", "tx6", "tx7",
0266 "rx";
0267
0268 ethernet-ports {
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271
0272 cpsw_port1: port@1 {
0273 reg = <1>;
0274 ti,mac-only;
0275 label = "port1";
0276 ti,syscon-efuse = <&mcu_conf 0x200>;
0277 phys = <&phy_gmii_sel 1>;
0278 };
0279 };
0280
0281 davinci_mdio: mdio@f00 {
0282 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0283 reg = <0x0 0xf00 0x0 0x100>;
0284 #address-cells = <1>;
0285 #size-cells = <0>;
0286 clocks = <&k3_clks 29 28>;
0287 clock-names = "fck";
0288 bus_freq = <1000000>;
0289 };
0290
0291 cpts@3d000 {
0292 compatible = "ti,am65-cpts";
0293 reg = <0x0 0x3d000 0x0 0x400>;
0294 clocks = <&k3_clks 29 3>;
0295 clock-names = "cpts";
0296 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
0297 interrupt-names = "cpts";
0298 ti,cpts-ext-ts-inputs = <4>;
0299 ti,cpts-periodic-outputs = <2>;
0300 };
0301 };
0302 };
