0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721E SoC Family
0004 *
0005 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/pinctrl/k3.h>
0011 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0012
0013 / {
0014 model = "Texas Instruments K3 J721E SoC";
0015 compatible = "ti,j721e";
0016 interrupt-parent = <&gic500>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 serial0 = &wkup_uart0;
0022 serial1 = &mcu_uart0;
0023 serial2 = &main_uart0;
0024 serial3 = &main_uart1;
0025 serial4 = &main_uart2;
0026 serial5 = &main_uart3;
0027 serial6 = &main_uart4;
0028 serial7 = &main_uart5;
0029 serial8 = &main_uart6;
0030 serial9 = &main_uart7;
0031 serial10 = &main_uart8;
0032 serial11 = &main_uart9;
0033 ethernet0 = &cpsw_port1;
0034 mmc0 = &main_sdhci0;
0035 mmc1 = &main_sdhci1;
0036 mmc2 = &main_sdhci2;
0037 };
0038
0039 chosen { };
0040
0041 cpus {
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044 cpu-map {
0045 cluster0: cluster0 {
0046 core0 {
0047 cpu = <&cpu0>;
0048 };
0049
0050 core1 {
0051 cpu = <&cpu1>;
0052 };
0053 };
0054
0055 };
0056
0057 cpu0: cpu@0 {
0058 compatible = "arm,cortex-a72";
0059 reg = <0x000>;
0060 device_type = "cpu";
0061 enable-method = "psci";
0062 i-cache-size = <0xC000>;
0063 i-cache-line-size = <64>;
0064 i-cache-sets = <256>;
0065 d-cache-size = <0x8000>;
0066 d-cache-line-size = <64>;
0067 d-cache-sets = <256>;
0068 next-level-cache = <&L2_0>;
0069 };
0070
0071 cpu1: cpu@1 {
0072 compatible = "arm,cortex-a72";
0073 reg = <0x001>;
0074 device_type = "cpu";
0075 enable-method = "psci";
0076 i-cache-size = <0xC000>;
0077 i-cache-line-size = <64>;
0078 i-cache-sets = <256>;
0079 d-cache-size = <0x8000>;
0080 d-cache-line-size = <64>;
0081 d-cache-sets = <256>;
0082 next-level-cache = <&L2_0>;
0083 };
0084 };
0085
0086 L2_0: l2-cache0 {
0087 compatible = "cache";
0088 cache-level = <2>;
0089 cache-size = <0x100000>;
0090 cache-line-size = <64>;
0091 cache-sets = <1024>;
0092 next-level-cache = <&msmc_l3>;
0093 };
0094
0095 msmc_l3: l3-cache0 {
0096 compatible = "cache";
0097 cache-level = <3>;
0098 };
0099
0100 firmware {
0101 optee {
0102 compatible = "linaro,optee-tz";
0103 method = "smc";
0104 };
0105
0106 psci: psci {
0107 compatible = "arm,psci-1.0";
0108 method = "smc";
0109 };
0110 };
0111
0112 a72_timer0: timer-cl0-cpu0 {
0113 compatible = "arm,armv8-timer";
0114 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
0115 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
0116 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
0117 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
0118 };
0119
0120 pmu: pmu {
0121 compatible = "arm,cortex-a72-pmu";
0122 /* Recommendation from GIC500 TRM Table A.3 */
0123 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0124 };
0125
0126 cbass_main: bus@100000 {
0127 compatible = "simple-bus";
0128 #address-cells = <2>;
0129 #size-cells = <2>;
0130 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
0131 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
0132 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
0133 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
0134 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
0135 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
0136 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
0137 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
0138 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
0139 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
0140 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
0141 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
0142 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
0143 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
0144 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
0145 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
0146 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
0147 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
0148 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
0149
0150 /* MCUSS_WKUP Range */
0151 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
0152 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
0153 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
0154 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
0155 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
0156 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
0157 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
0158 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
0159 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
0160 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
0161 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
0162 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
0163 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
0164
0165 cbass_mcu_wakeup: bus@28380000 {
0166 compatible = "simple-bus";
0167 #address-cells = <2>;
0168 #size-cells = <2>;
0169 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
0170 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
0171 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
0172 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
0173 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
0174 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
0175 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
0176 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
0177 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
0178 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
0179 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
0180 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
0181 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
0182 };
0183 };
0184 };
0185
0186 /* Now include the peripherals for each bus segments */
0187 #include "k3-j721e-main.dtsi"
0188 #include "k3-j721e-mcu-wakeup.dtsi"
