0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "k3-j721e.dtsi"
0009
0010 / {
0011 memory@80000000 {
0012 device_type = "memory";
0013 /* 4G RAM */
0014 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
0015 <0x00000008 0x80000000 0x00000000 0x80000000>;
0016 };
0017
0018 reserved_memory: reserved-memory {
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021 ranges;
0022
0023 secure_ddr: optee@9e800000 {
0024 reg = <0x00 0x9e800000 0x00 0x01800000>;
0025 alignment = <0x1000>;
0026 no-map;
0027 };
0028
0029 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
0030 compatible = "shared-dma-pool";
0031 reg = <0x00 0xa0000000 0x00 0x100000>;
0032 no-map;
0033 };
0034
0035 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
0036 compatible = "shared-dma-pool";
0037 reg = <0x00 0xa0100000 0x00 0xf00000>;
0038 no-map;
0039 };
0040
0041 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
0042 compatible = "shared-dma-pool";
0043 reg = <0x00 0xa1000000 0x00 0x100000>;
0044 no-map;
0045 };
0046
0047 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
0048 compatible = "shared-dma-pool";
0049 reg = <0x00 0xa1100000 0x00 0xf00000>;
0050 no-map;
0051 };
0052
0053 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
0054 compatible = "shared-dma-pool";
0055 reg = <0x00 0xa2000000 0x00 0x100000>;
0056 no-map;
0057 };
0058
0059 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
0060 compatible = "shared-dma-pool";
0061 reg = <0x00 0xa2100000 0x00 0xf00000>;
0062 no-map;
0063 };
0064
0065 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
0066 compatible = "shared-dma-pool";
0067 reg = <0x00 0xa3000000 0x00 0x100000>;
0068 no-map;
0069 };
0070
0071 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
0072 compatible = "shared-dma-pool";
0073 reg = <0x00 0xa3100000 0x00 0xf00000>;
0074 no-map;
0075 };
0076
0077 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
0078 compatible = "shared-dma-pool";
0079 reg = <0x00 0xa4000000 0x00 0x100000>;
0080 no-map;
0081 };
0082
0083 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
0084 compatible = "shared-dma-pool";
0085 reg = <0x00 0xa4100000 0x00 0xf00000>;
0086 no-map;
0087 };
0088
0089 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
0090 compatible = "shared-dma-pool";
0091 reg = <0x00 0xa5000000 0x00 0x100000>;
0092 no-map;
0093 };
0094
0095 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
0096 compatible = "shared-dma-pool";
0097 reg = <0x00 0xa5100000 0x00 0xf00000>;
0098 no-map;
0099 };
0100
0101 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
0102 compatible = "shared-dma-pool";
0103 reg = <0x00 0xa6000000 0x00 0x100000>;
0104 no-map;
0105 };
0106
0107 c66_0_memory_region: c66-memory@a6100000 {
0108 compatible = "shared-dma-pool";
0109 reg = <0x00 0xa6100000 0x00 0xf00000>;
0110 no-map;
0111 };
0112
0113 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
0114 compatible = "shared-dma-pool";
0115 reg = <0x00 0xa7000000 0x00 0x100000>;
0116 no-map;
0117 };
0118
0119 c66_1_memory_region: c66-memory@a7100000 {
0120 compatible = "shared-dma-pool";
0121 reg = <0x00 0xa7100000 0x00 0xf00000>;
0122 no-map;
0123 };
0124
0125 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
0126 compatible = "shared-dma-pool";
0127 reg = <0x00 0xa8000000 0x00 0x100000>;
0128 no-map;
0129 };
0130
0131 c71_0_memory_region: c71-memory@a8100000 {
0132 compatible = "shared-dma-pool";
0133 reg = <0x00 0xa8100000 0x00 0xf00000>;
0134 no-map;
0135 };
0136
0137 rtos_ipc_memory_region: ipc-memories@aa000000 {
0138 reg = <0x00 0xaa000000 0x00 0x01c00000>;
0139 alignment = <0x1000>;
0140 no-map;
0141 };
0142 };
0143 };
0144
0145 &wkup_pmx0 {
0146 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
0147 pinctrl-single,pins = <
0148 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
0149 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
0150 >;
0151 };
0152
0153 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
0154 pinctrl-single,pins = <
0155 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
0156 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
0157 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
0158 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
0159 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
0160 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
0161 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
0162 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
0163 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
0164 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
0165 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
0166 >;
0167 };
0168 };
0169
0170 &ospi0 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
0173
0174 flash@0 {
0175 compatible = "jedec,spi-nor";
0176 reg = <0x0>;
0177 spi-tx-bus-width = <8>;
0178 spi-rx-bus-width = <8>;
0179 spi-max-frequency = <25000000>;
0180 cdns,tshsl-ns = <60>;
0181 cdns,tsd2d-ns = <60>;
0182 cdns,tchsh-ns = <60>;
0183 cdns,tslch-ns = <60>;
0184 cdns,read-delay = <0>;
0185 };
0186 };
0187
0188 &mailbox0_cluster0 {
0189 interrupts = <436>;
0190
0191 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
0192 ti,mbox-rx = <0 0 0>;
0193 ti,mbox-tx = <1 0 0>;
0194 };
0195
0196 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
0197 ti,mbox-rx = <2 0 0>;
0198 ti,mbox-tx = <3 0 0>;
0199 };
0200 };
0201
0202 &mailbox0_cluster1 {
0203 interrupts = <432>;
0204
0205 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
0206 ti,mbox-rx = <0 0 0>;
0207 ti,mbox-tx = <1 0 0>;
0208 };
0209
0210 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
0211 ti,mbox-rx = <2 0 0>;
0212 ti,mbox-tx = <3 0 0>;
0213 };
0214 };
0215
0216 &mailbox0_cluster2 {
0217 interrupts = <428>;
0218
0219 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
0220 ti,mbox-rx = <0 0 0>;
0221 ti,mbox-tx = <1 0 0>;
0222 };
0223
0224 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
0225 ti,mbox-rx = <2 0 0>;
0226 ti,mbox-tx = <3 0 0>;
0227 };
0228 };
0229
0230 &mailbox0_cluster3 {
0231 interrupts = <424>;
0232
0233 mbox_c66_0: mbox-c66-0 {
0234 ti,mbox-rx = <0 0 0>;
0235 ti,mbox-tx = <1 0 0>;
0236 };
0237
0238 mbox_c66_1: mbox-c66-1 {
0239 ti,mbox-rx = <2 0 0>;
0240 ti,mbox-tx = <3 0 0>;
0241 };
0242 };
0243
0244 &mailbox0_cluster4 {
0245 interrupts = <420>;
0246
0247 mbox_c71_0: mbox-c71-0 {
0248 ti,mbox-rx = <0 0 0>;
0249 ti,mbox-tx = <1 0 0>;
0250 };
0251 };
0252
0253 &mailbox0_cluster5 {
0254 status = "disabled";
0255 };
0256
0257 &mailbox0_cluster6 {
0258 status = "disabled";
0259 };
0260
0261 &mailbox0_cluster7 {
0262 status = "disabled";
0263 };
0264
0265 &mailbox0_cluster8 {
0266 status = "disabled";
0267 };
0268
0269 &mailbox0_cluster9 {
0270 status = "disabled";
0271 };
0272
0273 &mailbox0_cluster10 {
0274 status = "disabled";
0275 };
0276
0277 &mailbox0_cluster11 {
0278 status = "disabled";
0279 };
0280
0281 &mcu_r5fss0_core0 {
0282 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
0283 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
0284 <&mcu_r5fss0_core0_memory_region>;
0285 };
0286
0287 &mcu_r5fss0_core1 {
0288 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
0289 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
0290 <&mcu_r5fss0_core1_memory_region>;
0291 };
0292
0293 &main_r5fss0_core0 {
0294 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
0295 memory-region = <&main_r5fss0_core0_dma_memory_region>,
0296 <&main_r5fss0_core0_memory_region>;
0297 };
0298
0299 &main_r5fss0_core1 {
0300 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
0301 memory-region = <&main_r5fss0_core1_dma_memory_region>,
0302 <&main_r5fss0_core1_memory_region>;
0303 };
0304
0305 &main_r5fss1_core0 {
0306 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
0307 memory-region = <&main_r5fss1_core0_dma_memory_region>,
0308 <&main_r5fss1_core0_memory_region>;
0309 };
0310
0311 &main_r5fss1_core1 {
0312 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
0313 memory-region = <&main_r5fss1_core1_dma_memory_region>,
0314 <&main_r5fss1_core1_memory_region>;
0315 };
0316
0317 &c66_0 {
0318 mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
0319 memory-region = <&c66_0_dma_memory_region>,
0320 <&c66_0_memory_region>;
0321 };
0322
0323 &c66_1 {
0324 mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
0325 memory-region = <&c66_1_dma_memory_region>,
0326 <&c66_1_memory_region>;
0327 };
0328
0329 &c71_0 {
0330 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
0331 memory-region = <&c71_0_dma_memory_region>,
0332 <&c71_0_memory_region>;
0333 };
