0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
0004 *
0005 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 &cbass_mcu_wakeup {
0009 dmsc: system-controller@44083000 {
0010 compatible = "ti,k2g-sci";
0011 ti,host-id = <12>;
0012
0013 mbox-names = "rx", "tx";
0014
0015 mboxes = <&secure_proxy_main 11>,
0016 <&secure_proxy_main 13>;
0017
0018 reg-names = "debug_messages";
0019 reg = <0x00 0x44083000 0x0 0x1000>;
0020
0021 k3_pds: power-controller {
0022 compatible = "ti,sci-pm-domain";
0023 #power-domain-cells = <2>;
0024 };
0025
0026 k3_clks: clock-controller {
0027 compatible = "ti,k2g-sci-clk";
0028 #clock-cells = <2>;
0029 };
0030
0031 k3_reset: reset-controller {
0032 compatible = "ti,sci-reset";
0033 #reset-cells = <2>;
0034 };
0035 };
0036
0037 mcu_conf: syscon@40f00000 {
0038 compatible = "syscon", "simple-mfd";
0039 reg = <0x0 0x40f00000 0x0 0x20000>;
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 ranges = <0x0 0x0 0x40f00000 0x20000>;
0043
0044 phy_gmii_sel: phy@4040 {
0045 compatible = "ti,am654-phy-gmii-sel";
0046 reg = <0x4040 0x4>;
0047 #phy-cells = <1>;
0048 };
0049 };
0050
0051 chipid@43000014 {
0052 compatible = "ti,am654-chipid";
0053 reg = <0x0 0x43000014 0x0 0x4>;
0054 };
0055
0056 wkup_pmx0: pinctrl@4301c000 {
0057 compatible = "pinctrl-single";
0058 /* Proxy 0 addressing */
0059 reg = <0x00 0x4301c000 0x00 0x178>;
0060 #pinctrl-cells = <1>;
0061 pinctrl-single,register-width = <32>;
0062 pinctrl-single,function-mask = <0xffffffff>;
0063 };
0064
0065 mcu_ram: sram@41c00000 {
0066 compatible = "mmio-sram";
0067 reg = <0x00 0x41c00000 0x00 0x100000>;
0068 ranges = <0x0 0x00 0x41c00000 0x100000>;
0069 #address-cells = <1>;
0070 #size-cells = <1>;
0071 };
0072
0073 wkup_uart0: serial@42300000 {
0074 compatible = "ti,j721e-uart", "ti,am654-uart";
0075 reg = <0x00 0x42300000 0x00 0x100>;
0076 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
0077 clock-frequency = <48000000>;
0078 current-speed = <115200>;
0079 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
0080 clocks = <&k3_clks 287 0>;
0081 clock-names = "fclk";
0082 };
0083
0084 mcu_uart0: serial@40a00000 {
0085 compatible = "ti,j721e-uart", "ti,am654-uart";
0086 reg = <0x00 0x40a00000 0x00 0x100>;
0087 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
0088 clock-frequency = <96000000>;
0089 current-speed = <115200>;
0090 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
0091 clocks = <&k3_clks 149 0>;
0092 clock-names = "fclk";
0093 };
0094
0095 wkup_gpio_intr: interrupt-controller@42200000 {
0096 compatible = "ti,sci-intr";
0097 reg = <0x00 0x42200000 0x00 0x400>;
0098 ti,intr-trigger-type = <1>;
0099 interrupt-controller;
0100 interrupt-parent = <&gic500>;
0101 #interrupt-cells = <1>;
0102 ti,sci = <&dmsc>;
0103 ti,sci-dev-id = <137>;
0104 ti,interrupt-ranges = <16 960 16>;
0105 };
0106
0107 wkup_gpio0: gpio@42110000 {
0108 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0109 reg = <0x0 0x42110000 0x0 0x100>;
0110 gpio-controller;
0111 #gpio-cells = <2>;
0112 interrupt-parent = <&wkup_gpio_intr>;
0113 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
0114 interrupt-controller;
0115 #interrupt-cells = <2>;
0116 ti,ngpio = <84>;
0117 ti,davinci-gpio-unbanked = <0>;
0118 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
0119 clocks = <&k3_clks 113 0>;
0120 clock-names = "gpio";
0121 };
0122
0123 wkup_gpio1: gpio@42100000 {
0124 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0125 reg = <0x0 0x42100000 0x0 0x100>;
0126 gpio-controller;
0127 #gpio-cells = <2>;
0128 interrupt-parent = <&wkup_gpio_intr>;
0129 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
0130 interrupt-controller;
0131 #interrupt-cells = <2>;
0132 ti,ngpio = <84>;
0133 ti,davinci-gpio-unbanked = <0>;
0134 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0135 clocks = <&k3_clks 114 0>;
0136 clock-names = "gpio";
0137 };
0138
0139 mcu_i2c0: i2c@40b00000 {
0140 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0141 reg = <0x0 0x40b00000 0x0 0x100>;
0142 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
0143 #address-cells = <1>;
0144 #size-cells = <0>;
0145 clock-names = "fck";
0146 clocks = <&k3_clks 194 0>;
0147 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
0148 };
0149
0150 mcu_i2c1: i2c@40b10000 {
0151 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0152 reg = <0x0 0x40b10000 0x0 0x100>;
0153 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 clock-names = "fck";
0157 clocks = <&k3_clks 195 0>;
0158 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
0159 };
0160
0161 wkup_i2c0: i2c@42120000 {
0162 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0163 reg = <0x0 0x42120000 0x0 0x100>;
0164 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
0165 #address-cells = <1>;
0166 #size-cells = <0>;
0167 clock-names = "fck";
0168 clocks = <&k3_clks 197 0>;
0169 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
0170 };
0171
0172 fss: fss@47000000 {
0173 compatible = "simple-bus";
0174 reg = <0x0 0x47000000 0x0 0x100>;
0175 #address-cells = <2>;
0176 #size-cells = <2>;
0177 ranges;
0178
0179 ospi0: spi@47040000 {
0180 compatible = "ti,am654-ospi", "cdns,qspi-nor";
0181 reg = <0x0 0x47040000 0x0 0x100>,
0182 <0x5 0x00000000 0x1 0x0000000>;
0183 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
0184 cdns,fifo-depth = <256>;
0185 cdns,fifo-width = <4>;
0186 cdns,trigger-address = <0x0>;
0187 clocks = <&k3_clks 103 0>;
0188 assigned-clocks = <&k3_clks 103 0>;
0189 assigned-clock-parents = <&k3_clks 103 2>;
0190 assigned-clock-rates = <166666666>;
0191 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194 };
0195
0196 ospi1: spi@47050000 {
0197 compatible = "ti,am654-ospi", "cdns,qspi-nor";
0198 reg = <0x0 0x47050000 0x0 0x100>,
0199 <0x7 0x00000000 0x1 0x00000000>;
0200 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
0201 cdns,fifo-depth = <256>;
0202 cdns,fifo-width = <4>;
0203 cdns,trigger-address = <0x0>;
0204 clocks = <&k3_clks 104 0>;
0205 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 };
0209 };
0210
0211 tscadc0: tscadc@40200000 {
0212 compatible = "ti,am3359-tscadc";
0213 reg = <0x0 0x40200000 0x0 0x1000>;
0214 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
0215 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
0216 clocks = <&k3_clks 0 1>;
0217 assigned-clocks = <&k3_clks 0 3>;
0218 assigned-clock-rates = <60000000>;
0219 clock-names = "adc_tsc_fck";
0220 dmas = <&main_udmap 0x7400>,
0221 <&main_udmap 0x7401>;
0222 dma-names = "fifo0", "fifo1";
0223
0224 adc {
0225 #io-channel-cells = <1>;
0226 compatible = "ti,am3359-adc";
0227 };
0228 };
0229
0230 tscadc1: tscadc@40210000 {
0231 compatible = "ti,am3359-tscadc";
0232 reg = <0x0 0x40210000 0x0 0x1000>;
0233 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
0234 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
0235 clocks = <&k3_clks 1 1>;
0236 assigned-clocks = <&k3_clks 1 3>;
0237 assigned-clock-rates = <60000000>;
0238 clock-names = "adc_tsc_fck";
0239 dmas = <&main_udmap 0x7402>,
0240 <&main_udmap 0x7403>;
0241 dma-names = "fifo0", "fifo1";
0242
0243 adc {
0244 #io-channel-cells = <1>;
0245 compatible = "ti,am3359-adc";
0246 };
0247 };
0248
0249 mcu_navss: bus@28380000 {
0250 compatible = "simple-mfd";
0251 #address-cells = <2>;
0252 #size-cells = <2>;
0253 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
0254 dma-coherent;
0255 dma-ranges;
0256
0257 ti,sci-dev-id = <232>;
0258
0259 mcu_ringacc: ringacc@2b800000 {
0260 compatible = "ti,am654-navss-ringacc";
0261 reg = <0x0 0x2b800000 0x0 0x400000>,
0262 <0x0 0x2b000000 0x0 0x400000>,
0263 <0x0 0x28590000 0x0 0x100>,
0264 <0x0 0x2a500000 0x0 0x40000>;
0265 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0266 ti,num-rings = <286>;
0267 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0268 ti,sci = <&dmsc>;
0269 ti,sci-dev-id = <235>;
0270 msi-parent = <&main_udmass_inta>;
0271 };
0272
0273 mcu_udmap: dma-controller@285c0000 {
0274 compatible = "ti,j721e-navss-mcu-udmap";
0275 reg = <0x0 0x285c0000 0x0 0x100>,
0276 <0x0 0x2a800000 0x0 0x40000>,
0277 <0x0 0x2aa00000 0x0 0x40000>;
0278 reg-names = "gcfg", "rchanrt", "tchanrt";
0279 msi-parent = <&main_udmass_inta>;
0280 #dma-cells = <1>;
0281
0282 ti,sci = <&dmsc>;
0283 ti,sci-dev-id = <236>;
0284 ti,ringacc = <&mcu_ringacc>;
0285
0286 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0287 <0x0f>; /* TX_HCHAN */
0288 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0289 <0x0b>; /* RX_HCHAN */
0290 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0291 };
0292 };
0293
0294 mcu_cpsw: ethernet@46000000 {
0295 compatible = "ti,j721e-cpsw-nuss";
0296 #address-cells = <2>;
0297 #size-cells = <2>;
0298 reg = <0x0 0x46000000 0x0 0x200000>;
0299 reg-names = "cpsw_nuss";
0300 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
0301 dma-coherent;
0302 clocks = <&k3_clks 18 22>;
0303 clock-names = "fck";
0304 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
0305
0306 dmas = <&mcu_udmap 0xf000>,
0307 <&mcu_udmap 0xf001>,
0308 <&mcu_udmap 0xf002>,
0309 <&mcu_udmap 0xf003>,
0310 <&mcu_udmap 0xf004>,
0311 <&mcu_udmap 0xf005>,
0312 <&mcu_udmap 0xf006>,
0313 <&mcu_udmap 0xf007>,
0314 <&mcu_udmap 0x7000>;
0315 dma-names = "tx0", "tx1", "tx2", "tx3",
0316 "tx4", "tx5", "tx6", "tx7",
0317 "rx";
0318
0319 ethernet-ports {
0320 #address-cells = <1>;
0321 #size-cells = <0>;
0322
0323 cpsw_port1: port@1 {
0324 reg = <1>;
0325 ti,mac-only;
0326 label = "port1";
0327 ti,syscon-efuse = <&mcu_conf 0x200>;
0328 phys = <&phy_gmii_sel 1>;
0329 };
0330 };
0331
0332 davinci_mdio: mdio@f00 {
0333 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0334 reg = <0x0 0xf00 0x0 0x100>;
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337 clocks = <&k3_clks 18 22>;
0338 clock-names = "fck";
0339 bus_freq = <1000000>;
0340 };
0341
0342 cpts@3d000 {
0343 compatible = "ti,am65-cpts";
0344 reg = <0x0 0x3d000 0x0 0x400>;
0345 clocks = <&k3_clks 18 2>;
0346 clock-names = "cpts";
0347 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
0348 interrupt-names = "cpts";
0349 ti,cpts-ext-ts-inputs = <4>;
0350 ti,cpts-periodic-outputs = <2>;
0351 };
0352 };
0353
0354 mcu_r5fss0: r5fss@41000000 {
0355 compatible = "ti,j721e-r5fss";
0356 ti,cluster-mode = <1>;
0357 #address-cells = <1>;
0358 #size-cells = <1>;
0359 ranges = <0x41000000 0x00 0x41000000 0x20000>,
0360 <0x41400000 0x00 0x41400000 0x20000>;
0361 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
0362
0363 mcu_r5fss0_core0: r5f@41000000 {
0364 compatible = "ti,j721e-r5f";
0365 reg = <0x41000000 0x00008000>,
0366 <0x41010000 0x00008000>;
0367 reg-names = "atcm", "btcm";
0368 ti,sci = <&dmsc>;
0369 ti,sci-dev-id = <250>;
0370 ti,sci-proc-ids = <0x01 0xff>;
0371 resets = <&k3_reset 250 1>;
0372 firmware-name = "j7-mcu-r5f0_0-fw";
0373 ti,atcm-enable = <1>;
0374 ti,btcm-enable = <1>;
0375 ti,loczrama = <1>;
0376 };
0377
0378 mcu_r5fss0_core1: r5f@41400000 {
0379 compatible = "ti,j721e-r5f";
0380 reg = <0x41400000 0x00008000>,
0381 <0x41410000 0x00008000>;
0382 reg-names = "atcm", "btcm";
0383 ti,sci = <&dmsc>;
0384 ti,sci-dev-id = <251>;
0385 ti,sci-proc-ids = <0x02 0xff>;
0386 resets = <&k3_reset 251 1>;
0387 firmware-name = "j7-mcu-r5f0_1-fw";
0388 ti,atcm-enable = <1>;
0389 ti,btcm-enable = <1>;
0390 ti,loczrama = <1>;
0391 };
0392 };
0393
0394 mcu_mcan0: can@40528000 {
0395 compatible = "bosch,m_can";
0396 reg = <0x00 0x40528000 0x00 0x200>,
0397 <0x00 0x40500000 0x00 0x8000>;
0398 reg-names = "m_can", "message_ram";
0399 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
0400 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
0401 clock-names = "hclk", "cclk";
0402 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
0403 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
0404 interrupt-names = "int0", "int1";
0405 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0406 };
0407
0408 mcu_mcan1: can@40568000 {
0409 compatible = "bosch,m_can";
0410 reg = <0x00 0x40568000 0x00 0x200>,
0411 <0x00 0x40540000 0x00 0x8000>;
0412 reg-names = "m_can", "message_ram";
0413 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
0414 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
0415 clock-names = "hclk", "cclk";
0416 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
0417 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
0418 interrupt-names = "int0", "int1";
0419 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0420 };
0421 };
