0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "k3-j721e-som-p0.dtsi"
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/net/ti-dp83867.h>
0012 #include <dt-bindings/phy/phy-cadence.h>
0013
0014 / {
0015 compatible = "ti,j721e-evm", "ti,j721e";
0016 model = "Texas Instruments J721e EVM";
0017
0018 chosen {
0019 stdout-path = "serial2:115200n8";
0020 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
0021 };
0022
0023 gpio_keys: gpio-keys {
0024 compatible = "gpio-keys";
0025 autorepeat;
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
0028
0029 sw10: switch-10 {
0030 label = "GPIO Key USER1";
0031 linux,code = <BTN_0>;
0032 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
0033 };
0034
0035 sw11: switch-11 {
0036 label = "GPIO Key USER2";
0037 linux,code = <BTN_1>;
0038 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
0039 };
0040 };
0041
0042 evm_12v0: fixedregulator-evm12v0 {
0043 /* main supply */
0044 compatible = "regulator-fixed";
0045 regulator-name = "evm_12v0";
0046 regulator-min-microvolt = <12000000>;
0047 regulator-max-microvolt = <12000000>;
0048 regulator-always-on;
0049 regulator-boot-on;
0050 };
0051
0052 vsys_3v3: fixedregulator-vsys3v3 {
0053 /* Output of LMS140 */
0054 compatible = "regulator-fixed";
0055 regulator-name = "vsys_3v3";
0056 regulator-min-microvolt = <3300000>;
0057 regulator-max-microvolt = <3300000>;
0058 vin-supply = <&evm_12v0>;
0059 regulator-always-on;
0060 regulator-boot-on;
0061 };
0062
0063 vsys_5v0: fixedregulator-vsys5v0 {
0064 /* Output of LM5140 */
0065 compatible = "regulator-fixed";
0066 regulator-name = "vsys_5v0";
0067 regulator-min-microvolt = <5000000>;
0068 regulator-max-microvolt = <5000000>;
0069 vin-supply = <&evm_12v0>;
0070 regulator-always-on;
0071 regulator-boot-on;
0072 };
0073
0074 vdd_mmc1: fixedregulator-sd {
0075 compatible = "regulator-fixed";
0076 regulator-name = "vdd_mmc1";
0077 regulator-min-microvolt = <3300000>;
0078 regulator-max-microvolt = <3300000>;
0079 regulator-boot-on;
0080 enable-active-high;
0081 vin-supply = <&vsys_3v3>;
0082 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
0083 };
0084
0085 vdd_sd_dv_alt: gpio-regulator-TLV71033 {
0086 compatible = "regulator-gpio";
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
0089 regulator-name = "tlv71033";
0090 regulator-min-microvolt = <1800000>;
0091 regulator-max-microvolt = <3300000>;
0092 regulator-boot-on;
0093 vin-supply = <&vsys_5v0>;
0094 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
0095 states = <1800000 0x0>,
0096 <3300000 0x1>;
0097 };
0098
0099 sound0: sound@0 {
0100 compatible = "ti,j721e-cpb-audio";
0101 model = "j721e-cpb";
0102
0103 ti,cpb-mcasp = <&mcasp10>;
0104 ti,cpb-codec = <&pcm3168a_1>;
0105
0106 clocks = <&k3_clks 184 1>,
0107 <&k3_clks 184 2>, <&k3_clks 184 4>,
0108 <&k3_clks 157 371>,
0109 <&k3_clks 157 400>, <&k3_clks 157 401>;
0110 clock-names = "cpb-mcasp-auxclk",
0111 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
0112 "cpb-codec-scki",
0113 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
0114 };
0115
0116 transceiver1: can-phy0 {
0117 compatible = "ti,tcan1043";
0118 #phy-cells = <0>;
0119 max-bitrate = <5000000>;
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
0122 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
0123 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
0124 };
0125
0126 transceiver2: can-phy1 {
0127 compatible = "ti,tcan1042";
0128 #phy-cells = <0>;
0129 max-bitrate = <5000000>;
0130 pinctrl-names = "default";
0131 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
0132 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
0133 };
0134
0135 transceiver3: can-phy2 {
0136 compatible = "ti,tcan1043";
0137 #phy-cells = <0>;
0138 max-bitrate = <5000000>;
0139 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
0140 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
0141 };
0142
0143 transceiver4: can-phy3 {
0144 compatible = "ti,tcan1042";
0145 #phy-cells = <0>;
0146 max-bitrate = <5000000>;
0147 pinctrl-names = "default";
0148 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
0149 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
0150 };
0151
0152 dp_pwr_3v3: regulator-dp-pwr {
0153 compatible = "regulator-fixed";
0154 regulator-name = "dp-pwr";
0155 regulator-min-microvolt = <3300000>;
0156 regulator-max-microvolt = <3300000>;
0157 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
0158 enable-active-high;
0159 };
0160
0161 dp0: connector {
0162 compatible = "dp-connector";
0163 label = "DP0";
0164 type = "full-size";
0165 dp-pwr-supply = <&dp_pwr_3v3>;
0166
0167 port {
0168 dp_connector_in: endpoint {
0169 remote-endpoint = <&dp0_out>;
0170 };
0171 };
0172 };
0173 };
0174
0175 &main_pmx0 {
0176 sw10_button_pins_default: sw10-button-pins-default {
0177 pinctrl-single,pins = <
0178 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
0179 >;
0180 };
0181
0182 main_mmc1_pins_default: main-mmc1-pins-default {
0183 pinctrl-single,pins = <
0184 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
0185 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
0186 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
0187 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
0188 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
0189 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
0190 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
0191 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
0192 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
0193 >;
0194 };
0195
0196 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
0197 pinctrl-single,pins = <
0198 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
0199 >;
0200 };
0201
0202 main_usbss0_pins_default: main-usbss0-pins-default {
0203 pinctrl-single,pins = <
0204 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
0205 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
0206 >;
0207 };
0208
0209 main_usbss1_pins_default: main-usbss1-pins-default {
0210 pinctrl-single,pins = <
0211 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
0212 >;
0213 };
0214
0215 dp0_pins_default: dp0-pins-default {
0216 pinctrl-single,pins = <
0217 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
0218 >;
0219 };
0220
0221 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
0222 pinctrl-single,pins = <
0223 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
0224 >;
0225 };
0226
0227 main_i2c0_pins_default: main-i2c0-pins-default {
0228 pinctrl-single,pins = <
0229 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
0230 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
0231 >;
0232 };
0233
0234 main_i2c1_pins_default: main-i2c1-pins-default {
0235 pinctrl-single,pins = <
0236 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
0237 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
0238 >;
0239 };
0240
0241 main_i2c3_pins_default: main-i2c3-pins-default {
0242 pinctrl-single,pins = <
0243 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
0244 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
0245 >;
0246 };
0247
0248 main_i2c6_pins_default: main-i2c6-pins-default {
0249 pinctrl-single,pins = <
0250 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
0251 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
0252 >;
0253 };
0254
0255 mcasp10_pins_default: mcasp10-pins-default {
0256 pinctrl-single,pins = <
0257 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
0258 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
0259 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
0260 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
0261 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
0262 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
0263 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
0264 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
0265 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
0266 >;
0267 };
0268
0269 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
0270 pinctrl-single,pins = <
0271 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
0272 >;
0273 };
0274
0275 main_mcan0_pins_default: main-mcan0-pins-default {
0276 pinctrl-single,pins = <
0277 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
0278 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
0279 >;
0280 };
0281
0282 main_mcan2_pins_default: main-mcan2-pins-default {
0283 pinctrl-single,pins = <
0284 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
0285 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
0286 >;
0287 };
0288
0289 main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
0290 pinctrl-single,pins = <
0291 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
0292 >;
0293 };
0294 };
0295
0296 &wkup_pmx0 {
0297 sw11_button_pins_default: sw11-button-pins-default {
0298 pinctrl-single,pins = <
0299 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
0300 >;
0301 };
0302
0303 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
0304 pinctrl-single,pins = <
0305 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
0306 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
0307 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
0308 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
0309 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
0310 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
0311 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
0312 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
0313 >;
0314 };
0315
0316 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
0317 pinctrl-single,pins = <
0318 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
0319 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
0320 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
0321 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
0322 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
0323 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
0324 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
0325 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
0326 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
0327 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
0328 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
0329 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
0330 >;
0331 };
0332
0333 mcu_mdio_pins_default: mcu-mdio1-pins-default {
0334 pinctrl-single,pins = <
0335 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
0336 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
0337 >;
0338 };
0339
0340 mcu_mcan0_pins_default: mcu-mcan0-pins-default {
0341 pinctrl-single,pins = <
0342 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
0343 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
0344 >;
0345 };
0346
0347 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
0348 pinctrl-single,pins = <
0349 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
0350 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
0351 >;
0352 };
0353
0354 mcu_mcan1_pins_default: mcu-mcan1-pins-default {
0355 pinctrl-single,pins = <
0356 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
0357 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
0358 >;
0359 };
0360
0361 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
0362 pinctrl-single,pins = <
0363 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
0364 >;
0365 };
0366 };
0367
0368 &wkup_uart0 {
0369 /* Wakeup UART is used by System firmware */
0370 status = "reserved";
0371 };
0372
0373 &main_uart0 {
0374 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
0375 };
0376
0377 &main_uart3 {
0378 /* UART not brought out */
0379 status = "disabled";
0380 };
0381
0382 &main_uart5 {
0383 /* UART not brought out */
0384 status = "disabled";
0385 };
0386
0387 &main_uart6 {
0388 /* UART not brought out */
0389 status = "disabled";
0390 };
0391
0392 &main_uart7 {
0393 /* UART not brought out */
0394 status = "disabled";
0395 };
0396
0397 &main_uart8 {
0398 /* UART not brought out */
0399 status = "disabled";
0400 };
0401
0402 &main_uart9 {
0403 /* UART not brought out */
0404 status = "disabled";
0405 };
0406
0407 &main_gpio2 {
0408 status = "disabled";
0409 };
0410
0411 &main_gpio3 {
0412 status = "disabled";
0413 };
0414
0415 &main_gpio4 {
0416 status = "disabled";
0417 };
0418
0419 &main_gpio5 {
0420 status = "disabled";
0421 };
0422
0423 &main_gpio6 {
0424 status = "disabled";
0425 };
0426
0427 &main_gpio7 {
0428 status = "disabled";
0429 };
0430
0431 &wkup_gpio1 {
0432 status = "disabled";
0433 };
0434
0435 &main_sdhci0 {
0436 /* eMMC */
0437 non-removable;
0438 ti,driver-strength-ohm = <50>;
0439 disable-wp;
0440 };
0441
0442 &main_sdhci1 {
0443 /* SD/MMC */
0444 vmmc-supply = <&vdd_mmc1>;
0445 vqmmc-supply = <&vdd_sd_dv_alt>;
0446 pinctrl-names = "default";
0447 pinctrl-0 = <&main_mmc1_pins_default>;
0448 ti,driver-strength-ohm = <50>;
0449 disable-wp;
0450 };
0451
0452 &main_sdhci2 {
0453 /* Unused */
0454 status = "disabled";
0455 };
0456
0457 &usb_serdes_mux {
0458 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
0459 };
0460
0461 &serdes_ln_ctrl {
0462 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
0463 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
0464 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
0465 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
0466 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
0467 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
0468 };
0469
0470 &serdes_wiz3 {
0471 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
0472 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
0473 };
0474
0475 &serdes3 {
0476 serdes3_usb_link: phy@0 {
0477 reg = <0>;
0478 cdns,num-lanes = <2>;
0479 #phy-cells = <0>;
0480 cdns,phy-type = <PHY_TYPE_USB3>;
0481 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
0482 };
0483 };
0484
0485 &usbss0 {
0486 pinctrl-names = "default";
0487 pinctrl-0 = <&main_usbss0_pins_default>;
0488 ti,vbus-divider;
0489 };
0490
0491 &usb0 {
0492 dr_mode = "otg";
0493 maximum-speed = "super-speed";
0494 phys = <&serdes3_usb_link>;
0495 phy-names = "cdns3,usb3-phy";
0496 };
0497
0498 &usbss1 {
0499 pinctrl-names = "default";
0500 pinctrl-0 = <&main_usbss1_pins_default>;
0501 ti,usb2-only;
0502 };
0503
0504 &usb1 {
0505 dr_mode = "host";
0506 maximum-speed = "high-speed";
0507 };
0508
0509 &ospi1 {
0510 pinctrl-names = "default";
0511 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
0512
0513 flash@0 {
0514 compatible = "jedec,spi-nor";
0515 reg = <0x0>;
0516 spi-tx-bus-width = <1>;
0517 spi-rx-bus-width = <4>;
0518 spi-max-frequency = <40000000>;
0519 cdns,tshsl-ns = <60>;
0520 cdns,tsd2d-ns = <60>;
0521 cdns,tchsh-ns = <60>;
0522 cdns,tslch-ns = <60>;
0523 cdns,read-delay = <2>;
0524 };
0525 };
0526
0527 &tscadc0 {
0528 adc {
0529 ti,adc-channels = <0 1 2 3 4 5 6 7>;
0530 };
0531 };
0532
0533 &tscadc1 {
0534 adc {
0535 ti,adc-channels = <0 1 2 3 4 5 6 7>;
0536 };
0537 };
0538
0539 &main_i2c0 {
0540 pinctrl-names = "default";
0541 pinctrl-0 = <&main_i2c0_pins_default>;
0542 clock-frequency = <400000>;
0543
0544 exp1: gpio@20 {
0545 compatible = "ti,tca6416";
0546 reg = <0x20>;
0547 gpio-controller;
0548 #gpio-cells = <2>;
0549 };
0550
0551 exp2: gpio@22 {
0552 compatible = "ti,tca6424";
0553 reg = <0x22>;
0554 gpio-controller;
0555 #gpio-cells = <2>;
0556
0557 p09-hog {
0558 /* P11 - MCASP/TRACE_MUX_S0 */
0559 gpio-hog;
0560 gpios = <9 GPIO_ACTIVE_HIGH>;
0561 output-low;
0562 line-name = "MCASP/TRACE_MUX_S0";
0563 };
0564
0565 p10-hog {
0566 /* P12 - MCASP/TRACE_MUX_S1 */
0567 gpio-hog;
0568 gpios = <10 GPIO_ACTIVE_HIGH>;
0569 output-high;
0570 line-name = "MCASP/TRACE_MUX_S1";
0571 };
0572 };
0573 };
0574
0575 &main_i2c1 {
0576 pinctrl-names = "default";
0577 pinctrl-0 = <&main_i2c1_pins_default>;
0578 clock-frequency = <400000>;
0579
0580 exp4: gpio@20 {
0581 compatible = "ti,tca6408";
0582 reg = <0x20>;
0583 gpio-controller;
0584 #gpio-cells = <2>;
0585 pinctrl-names = "default";
0586 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
0587 interrupt-parent = <&main_gpio1>;
0588 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
0589 interrupt-controller;
0590 #interrupt-cells = <2>;
0591 };
0592 };
0593
0594 &k3_clks {
0595 /* Confiure AUDIO_EXT_REFCLK2 pin as output */
0596 pinctrl-names = "default";
0597 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
0598 };
0599
0600 &main_i2c3 {
0601 pinctrl-names = "default";
0602 pinctrl-0 = <&main_i2c3_pins_default>;
0603 clock-frequency = <400000>;
0604
0605 exp3: gpio@20 {
0606 compatible = "ti,tca6408";
0607 reg = <0x20>;
0608 gpio-controller;
0609 #gpio-cells = <2>;
0610 };
0611
0612 pcm3168a_1: audio-codec@44 {
0613 compatible = "ti,pcm3168a";
0614 reg = <0x44>;
0615
0616 #sound-dai-cells = <1>;
0617
0618 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
0619
0620 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
0621 clocks = <&k3_clks 157 371>;
0622 clock-names = "scki";
0623
0624 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
0625 assigned-clocks = <&k3_clks 157 371>;
0626 assigned-clock-parents = <&k3_clks 157 400>;
0627 assigned-clock-rates = <24576000>; /* for 48KHz */
0628
0629 VDD1-supply = <&vsys_3v3>;
0630 VDD2-supply = <&vsys_3v3>;
0631 VCCAD1-supply = <&vsys_5v0>;
0632 VCCAD2-supply = <&vsys_5v0>;
0633 VCCDA1-supply = <&vsys_5v0>;
0634 VCCDA2-supply = <&vsys_5v0>;
0635 };
0636 };
0637
0638 &main_i2c6 {
0639 pinctrl-names = "default";
0640 pinctrl-0 = <&main_i2c6_pins_default>;
0641 clock-frequency = <400000>;
0642
0643 exp5: gpio@20 {
0644 compatible = "ti,tca6408";
0645 reg = <0x20>;
0646 gpio-controller;
0647 #gpio-cells = <2>;
0648 };
0649 };
0650
0651 &mcu_cpsw {
0652 pinctrl-names = "default";
0653 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
0654 };
0655
0656 &davinci_mdio {
0657 phy0: ethernet-phy@0 {
0658 reg = <0>;
0659 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0660 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0661 };
0662 };
0663
0664 &cpsw_port1 {
0665 phy-mode = "rgmii-rxid";
0666 phy-handle = <&phy0>;
0667 };
0668
0669 &dss {
0670 /*
0671 * These clock assignments are chosen to enable the following outputs:
0672 *
0673 * VP0 - DisplayPort SST
0674 * VP1 - DPI0
0675 * VP2 - DSI
0676 * VP3 - DPI1
0677 */
0678
0679 assigned-clocks = <&k3_clks 152 1>,
0680 <&k3_clks 152 4>,
0681 <&k3_clks 152 9>,
0682 <&k3_clks 152 13>;
0683 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
0684 <&k3_clks 152 6>, /* PLL19_HSDIV0 */
0685 <&k3_clks 152 11>, /* PLL18_HSDIV0 */
0686 <&k3_clks 152 18>; /* PLL23_HSDIV0 */
0687 };
0688
0689 &dss_ports {
0690 port {
0691 dpi0_out: endpoint {
0692 remote-endpoint = <&dp0_in>;
0693 };
0694 };
0695 };
0696
0697 &dp0_ports {
0698 #address-cells = <1>;
0699 #size-cells = <0>;
0700
0701 port@0 {
0702 reg = <0>;
0703 dp0_in: endpoint {
0704 remote-endpoint = <&dpi0_out>;
0705 };
0706 };
0707
0708 port@4 {
0709 reg = <4>;
0710 dp0_out: endpoint {
0711 remote-endpoint = <&dp_connector_in>;
0712 };
0713 };
0714 };
0715
0716 &mcasp0 {
0717 status = "disabled";
0718 };
0719
0720 &mcasp1 {
0721 status = "disabled";
0722 };
0723
0724 &mcasp2 {
0725 status = "disabled";
0726 };
0727
0728 &mcasp3 {
0729 status = "disabled";
0730 };
0731
0732 &mcasp4 {
0733 status = "disabled";
0734 };
0735
0736 &mcasp5 {
0737 status = "disabled";
0738 };
0739
0740 &mcasp6 {
0741 status = "disabled";
0742 };
0743
0744 &mcasp7 {
0745 status = "disabled";
0746 };
0747
0748 &mcasp8 {
0749 status = "disabled";
0750 };
0751
0752 &mcasp9 {
0753 status = "disabled";
0754 };
0755
0756 &mcasp10 {
0757 #sound-dai-cells = <0>;
0758
0759 pinctrl-names = "default";
0760 pinctrl-0 = <&mcasp10_pins_default>;
0761
0762 op-mode = <0>; /* MCASP_IIS_MODE */
0763 tdm-slots = <2>;
0764 auxclk-fs-ratio = <256>;
0765
0766 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0767 1 1 1 1
0768 2 2 2 0
0769 >;
0770 tx-num-evt = <0>;
0771 rx-num-evt = <0>;
0772 };
0773
0774 &mcasp11 {
0775 status = "disabled";
0776 };
0777
0778 &cmn_refclk1 {
0779 clock-frequency = <100000000>;
0780 };
0781
0782 &wiz0_pll1_refclk {
0783 assigned-clocks = <&wiz0_pll1_refclk>;
0784 assigned-clock-parents = <&cmn_refclk1>;
0785 };
0786
0787 &wiz0_refclk_dig {
0788 assigned-clocks = <&wiz0_refclk_dig>;
0789 assigned-clock-parents = <&cmn_refclk1>;
0790 };
0791
0792 &wiz1_pll1_refclk {
0793 assigned-clocks = <&wiz1_pll1_refclk>;
0794 assigned-clock-parents = <&cmn_refclk1>;
0795 };
0796
0797 &wiz1_refclk_dig {
0798 assigned-clocks = <&wiz1_refclk_dig>;
0799 assigned-clock-parents = <&cmn_refclk1>;
0800 };
0801
0802 &wiz2_pll1_refclk {
0803 assigned-clocks = <&wiz2_pll1_refclk>;
0804 assigned-clock-parents = <&cmn_refclk1>;
0805 };
0806
0807 &wiz2_refclk_dig {
0808 assigned-clocks = <&wiz2_refclk_dig>;
0809 assigned-clock-parents = <&cmn_refclk1>;
0810 };
0811
0812 &serdes0 {
0813 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
0814 assigned-clock-parents = <&wiz0_pll1_refclk>;
0815
0816 serdes0_pcie_link: phy@0 {
0817 reg = <0>;
0818 cdns,num-lanes = <1>;
0819 #phy-cells = <0>;
0820 cdns,phy-type = <PHY_TYPE_PCIE>;
0821 resets = <&serdes_wiz0 1>;
0822 };
0823 };
0824
0825 &serdes1 {
0826 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
0827 assigned-clock-parents = <&wiz1_pll1_refclk>;
0828
0829 serdes1_pcie_link: phy@0 {
0830 reg = <0>;
0831 cdns,num-lanes = <2>;
0832 #phy-cells = <0>;
0833 cdns,phy-type = <PHY_TYPE_PCIE>;
0834 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
0835 };
0836 };
0837
0838 &serdes2 {
0839 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
0840 assigned-clock-parents = <&wiz2_pll1_refclk>;
0841
0842 serdes2_pcie_link: phy@0 {
0843 reg = <0>;
0844 cdns,num-lanes = <2>;
0845 #phy-cells = <0>;
0846 cdns,phy-type = <PHY_TYPE_PCIE>;
0847 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
0848 };
0849 };
0850
0851 &serdes4 {
0852 torrent_phy_dp: phy@0 {
0853 reg = <0>;
0854 resets = <&serdes_wiz4 1>;
0855 cdns,phy-type = <PHY_TYPE_DP>;
0856 cdns,num-lanes = <4>;
0857 cdns,max-bit-rate = <5400>;
0858 #phy-cells = <0>;
0859 };
0860 };
0861
0862 &mhdp {
0863 phys = <&torrent_phy_dp>;
0864 phy-names = "dpphy";
0865 pinctrl-names = "default";
0866 pinctrl-0 = <&dp0_pins_default>;
0867 };
0868
0869 &pcie0_rc {
0870 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
0871 phys = <&serdes0_pcie_link>;
0872 phy-names = "pcie-phy";
0873 num-lanes = <1>;
0874 };
0875
0876 &pcie1_rc {
0877 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
0878 phys = <&serdes1_pcie_link>;
0879 phy-names = "pcie-phy";
0880 num-lanes = <2>;
0881 };
0882
0883 &pcie2_rc {
0884 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
0885 phys = <&serdes2_pcie_link>;
0886 phy-names = "pcie-phy";
0887 num-lanes = <2>;
0888 };
0889
0890 &pcie0_ep {
0891 phys = <&serdes0_pcie_link>;
0892 phy-names = "pcie-phy";
0893 num-lanes = <1>;
0894 status = "disabled";
0895 };
0896
0897 &pcie1_ep {
0898 phys = <&serdes1_pcie_link>;
0899 phy-names = "pcie-phy";
0900 num-lanes = <2>;
0901 status = "disabled";
0902 };
0903
0904 &pcie2_ep {
0905 phys = <&serdes2_pcie_link>;
0906 phy-names = "pcie-phy";
0907 num-lanes = <2>;
0908 status = "disabled";
0909 };
0910
0911 &pcie3_rc {
0912 status = "disabled";
0913 };
0914
0915 &pcie3_ep {
0916 status = "disabled";
0917 };
0918
0919 &icssg0_mdio {
0920 status = "disabled";
0921 };
0922
0923 &icssg1_mdio {
0924 status = "disabled";
0925 };
0926
0927 &mcu_mcan0 {
0928 pinctrl-names = "default";
0929 pinctrl-0 = <&mcu_mcan0_pins_default>;
0930 phys = <&transceiver1>;
0931 };
0932
0933 &mcu_mcan1 {
0934 pinctrl-names = "default";
0935 pinctrl-0 = <&mcu_mcan1_pins_default>;
0936 phys = <&transceiver2>;
0937 };
0938
0939 &main_mcan0 {
0940 pinctrl-names = "default";
0941 pinctrl-0 = <&main_mcan0_pins_default>;
0942 phys = <&transceiver3>;
0943 };
0944
0945 &main_mcan1 {
0946 status = "disabled";
0947 };
0948
0949 &main_mcan2 {
0950 pinctrl-names = "default";
0951 pinctrl-0 = <&main_mcan2_pins_default>;
0952 phys = <&transceiver4>;
0953 };
0954
0955 &main_mcan3 {
0956 status = "disabled";
0957 };
0958
0959 &main_mcan4 {
0960 status = "disabled";
0961 };
0962
0963 &main_mcan5 {
0964 status = "disabled";
0965 };
0966
0967 &main_mcan6 {
0968 status = "disabled";
0969 };
0970
0971 &main_mcan7 {
0972 status = "disabled";
0973 };
0974
0975 &main_mcan8 {
0976 status = "disabled";
0977 };
0978
0979 &main_mcan9 {
0980 status = "disabled";
0981 };
0982
0983 &main_mcan10 {
0984 status = "disabled";
0985 };
0986
0987 &main_mcan11 {
0988 status = "disabled";
0989 };
0990
0991 &main_mcan12 {
0992 status = "disabled";
0993 };
0994
0995 &main_mcan13 {
0996 status = "disabled";
0997 };
