0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J7200 SoC Family
0004 *
0005 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/pinctrl/k3.h>
0011 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0012
0013 / {
0014 model = "Texas Instruments K3 J7200 SoC";
0015 compatible = "ti,j7200";
0016 interrupt-parent = <&gic500>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 serial0 = &wkup_uart0;
0022 serial1 = &mcu_uart0;
0023 serial2 = &main_uart0;
0024 serial3 = &main_uart1;
0025 serial4 = &main_uart2;
0026 serial5 = &main_uart3;
0027 serial6 = &main_uart4;
0028 serial7 = &main_uart5;
0029 serial8 = &main_uart6;
0030 serial9 = &main_uart7;
0031 serial10 = &main_uart8;
0032 serial11 = &main_uart9;
0033 mmc0 = &main_sdhci0;
0034 mmc1 = &main_sdhci1;
0035 };
0036
0037 chosen { };
0038
0039 cpus {
0040 #address-cells = <1>;
0041 #size-cells = <0>;
0042 cpu-map {
0043 cluster0: cluster0 {
0044 core0 {
0045 cpu = <&cpu0>;
0046 };
0047
0048 core1 {
0049 cpu = <&cpu1>;
0050 };
0051 };
0052
0053 };
0054
0055 cpu0: cpu@0 {
0056 compatible = "arm,cortex-a72";
0057 reg = <0x000>;
0058 device_type = "cpu";
0059 enable-method = "psci";
0060 i-cache-size = <0xc000>;
0061 i-cache-line-size = <64>;
0062 i-cache-sets = <256>;
0063 d-cache-size = <0x8000>;
0064 d-cache-line-size = <64>;
0065 d-cache-sets = <256>;
0066 next-level-cache = <&L2_0>;
0067 };
0068
0069 cpu1: cpu@1 {
0070 compatible = "arm,cortex-a72";
0071 reg = <0x001>;
0072 device_type = "cpu";
0073 enable-method = "psci";
0074 i-cache-size = <0xc000>;
0075 i-cache-line-size = <64>;
0076 i-cache-sets = <256>;
0077 d-cache-size = <0x8000>;
0078 d-cache-line-size = <64>;
0079 d-cache-sets = <256>;
0080 next-level-cache = <&L2_0>;
0081 };
0082 };
0083
0084 L2_0: l2-cache0 {
0085 compatible = "cache";
0086 cache-level = <2>;
0087 cache-size = <0x100000>;
0088 cache-line-size = <64>;
0089 cache-sets = <1024>;
0090 next-level-cache = <&msmc_l3>;
0091 };
0092
0093 msmc_l3: l3-cache0 {
0094 compatible = "cache";
0095 cache-level = <3>;
0096 };
0097
0098 firmware {
0099 optee {
0100 compatible = "linaro,optee-tz";
0101 method = "smc";
0102 };
0103
0104 psci: psci {
0105 compatible = "arm,psci-1.0";
0106 method = "smc";
0107 };
0108 };
0109
0110 a72_timer0: timer-cl0-cpu0 {
0111 compatible = "arm,armv8-timer";
0112 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
0113 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
0114 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
0115 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
0116 };
0117
0118 pmu: pmu {
0119 compatible = "arm,cortex-a72-pmu";
0120 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0121 };
0122
0123 cbass_main: bus@100000 {
0124 compatible = "simple-bus";
0125 #address-cells = <2>;
0126 #size-cells = <2>;
0127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
0128 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
0129 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
0130 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
0131 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
0132 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
0133 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
0134 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
0135 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
0136
0137 /* MCUSS_WKUP Range */
0138 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
0139 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
0140 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
0141 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
0142 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
0143 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
0144 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
0145 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
0146 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
0147 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
0148 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
0149 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
0150 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
0151
0152 cbass_mcu_wakeup: bus@28380000 {
0153 compatible = "simple-bus";
0154 #address-cells = <2>;
0155 #size-cells = <2>;
0156 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
0157 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
0158 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
0159 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
0160 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
0161 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
0162 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
0163 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
0164 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
0165 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
0166 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
0167 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
0168 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
0169 };
0170 };
0171 };
0172
0173 /* Now include the peripherals for each bus segments */
0174 #include "k3-j7200-main.dtsi"
0175 #include "k3-j7200-mcu-wakeup.dtsi"
