0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "k3-j7200.dtsi"
0009
0010 / {
0011 memory@80000000 {
0012 device_type = "memory";
0013 /* 4G RAM */
0014 reg = <0x00 0x80000000 0x00 0x80000000>,
0015 <0x08 0x80000000 0x00 0x80000000>;
0016 };
0017
0018 reserved_memory: reserved-memory {
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021 ranges;
0022
0023 secure_ddr: optee@9e800000 {
0024 reg = <0x00 0x9e800000 0x00 0x01800000>;
0025 alignment = <0x1000>;
0026 no-map;
0027 };
0028
0029 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
0030 compatible = "shared-dma-pool";
0031 reg = <0x00 0xa0000000 0x00 0x100000>;
0032 no-map;
0033 };
0034
0035 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
0036 compatible = "shared-dma-pool";
0037 reg = <0x00 0xa0100000 0x00 0xf00000>;
0038 no-map;
0039 };
0040
0041 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
0042 compatible = "shared-dma-pool";
0043 reg = <0x00 0xa1000000 0x00 0x100000>;
0044 no-map;
0045 };
0046
0047 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
0048 compatible = "shared-dma-pool";
0049 reg = <0x00 0xa1100000 0x00 0xf00000>;
0050 no-map;
0051 };
0052
0053 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
0054 compatible = "shared-dma-pool";
0055 reg = <0x00 0xa2000000 0x00 0x100000>;
0056 no-map;
0057 };
0058
0059 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
0060 compatible = "shared-dma-pool";
0061 reg = <0x00 0xa2100000 0x00 0xf00000>;
0062 no-map;
0063 };
0064
0065 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
0066 compatible = "shared-dma-pool";
0067 reg = <0x00 0xa3000000 0x00 0x100000>;
0068 no-map;
0069 };
0070
0071 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
0072 compatible = "shared-dma-pool";
0073 reg = <0x00 0xa3100000 0x00 0xf00000>;
0074 no-map;
0075 };
0076
0077 rtos_ipc_memory_region: ipc-memories@a4000000 {
0078 reg = <0x00 0xa4000000 0x00 0x00800000>;
0079 alignment = <0x1000>;
0080 no-map;
0081 };
0082 };
0083 };
0084
0085 &wkup_pmx0 {
0086 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
0087 pinctrl-single,pins = <
0088 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
0089 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
0090 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
0091 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
0092 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
0093 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
0094 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
0095 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
0096 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
0097 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
0098 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
0099 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
0100 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
0101 >;
0102 };
0103
0104 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
0105 pinctrl-single,pins = <
0106 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
0107 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
0108 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
0109 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
0110 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
0111 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
0112 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
0113 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
0114 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
0115 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
0116 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
0117 >;
0118 };
0119 };
0120
0121 &main_pmx0 {
0122 main_i2c0_pins_default: main-i2c0-pins-default {
0123 pinctrl-single,pins = <
0124 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
0125 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
0126 >;
0127 };
0128 };
0129
0130 &hbmc {
0131 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
0132 * appropriate node based on board detection
0133 */
0134 status = "disabled";
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
0137 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
0138 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
0139
0140 flash@0,0 {
0141 compatible = "cypress,hyperflash", "cfi-flash";
0142 reg = <0x00 0x00 0x4000000>;
0143 };
0144 };
0145
0146 &mailbox0_cluster0 {
0147 interrupts = <436>;
0148
0149 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
0150 ti,mbox-rx = <0 0 0>;
0151 ti,mbox-tx = <1 0 0>;
0152 };
0153
0154 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
0155 ti,mbox-rx = <2 0 0>;
0156 ti,mbox-tx = <3 0 0>;
0157 };
0158 };
0159
0160 &mailbox0_cluster1 {
0161 interrupts = <432>;
0162
0163 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
0164 ti,mbox-rx = <0 0 0>;
0165 ti,mbox-tx = <1 0 0>;
0166 };
0167
0168 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
0169 ti,mbox-rx = <2 0 0>;
0170 ti,mbox-tx = <3 0 0>;
0171 };
0172 };
0173
0174 &mailbox0_cluster2 {
0175 status = "disabled";
0176 };
0177
0178 &mailbox0_cluster3 {
0179 status = "disabled";
0180 };
0181
0182 &mailbox0_cluster4 {
0183 status = "disabled";
0184 };
0185
0186 &mailbox0_cluster5 {
0187 status = "disabled";
0188 };
0189
0190 &mailbox0_cluster6 {
0191 status = "disabled";
0192 };
0193
0194 &mailbox0_cluster7 {
0195 status = "disabled";
0196 };
0197
0198 &mailbox0_cluster8 {
0199 status = "disabled";
0200 };
0201
0202 &mailbox0_cluster9 {
0203 status = "disabled";
0204 };
0205
0206 &mailbox0_cluster10 {
0207 status = "disabled";
0208 };
0209
0210 &mailbox0_cluster11 {
0211 status = "disabled";
0212 };
0213
0214 &mcu_r5fss0_core0 {
0215 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
0216 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
0217 <&mcu_r5fss0_core0_memory_region>;
0218 };
0219
0220 &mcu_r5fss0_core1 {
0221 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
0222 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
0223 <&mcu_r5fss0_core1_memory_region>;
0224 };
0225
0226 &main_r5fss0_core0 {
0227 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
0228 memory-region = <&main_r5fss0_core0_dma_memory_region>,
0229 <&main_r5fss0_core0_memory_region>;
0230 };
0231
0232 &main_r5fss0_core1 {
0233 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
0234 memory-region = <&main_r5fss0_core1_dma_memory_region>,
0235 <&main_r5fss0_core1_memory_region>;
0236 };
0237
0238 &main_i2c0 {
0239 pinctrl-names = "default";
0240 pinctrl-0 = <&main_i2c0_pins_default>;
0241 clock-frequency = <400000>;
0242
0243 exp_som: gpio@21 {
0244 compatible = "ti,tca6408";
0245 reg = <0x21>;
0246 gpio-controller;
0247 #gpio-cells = <2>;
0248 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
0249 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
0250 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
0251 "GPIO_LIN_EN", "CAN_STB";
0252 };
0253 };
0254
0255 &ospi0 {
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
0258
0259 flash@0 {
0260 compatible = "jedec,spi-nor";
0261 reg = <0x0>;
0262 spi-tx-bus-width = <8>;
0263 spi-rx-bus-width = <8>;
0264 spi-max-frequency = <25000000>;
0265 cdns,tshsl-ns = <60>;
0266 cdns,tsd2d-ns = <60>;
0267 cdns,tchsh-ns = <60>;
0268 cdns,tslch-ns = <60>;
0269 cdns,read-delay = <4>;
0270 };
0271 };
