0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
0004 *
0005 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 &cbass_mcu_wakeup {
0009 dmsc: system-controller@44083000 {
0010 compatible = "ti,k2g-sci";
0011 ti,host-id = <12>;
0012
0013 mbox-names = "rx", "tx";
0014
0015 mboxes = <&secure_proxy_main 11>,
0016 <&secure_proxy_main 13>;
0017
0018 reg-names = "debug_messages";
0019 reg = <0x00 0x44083000 0x00 0x1000>;
0020
0021 k3_pds: power-controller {
0022 compatible = "ti,sci-pm-domain";
0023 #power-domain-cells = <2>;
0024 };
0025
0026 k3_clks: clock-controller {
0027 compatible = "ti,k2g-sci-clk";
0028 #clock-cells = <2>;
0029 };
0030
0031 k3_reset: reset-controller {
0032 compatible = "ti,sci-reset";
0033 #reset-cells = <2>;
0034 };
0035 };
0036
0037 mcu_conf: syscon@40f00000 {
0038 compatible = "syscon", "simple-mfd";
0039 reg = <0x00 0x40f00000 0x00 0x20000>;
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 ranges = <0x00 0x00 0x40f00000 0x20000>;
0043
0044 phy_gmii_sel: phy@4040 {
0045 compatible = "ti,am654-phy-gmii-sel";
0046 reg = <0x4040 0x4>;
0047 #phy-cells = <1>;
0048 };
0049 };
0050
0051 chipid@43000014 {
0052 compatible = "ti,am654-chipid";
0053 reg = <0x00 0x43000014 0x00 0x4>;
0054 };
0055
0056 wkup_pmx0: pinctrl@4301c000 {
0057 compatible = "pinctrl-single";
0058 /* Proxy 0 addressing */
0059 reg = <0x00 0x4301c000 0x00 0x178>;
0060 #pinctrl-cells = <1>;
0061 pinctrl-single,register-width = <32>;
0062 pinctrl-single,function-mask = <0xffffffff>;
0063 };
0064
0065 mcu_ram: sram@41c00000 {
0066 compatible = "mmio-sram";
0067 reg = <0x00 0x41c00000 0x00 0x100000>;
0068 ranges = <0x00 0x00 0x41c00000 0x100000>;
0069 #address-cells = <1>;
0070 #size-cells = <1>;
0071 };
0072
0073 wkup_uart0: serial@42300000 {
0074 compatible = "ti,j721e-uart", "ti,am654-uart";
0075 reg = <0x00 0x42300000 0x00 0x100>;
0076 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
0077 clock-frequency = <48000000>;
0078 current-speed = <115200>;
0079 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
0080 clocks = <&k3_clks 287 2>;
0081 clock-names = "fclk";
0082 };
0083
0084 mcu_uart0: serial@40a00000 {
0085 compatible = "ti,j721e-uart", "ti,am654-uart";
0086 reg = <0x00 0x40a00000 0x00 0x100>;
0087 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
0088 clock-frequency = <96000000>;
0089 current-speed = <115200>;
0090 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
0091 clocks = <&k3_clks 149 2>;
0092 clock-names = "fclk";
0093 };
0094
0095 wkup_gpio_intr: interrupt-controller@42200000 {
0096 compatible = "ti,sci-intr";
0097 reg = <0x00 0x42200000 0x00 0x400>;
0098 ti,intr-trigger-type = <1>;
0099 interrupt-controller;
0100 interrupt-parent = <&gic500>;
0101 #interrupt-cells = <1>;
0102 ti,sci = <&dmsc>;
0103 ti,sci-dev-id = <137>;
0104 ti,interrupt-ranges = <16 960 16>;
0105 };
0106
0107 wkup_gpio0: gpio@42110000 {
0108 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0109 reg = <0x00 0x42110000 0x00 0x100>;
0110 gpio-controller;
0111 #gpio-cells = <2>;
0112 interrupt-parent = <&wkup_gpio_intr>;
0113 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
0114 interrupt-controller;
0115 #interrupt-cells = <2>;
0116 ti,ngpio = <85>;
0117 ti,davinci-gpio-unbanked = <0>;
0118 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
0119 clocks = <&k3_clks 113 0>;
0120 clock-names = "gpio";
0121 };
0122
0123 wkup_gpio1: gpio@42100000 {
0124 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0125 reg = <0x00 0x42100000 0x00 0x100>;
0126 gpio-controller;
0127 #gpio-cells = <2>;
0128 interrupt-parent = <&wkup_gpio_intr>;
0129 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
0130 interrupt-controller;
0131 #interrupt-cells = <2>;
0132 ti,ngpio = <85>;
0133 ti,davinci-gpio-unbanked = <0>;
0134 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0135 clocks = <&k3_clks 114 0>;
0136 clock-names = "gpio";
0137 };
0138
0139 mcu_navss: bus@28380000 {
0140 compatible = "simple-mfd";
0141 #address-cells = <2>;
0142 #size-cells = <2>;
0143 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
0144 dma-coherent;
0145 dma-ranges;
0146 ti,sci-dev-id = <232>;
0147
0148 mcu_ringacc: ringacc@2b800000 {
0149 compatible = "ti,am654-navss-ringacc";
0150 reg = <0x00 0x2b800000 0x00 0x400000>,
0151 <0x00 0x2b000000 0x00 0x400000>,
0152 <0x00 0x28590000 0x00 0x100>,
0153 <0x00 0x2a500000 0x00 0x40000>;
0154 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0155 ti,num-rings = <286>;
0156 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0157 ti,sci = <&dmsc>;
0158 ti,sci-dev-id = <235>;
0159 msi-parent = <&main_udmass_inta>;
0160 };
0161
0162 mcu_udmap: dma-controller@285c0000 {
0163 compatible = "ti,j721e-navss-mcu-udmap";
0164 reg = <0x00 0x285c0000 0x00 0x100>,
0165 <0x00 0x2a800000 0x00 0x40000>,
0166 <0x00 0x2aa00000 0x00 0x40000>;
0167 reg-names = "gcfg", "rchanrt", "tchanrt";
0168 msi-parent = <&main_udmass_inta>;
0169 #dma-cells = <1>;
0170
0171 ti,sci = <&dmsc>;
0172 ti,sci-dev-id = <236>;
0173 ti,ringacc = <&mcu_ringacc>;
0174
0175 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0176 <0x0f>; /* TX_HCHAN */
0177 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0178 <0x0b>; /* RX_HCHAN */
0179 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0180 };
0181 };
0182
0183 mcu_cpsw: ethernet@46000000 {
0184 compatible = "ti,j721e-cpsw-nuss";
0185 #address-cells = <2>;
0186 #size-cells = <2>;
0187 reg = <0x00 0x46000000 0x00 0x200000>;
0188 reg-names = "cpsw_nuss";
0189 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
0190 dma-coherent;
0191 clocks = <&k3_clks 18 21>;
0192 clock-names = "fck";
0193 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
0194
0195 dmas = <&mcu_udmap 0xf000>,
0196 <&mcu_udmap 0xf001>,
0197 <&mcu_udmap 0xf002>,
0198 <&mcu_udmap 0xf003>,
0199 <&mcu_udmap 0xf004>,
0200 <&mcu_udmap 0xf005>,
0201 <&mcu_udmap 0xf006>,
0202 <&mcu_udmap 0xf007>,
0203 <&mcu_udmap 0x7000>;
0204 dma-names = "tx0", "tx1", "tx2", "tx3",
0205 "tx4", "tx5", "tx6", "tx7",
0206 "rx";
0207
0208 ethernet-ports {
0209 #address-cells = <1>;
0210 #size-cells = <0>;
0211
0212 cpsw_port1: port@1 {
0213 reg = <1>;
0214 ti,mac-only;
0215 label = "port1";
0216 ti,syscon-efuse = <&mcu_conf 0x200>;
0217 phys = <&phy_gmii_sel 1>;
0218 };
0219 };
0220
0221 davinci_mdio: mdio@f00 {
0222 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0223 reg = <0x00 0xf00 0x00 0x100>;
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226 clocks = <&k3_clks 18 21>;
0227 clock-names = "fck";
0228 bus_freq = <1000000>;
0229 };
0230
0231 cpts@3d000 {
0232 compatible = "ti,am65-cpts";
0233 reg = <0x00 0x3d000 0x00 0x400>;
0234 clocks = <&k3_clks 18 2>;
0235 clock-names = "cpts";
0236 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
0237 interrupt-names = "cpts";
0238 ti,cpts-ext-ts-inputs = <4>;
0239 ti,cpts-periodic-outputs = <2>;
0240 };
0241 };
0242
0243 mcu_i2c0: i2c@40b00000 {
0244 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0245 reg = <0x00 0x40b00000 0x00 0x100>;
0246 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249 clock-names = "fck";
0250 clocks = <&k3_clks 194 1>;
0251 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
0252 };
0253
0254 mcu_i2c1: i2c@40b10000 {
0255 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0256 reg = <0x00 0x40b10000 0x00 0x100>;
0257 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
0258 #address-cells = <1>;
0259 #size-cells = <0>;
0260 clock-names = "fck";
0261 clocks = <&k3_clks 195 1>;
0262 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
0263 };
0264
0265 wkup_i2c0: i2c@42120000 {
0266 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0267 reg = <0x00 0x42120000 0x00 0x100>;
0268 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 clock-names = "fck";
0272 clocks = <&k3_clks 197 1>;
0273 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
0274 };
0275
0276 fss: syscon@47000000 {
0277 compatible = "syscon", "simple-mfd";
0278 reg = <0x00 0x47000000 0x00 0x100>;
0279 #address-cells = <2>;
0280 #size-cells = <2>;
0281 ranges;
0282
0283 hbmc_mux: hbmc-mux {
0284 compatible = "mmio-mux";
0285 #mux-control-cells = <1>;
0286 mux-reg-masks = <0x4 0x2>; /* HBMC select */
0287 };
0288
0289 hbmc: hyperbus@47034000 {
0290 compatible = "ti,am654-hbmc";
0291 reg = <0x00 0x47034000 0x00 0x100>,
0292 <0x05 0x00000000 0x01 0x0000000>;
0293 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
0294 clocks = <&k3_clks 102 0>;
0295 assigned-clocks = <&k3_clks 102 5>;
0296 assigned-clock-rates = <333333333>;
0297 #address-cells = <2>;
0298 #size-cells = <1>;
0299 mux-controls = <&hbmc_mux 0>;
0300 };
0301
0302 ospi0: spi@47040000 {
0303 compatible = "ti,am654-ospi", "cdns,qspi-nor";
0304 reg = <0x0 0x47040000 0x0 0x100>,
0305 <0x5 0x00000000 0x1 0x0000000>;
0306 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
0307 cdns,fifo-depth = <256>;
0308 cdns,fifo-width = <4>;
0309 cdns,trigger-address = <0x0>;
0310 clocks = <&k3_clks 103 0>;
0311 assigned-clocks = <&k3_clks 103 0>;
0312 assigned-clock-parents = <&k3_clks 103 2>;
0313 assigned-clock-rates = <166666666>;
0314 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
0315 #address-cells = <1>;
0316 #size-cells = <0>;
0317 };
0318 };
0319
0320 tscadc0: tscadc@40200000 {
0321 compatible = "ti,am3359-tscadc";
0322 reg = <0x00 0x40200000 0x00 0x1000>;
0323 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
0324 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
0325 clocks = <&k3_clks 0 1>;
0326 assigned-clocks = <&k3_clks 0 3>;
0327 assigned-clock-rates = <60000000>;
0328 clock-names = "adc_tsc_fck";
0329 dmas = <&main_udmap 0x7400>,
0330 <&main_udmap 0x7401>;
0331 dma-names = "fifo0", "fifo1";
0332
0333 adc {
0334 #io-channel-cells = <1>;
0335 compatible = "ti,am3359-adc";
0336 };
0337 };
0338
0339 mcu_r5fss0: r5fss@41000000 {
0340 compatible = "ti,j7200-r5fss";
0341 ti,cluster-mode = <1>;
0342 #address-cells = <1>;
0343 #size-cells = <1>;
0344 ranges = <0x41000000 0x00 0x41000000 0x20000>,
0345 <0x41400000 0x00 0x41400000 0x20000>;
0346 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
0347
0348 mcu_r5fss0_core0: r5f@41000000 {
0349 compatible = "ti,j7200-r5f";
0350 reg = <0x41000000 0x00010000>,
0351 <0x41010000 0x00010000>;
0352 reg-names = "atcm", "btcm";
0353 ti,sci = <&dmsc>;
0354 ti,sci-dev-id = <250>;
0355 ti,sci-proc-ids = <0x01 0xff>;
0356 resets = <&k3_reset 250 1>;
0357 firmware-name = "j7200-mcu-r5f0_0-fw";
0358 ti,atcm-enable = <1>;
0359 ti,btcm-enable = <1>;
0360 ti,loczrama = <1>;
0361 };
0362
0363 mcu_r5fss0_core1: r5f@41400000 {
0364 compatible = "ti,j7200-r5f";
0365 reg = <0x41400000 0x00008000>,
0366 <0x41410000 0x00008000>;
0367 reg-names = "atcm", "btcm";
0368 ti,sci = <&dmsc>;
0369 ti,sci-dev-id = <251>;
0370 ti,sci-proc-ids = <0x02 0xff>;
0371 resets = <&k3_reset 251 1>;
0372 firmware-name = "j7200-mcu-r5f0_1-fw";
0373 ti,atcm-enable = <1>;
0374 ti,btcm-enable = <1>;
0375 ti,loczrama = <1>;
0376 };
0377 };
0378 };
