0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J7200 SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 / {
0009 serdes_refclk: serdes-refclk {
0010 #clock-cells = <0>;
0011 compatible = "fixed-clock";
0012 };
0013 };
0014
0015 &cbass_main {
0016 msmc_ram: sram@70000000 {
0017 compatible = "mmio-sram";
0018 reg = <0x00 0x70000000 0x00 0x100000>;
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021 ranges = <0x00 0x00 0x70000000 0x100000>;
0022
0023 atf-sram@0 {
0024 reg = <0x00 0x20000>;
0025 };
0026 };
0027
0028 scm_conf: scm-conf@100000 {
0029 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
0030 reg = <0x00 0x00100000 0x00 0x1c000>;
0031 #address-cells = <1>;
0032 #size-cells = <1>;
0033 ranges = <0x00 0x00 0x00100000 0x1c000>;
0034
0035 serdes_ln_ctrl: mux-controller@4080 {
0036 compatible = "mmio-mux";
0037 #mux-control-cells = <1>;
0038 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
0039 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
0040 };
0041
0042 usb_serdes_mux: mux-controller@4000 {
0043 compatible = "mmio-mux";
0044 #mux-control-cells = <1>;
0045 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
0046 };
0047 };
0048
0049 gic500: interrupt-controller@1800000 {
0050 compatible = "arm,gic-v3";
0051 #address-cells = <2>;
0052 #size-cells = <2>;
0053 ranges;
0054 #interrupt-cells = <3>;
0055 interrupt-controller;
0056 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
0057 <0x00 0x01900000 0x00 0x100000>, /* GICR */
0058 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
0059 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
0060 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
0061
0062 /* vcpumntirq: virtual CPU interface maintenance interrupt */
0063 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0064
0065 gic_its: msi-controller@1820000 {
0066 compatible = "arm,gic-v3-its";
0067 reg = <0x00 0x01820000 0x00 0x10000>;
0068 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0069 msi-controller;
0070 #msi-cells = <1>;
0071 };
0072 };
0073
0074 main_gpio_intr: interrupt-controller@a00000 {
0075 compatible = "ti,sci-intr";
0076 reg = <0x00 0x00a00000 0x00 0x800>;
0077 ti,intr-trigger-type = <1>;
0078 interrupt-controller;
0079 interrupt-parent = <&gic500>;
0080 #interrupt-cells = <1>;
0081 ti,sci = <&dmsc>;
0082 ti,sci-dev-id = <131>;
0083 ti,interrupt-ranges = <8 392 56>;
0084 };
0085
0086 main_navss: bus@30000000 {
0087 compatible = "simple-mfd";
0088 #address-cells = <2>;
0089 #size-cells = <2>;
0090 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
0091 ti,sci-dev-id = <199>;
0092 dma-coherent;
0093 dma-ranges;
0094
0095 main_navss_intr: interrupt-controller@310e0000 {
0096 compatible = "ti,sci-intr";
0097 reg = <0x00 0x310e0000 0x00 0x4000>;
0098 ti,intr-trigger-type = <4>;
0099 interrupt-controller;
0100 interrupt-parent = <&gic500>;
0101 #interrupt-cells = <1>;
0102 ti,sci = <&dmsc>;
0103 ti,sci-dev-id = <213>;
0104 ti,interrupt-ranges = <0 64 64>,
0105 <64 448 64>,
0106 <128 672 64>;
0107 };
0108
0109 main_udmass_inta: msi-controller@33d00000 {
0110 compatible = "ti,sci-inta";
0111 reg = <0x00 0x33d00000 0x00 0x100000>;
0112 interrupt-controller;
0113 #interrupt-cells = <0>;
0114 interrupt-parent = <&main_navss_intr>;
0115 msi-controller;
0116 ti,sci = <&dmsc>;
0117 ti,sci-dev-id = <209>;
0118 ti,interrupt-ranges = <0 0 256>;
0119 };
0120
0121 secure_proxy_main: mailbox@32c00000 {
0122 compatible = "ti,am654-secure-proxy";
0123 #mbox-cells = <1>;
0124 reg-names = "target_data", "rt", "scfg";
0125 reg = <0x00 0x32c00000 0x00 0x100000>,
0126 <0x00 0x32400000 0x00 0x100000>,
0127 <0x00 0x32800000 0x00 0x100000>;
0128 interrupt-names = "rx_011";
0129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0130 };
0131
0132 hwspinlock: spinlock@30e00000 {
0133 compatible = "ti,am654-hwspinlock";
0134 reg = <0x00 0x30e00000 0x00 0x1000>;
0135 #hwlock-cells = <1>;
0136 };
0137
0138 mailbox0_cluster0: mailbox@31f80000 {
0139 compatible = "ti,am654-mailbox";
0140 reg = <0x00 0x31f80000 0x00 0x200>;
0141 #mbox-cells = <1>;
0142 ti,mbox-num-users = <4>;
0143 ti,mbox-num-fifos = <16>;
0144 interrupt-parent = <&main_navss_intr>;
0145 };
0146
0147 mailbox0_cluster1: mailbox@31f81000 {
0148 compatible = "ti,am654-mailbox";
0149 reg = <0x00 0x31f81000 0x00 0x200>;
0150 #mbox-cells = <1>;
0151 ti,mbox-num-users = <4>;
0152 ti,mbox-num-fifos = <16>;
0153 interrupt-parent = <&main_navss_intr>;
0154 };
0155
0156 mailbox0_cluster2: mailbox@31f82000 {
0157 compatible = "ti,am654-mailbox";
0158 reg = <0x00 0x31f82000 0x00 0x200>;
0159 #mbox-cells = <1>;
0160 ti,mbox-num-users = <4>;
0161 ti,mbox-num-fifos = <16>;
0162 interrupt-parent = <&main_navss_intr>;
0163 };
0164
0165 mailbox0_cluster3: mailbox@31f83000 {
0166 compatible = "ti,am654-mailbox";
0167 reg = <0x00 0x31f83000 0x00 0x200>;
0168 #mbox-cells = <1>;
0169 ti,mbox-num-users = <4>;
0170 ti,mbox-num-fifos = <16>;
0171 interrupt-parent = <&main_navss_intr>;
0172 };
0173
0174 mailbox0_cluster4: mailbox@31f84000 {
0175 compatible = "ti,am654-mailbox";
0176 reg = <0x00 0x31f84000 0x00 0x200>;
0177 #mbox-cells = <1>;
0178 ti,mbox-num-users = <4>;
0179 ti,mbox-num-fifos = <16>;
0180 interrupt-parent = <&main_navss_intr>;
0181 };
0182
0183 mailbox0_cluster5: mailbox@31f85000 {
0184 compatible = "ti,am654-mailbox";
0185 reg = <0x00 0x31f85000 0x00 0x200>;
0186 #mbox-cells = <1>;
0187 ti,mbox-num-users = <4>;
0188 ti,mbox-num-fifos = <16>;
0189 interrupt-parent = <&main_navss_intr>;
0190 };
0191
0192 mailbox0_cluster6: mailbox@31f86000 {
0193 compatible = "ti,am654-mailbox";
0194 reg = <0x00 0x31f86000 0x00 0x200>;
0195 #mbox-cells = <1>;
0196 ti,mbox-num-users = <4>;
0197 ti,mbox-num-fifos = <16>;
0198 interrupt-parent = <&main_navss_intr>;
0199 };
0200
0201 mailbox0_cluster7: mailbox@31f87000 {
0202 compatible = "ti,am654-mailbox";
0203 reg = <0x00 0x31f87000 0x00 0x200>;
0204 #mbox-cells = <1>;
0205 ti,mbox-num-users = <4>;
0206 ti,mbox-num-fifos = <16>;
0207 interrupt-parent = <&main_navss_intr>;
0208 };
0209
0210 mailbox0_cluster8: mailbox@31f88000 {
0211 compatible = "ti,am654-mailbox";
0212 reg = <0x00 0x31f88000 0x00 0x200>;
0213 #mbox-cells = <1>;
0214 ti,mbox-num-users = <4>;
0215 ti,mbox-num-fifos = <16>;
0216 interrupt-parent = <&main_navss_intr>;
0217 };
0218
0219 mailbox0_cluster9: mailbox@31f89000 {
0220 compatible = "ti,am654-mailbox";
0221 reg = <0x00 0x31f89000 0x00 0x200>;
0222 #mbox-cells = <1>;
0223 ti,mbox-num-users = <4>;
0224 ti,mbox-num-fifos = <16>;
0225 interrupt-parent = <&main_navss_intr>;
0226 };
0227
0228 mailbox0_cluster10: mailbox@31f8a000 {
0229 compatible = "ti,am654-mailbox";
0230 reg = <0x00 0x31f8a000 0x00 0x200>;
0231 #mbox-cells = <1>;
0232 ti,mbox-num-users = <4>;
0233 ti,mbox-num-fifos = <16>;
0234 interrupt-parent = <&main_navss_intr>;
0235 };
0236
0237 mailbox0_cluster11: mailbox@31f8b000 {
0238 compatible = "ti,am654-mailbox";
0239 reg = <0x00 0x31f8b000 0x00 0x200>;
0240 #mbox-cells = <1>;
0241 ti,mbox-num-users = <4>;
0242 ti,mbox-num-fifos = <16>;
0243 interrupt-parent = <&main_navss_intr>;
0244 };
0245
0246 main_ringacc: ringacc@3c000000 {
0247 compatible = "ti,am654-navss-ringacc";
0248 reg = <0x00 0x3c000000 0x00 0x400000>,
0249 <0x00 0x38000000 0x00 0x400000>,
0250 <0x00 0x31120000 0x00 0x100>,
0251 <0x00 0x33000000 0x00 0x40000>;
0252 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0253 ti,num-rings = <1024>;
0254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0255 ti,sci = <&dmsc>;
0256 ti,sci-dev-id = <211>;
0257 msi-parent = <&main_udmass_inta>;
0258 };
0259
0260 main_udmap: dma-controller@31150000 {
0261 compatible = "ti,j721e-navss-main-udmap";
0262 reg = <0x00 0x31150000 0x00 0x100>,
0263 <0x00 0x34000000 0x00 0x100000>,
0264 <0x00 0x35000000 0x00 0x100000>;
0265 reg-names = "gcfg", "rchanrt", "tchanrt";
0266 msi-parent = <&main_udmass_inta>;
0267 #dma-cells = <1>;
0268
0269 ti,sci = <&dmsc>;
0270 ti,sci-dev-id = <212>;
0271 ti,ringacc = <&main_ringacc>;
0272
0273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0274 <0x0f>, /* TX_HCHAN */
0275 <0x10>; /* TX_UHCHAN */
0276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0277 <0x0b>, /* RX_HCHAN */
0278 <0x0c>; /* RX_UHCHAN */
0279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0280 };
0281
0282 cpts@310d0000 {
0283 compatible = "ti,j721e-cpts";
0284 reg = <0x00 0x310d0000 0x00 0x400>;
0285 reg-names = "cpts";
0286 clocks = <&k3_clks 201 1>;
0287 clock-names = "cpts";
0288 interrupts-extended = <&main_navss_intr 391>;
0289 interrupt-names = "cpts";
0290 ti,cpts-periodic-outputs = <6>;
0291 ti,cpts-ext-ts-inputs = <8>;
0292 };
0293 };
0294
0295 main_pmx0: pinctrl@11c000 {
0296 compatible = "pinctrl-single";
0297 /* Proxy 0 addressing */
0298 reg = <0x00 0x11c000 0x00 0x2b4>;
0299 #pinctrl-cells = <1>;
0300 pinctrl-single,register-width = <32>;
0301 pinctrl-single,function-mask = <0xffffffff>;
0302 };
0303
0304 main_uart0: serial@2800000 {
0305 compatible = "ti,j721e-uart", "ti,am654-uart";
0306 reg = <0x00 0x02800000 0x00 0x100>;
0307 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0308 clock-frequency = <48000000>;
0309 current-speed = <115200>;
0310 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0311 clocks = <&k3_clks 146 2>;
0312 clock-names = "fclk";
0313 };
0314
0315 main_uart1: serial@2810000 {
0316 compatible = "ti,j721e-uart", "ti,am654-uart";
0317 reg = <0x00 0x02810000 0x00 0x100>;
0318 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0319 clock-frequency = <48000000>;
0320 current-speed = <115200>;
0321 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
0322 clocks = <&k3_clks 278 2>;
0323 clock-names = "fclk";
0324 };
0325
0326 main_uart2: serial@2820000 {
0327 compatible = "ti,j721e-uart", "ti,am654-uart";
0328 reg = <0x00 0x02820000 0x00 0x100>;
0329 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0330 clock-frequency = <48000000>;
0331 current-speed = <115200>;
0332 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
0333 clocks = <&k3_clks 279 2>;
0334 clock-names = "fclk";
0335 };
0336
0337 main_uart3: serial@2830000 {
0338 compatible = "ti,j721e-uart", "ti,am654-uart";
0339 reg = <0x00 0x02830000 0x00 0x100>;
0340 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0341 clock-frequency = <48000000>;
0342 current-speed = <115200>;
0343 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
0344 clocks = <&k3_clks 280 2>;
0345 clock-names = "fclk";
0346 };
0347
0348 main_uart4: serial@2840000 {
0349 compatible = "ti,j721e-uart", "ti,am654-uart";
0350 reg = <0x00 0x02840000 0x00 0x100>;
0351 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0352 clock-frequency = <48000000>;
0353 current-speed = <115200>;
0354 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
0355 clocks = <&k3_clks 281 2>;
0356 clock-names = "fclk";
0357 };
0358
0359 main_uart5: serial@2850000 {
0360 compatible = "ti,j721e-uart", "ti,am654-uart";
0361 reg = <0x00 0x02850000 0x00 0x100>;
0362 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0363 clock-frequency = <48000000>;
0364 current-speed = <115200>;
0365 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
0366 clocks = <&k3_clks 282 2>;
0367 clock-names = "fclk";
0368 };
0369
0370 main_uart6: serial@2860000 {
0371 compatible = "ti,j721e-uart", "ti,am654-uart";
0372 reg = <0x00 0x02860000 0x00 0x100>;
0373 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
0374 clock-frequency = <48000000>;
0375 current-speed = <115200>;
0376 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
0377 clocks = <&k3_clks 283 2>;
0378 clock-names = "fclk";
0379 };
0380
0381 main_uart7: serial@2870000 {
0382 compatible = "ti,j721e-uart", "ti,am654-uart";
0383 reg = <0x00 0x02870000 0x00 0x100>;
0384 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
0385 clock-frequency = <48000000>;
0386 current-speed = <115200>;
0387 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
0388 clocks = <&k3_clks 284 2>;
0389 clock-names = "fclk";
0390 };
0391
0392 main_uart8: serial@2880000 {
0393 compatible = "ti,j721e-uart", "ti,am654-uart";
0394 reg = <0x00 0x02880000 0x00 0x100>;
0395 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
0396 clock-frequency = <48000000>;
0397 current-speed = <115200>;
0398 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
0399 clocks = <&k3_clks 285 2>;
0400 clock-names = "fclk";
0401 };
0402
0403 main_uart9: serial@2890000 {
0404 compatible = "ti,j721e-uart", "ti,am654-uart";
0405 reg = <0x00 0x02890000 0x00 0x100>;
0406 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0407 clock-frequency = <48000000>;
0408 current-speed = <115200>;
0409 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
0410 clocks = <&k3_clks 286 2>;
0411 clock-names = "fclk";
0412 };
0413
0414 main_i2c0: i2c@2000000 {
0415 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0416 reg = <0x00 0x2000000 0x00 0x100>;
0417 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420 clock-names = "fck";
0421 clocks = <&k3_clks 187 1>;
0422 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
0423 };
0424
0425 main_i2c1: i2c@2010000 {
0426 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0427 reg = <0x00 0x2010000 0x00 0x100>;
0428 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0429 #address-cells = <1>;
0430 #size-cells = <0>;
0431 clock-names = "fck";
0432 clocks = <&k3_clks 188 1>;
0433 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
0434 };
0435
0436 main_i2c2: i2c@2020000 {
0437 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0438 reg = <0x00 0x2020000 0x00 0x100>;
0439 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0440 #address-cells = <1>;
0441 #size-cells = <0>;
0442 clock-names = "fck";
0443 clocks = <&k3_clks 189 1>;
0444 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
0445 };
0446
0447 main_i2c3: i2c@2030000 {
0448 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0449 reg = <0x00 0x2030000 0x00 0x100>;
0450 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0451 #address-cells = <1>;
0452 #size-cells = <0>;
0453 clock-names = "fck";
0454 clocks = <&k3_clks 190 1>;
0455 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
0456 };
0457
0458 main_i2c4: i2c@2040000 {
0459 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0460 reg = <0x00 0x2040000 0x00 0x100>;
0461 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
0462 #address-cells = <1>;
0463 #size-cells = <0>;
0464 clock-names = "fck";
0465 clocks = <&k3_clks 191 1>;
0466 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
0467 };
0468
0469 main_i2c5: i2c@2050000 {
0470 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0471 reg = <0x00 0x2050000 0x00 0x100>;
0472 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
0473 #address-cells = <1>;
0474 #size-cells = <0>;
0475 clock-names = "fck";
0476 clocks = <&k3_clks 192 1>;
0477 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
0478 };
0479
0480 main_i2c6: i2c@2060000 {
0481 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0482 reg = <0x00 0x2060000 0x00 0x100>;
0483 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
0484 #address-cells = <1>;
0485 #size-cells = <0>;
0486 clock-names = "fck";
0487 clocks = <&k3_clks 193 1>;
0488 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
0489 };
0490
0491 main_sdhci0: mmc@4f80000 {
0492 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
0493 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
0494 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0495 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
0496 clock-names = "clk_ahb", "clk_xin";
0497 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
0498 ti,otap-del-sel-legacy = <0x0>;
0499 ti,otap-del-sel-mmc-hs = <0x0>;
0500 ti,otap-del-sel-ddr52 = <0x6>;
0501 ti,otap-del-sel-hs200 = <0x8>;
0502 ti,otap-del-sel-hs400 = <0x5>;
0503 ti,itap-del-sel-legacy = <0x10>;
0504 ti,itap-del-sel-mmc-hs = <0xa>;
0505 ti,strobe-sel = <0x77>;
0506 ti,clkbuf-sel = <0x7>;
0507 ti,trm-icp = <0x8>;
0508 bus-width = <8>;
0509 mmc-ddr-1_8v;
0510 mmc-hs200-1_8v;
0511 mmc-hs400-1_8v;
0512 dma-coherent;
0513 };
0514
0515 main_sdhci1: mmc@4fb0000 {
0516 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
0517 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
0518 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0519 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
0520 clock-names = "clk_ahb", "clk_xin";
0521 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
0522 ti,otap-del-sel-legacy = <0x0>;
0523 ti,otap-del-sel-sd-hs = <0x0>;
0524 ti,otap-del-sel-sdr12 = <0xf>;
0525 ti,otap-del-sel-sdr25 = <0xf>;
0526 ti,otap-del-sel-sdr50 = <0xc>;
0527 ti,otap-del-sel-sdr104 = <0x5>;
0528 ti,otap-del-sel-ddr50 = <0xc>;
0529 ti,itap-del-sel-legacy = <0x0>;
0530 ti,itap-del-sel-sd-hs = <0x0>;
0531 ti,itap-del-sel-sdr12 = <0x0>;
0532 ti,itap-del-sel-sdr25 = <0x0>;
0533 ti,clkbuf-sel = <0x7>;
0534 ti,trm-icp = <0x8>;
0535 dma-coherent;
0536 };
0537
0538 serdes_wiz0: wiz@5060000 {
0539 compatible = "ti,j721e-wiz-10g";
0540 #address-cells = <1>;
0541 #size-cells = <1>;
0542 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
0543 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
0544 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0545 num-lanes = <4>;
0546 #reset-cells = <1>;
0547 ranges = <0x5060000 0x0 0x5060000 0x10000>;
0548
0549 assigned-clocks = <&k3_clks 292 85>;
0550 assigned-clock-parents = <&k3_clks 292 89>;
0551
0552 wiz0_pll0_refclk: pll0-refclk {
0553 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
0554 clock-output-names = "wiz0_pll0_refclk";
0555 #clock-cells = <0>;
0556 assigned-clocks = <&wiz0_pll0_refclk>;
0557 assigned-clock-parents = <&k3_clks 292 85>;
0558 };
0559
0560 wiz0_pll1_refclk: pll1-refclk {
0561 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
0562 clock-output-names = "wiz0_pll1_refclk";
0563 #clock-cells = <0>;
0564 assigned-clocks = <&wiz0_pll1_refclk>;
0565 assigned-clock-parents = <&k3_clks 292 85>;
0566 };
0567
0568 wiz0_refclk_dig: refclk-dig {
0569 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
0570 clock-output-names = "wiz0_refclk_dig";
0571 #clock-cells = <0>;
0572 assigned-clocks = <&wiz0_refclk_dig>;
0573 assigned-clock-parents = <&k3_clks 292 85>;
0574 };
0575
0576 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
0577 clocks = <&wiz0_refclk_dig>;
0578 #clock-cells = <0>;
0579 };
0580
0581 serdes0: serdes@5060000 {
0582 compatible = "ti,j721e-serdes-10g";
0583 reg = <0x05060000 0x00010000>;
0584 reg-names = "torrent_phy";
0585 resets = <&serdes_wiz0 0>;
0586 reset-names = "torrent_reset";
0587 clocks = <&wiz0_pll0_refclk>;
0588 clock-names = "refclk";
0589 #address-cells = <1>;
0590 #size-cells = <0>;
0591 };
0592 };
0593
0594 pcie1_rc: pcie@2910000 {
0595 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
0596 reg = <0x00 0x02910000 0x00 0x1000>,
0597 <0x00 0x02917000 0x00 0x400>,
0598 <0x00 0x0d800000 0x00 0x00800000>,
0599 <0x00 0x18000000 0x00 0x00001000>;
0600 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0601 interrupt-names = "link_state";
0602 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
0603 device_type = "pci";
0604 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
0605 max-link-speed = <3>;
0606 num-lanes = <4>;
0607 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
0608 clocks = <&k3_clks 240 6>;
0609 clock-names = "fck";
0610 #address-cells = <3>;
0611 #size-cells = <2>;
0612 bus-range = <0x0 0xff>;
0613 cdns,no-bar-match-nbits = <64>;
0614 vendor-id = <0x104c>;
0615 device-id = <0xb00f>;
0616 msi-map = <0x0 &gic_its 0x0 0x10000>;
0617 dma-coherent;
0618 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
0619 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
0620 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0621 };
0622
0623 pcie1_ep: pcie-ep@2910000 {
0624 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
0625 reg = <0x00 0x02910000 0x00 0x1000>,
0626 <0x00 0x02917000 0x00 0x400>,
0627 <0x00 0x0d800000 0x00 0x00800000>,
0628 <0x00 0x18000000 0x00 0x08000000>;
0629 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0630 interrupt-names = "link_state";
0631 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
0632 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
0633 max-link-speed = <3>;
0634 num-lanes = <4>;
0635 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
0636 clocks = <&k3_clks 240 6>;
0637 clock-names = "fck";
0638 max-functions = /bits/ 8 <6>;
0639 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
0640 dma-coherent;
0641 };
0642
0643 usbss0: cdns-usb@4104000 {
0644 compatible = "ti,j721e-usb";
0645 reg = <0x00 0x4104000 0x00 0x100>;
0646 dma-coherent;
0647 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
0648 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
0649 clock-names = "ref", "lpm";
0650 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
0651 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
0652 #address-cells = <2>;
0653 #size-cells = <2>;
0654 ranges;
0655
0656 usb0: usb@6000000 {
0657 compatible = "cdns,usb3";
0658 reg = <0x00 0x6000000 0x00 0x10000>,
0659 <0x00 0x6010000 0x00 0x10000>,
0660 <0x00 0x6020000 0x00 0x10000>;
0661 reg-names = "otg", "xhci", "dev";
0662 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
0663 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
0664 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
0665 interrupt-names = "host",
0666 "peripheral",
0667 "otg";
0668 maximum-speed = "super-speed";
0669 dr_mode = "otg";
0670 cdns,phyrst-a-enable;
0671 };
0672 };
0673
0674 main_gpio0: gpio@600000 {
0675 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0676 reg = <0x00 0x00600000 0x00 0x100>;
0677 gpio-controller;
0678 #gpio-cells = <2>;
0679 interrupt-parent = <&main_gpio_intr>;
0680 interrupts = <145>, <146>, <147>, <148>,
0681 <149>;
0682 interrupt-controller;
0683 #interrupt-cells = <2>;
0684 ti,ngpio = <69>;
0685 ti,davinci-gpio-unbanked = <0>;
0686 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
0687 clocks = <&k3_clks 105 0>;
0688 clock-names = "gpio";
0689 };
0690
0691 main_gpio2: gpio@610000 {
0692 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0693 reg = <0x00 0x00610000 0x00 0x100>;
0694 gpio-controller;
0695 #gpio-cells = <2>;
0696 interrupt-parent = <&main_gpio_intr>;
0697 interrupts = <154>, <155>, <156>, <157>,
0698 <158>;
0699 interrupt-controller;
0700 #interrupt-cells = <2>;
0701 ti,ngpio = <69>;
0702 ti,davinci-gpio-unbanked = <0>;
0703 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
0704 clocks = <&k3_clks 107 0>;
0705 clock-names = "gpio";
0706 };
0707
0708 main_gpio4: gpio@620000 {
0709 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0710 reg = <0x00 0x00620000 0x00 0x100>;
0711 gpio-controller;
0712 #gpio-cells = <2>;
0713 interrupt-parent = <&main_gpio_intr>;
0714 interrupts = <163>, <164>, <165>, <166>,
0715 <167>;
0716 interrupt-controller;
0717 #interrupt-cells = <2>;
0718 ti,ngpio = <69>;
0719 ti,davinci-gpio-unbanked = <0>;
0720 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
0721 clocks = <&k3_clks 109 0>;
0722 clock-names = "gpio";
0723 };
0724
0725 main_gpio6: gpio@630000 {
0726 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0727 reg = <0x00 0x00630000 0x00 0x100>;
0728 gpio-controller;
0729 #gpio-cells = <2>;
0730 interrupt-parent = <&main_gpio_intr>;
0731 interrupts = <172>, <173>, <174>, <175>,
0732 <176>;
0733 interrupt-controller;
0734 #interrupt-cells = <2>;
0735 ti,ngpio = <69>;
0736 ti,davinci-gpio-unbanked = <0>;
0737 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
0738 clocks = <&k3_clks 111 0>;
0739 clock-names = "gpio";
0740 };
0741
0742 main_r5fss0: r5fss@5c00000 {
0743 compatible = "ti,j7200-r5fss";
0744 ti,cluster-mode = <1>;
0745 #address-cells = <1>;
0746 #size-cells = <1>;
0747 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
0748 <0x5d00000 0x00 0x5d00000 0x20000>;
0749 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
0750
0751 main_r5fss0_core0: r5f@5c00000 {
0752 compatible = "ti,j7200-r5f";
0753 reg = <0x5c00000 0x00010000>,
0754 <0x5c10000 0x00010000>;
0755 reg-names = "atcm", "btcm";
0756 ti,sci = <&dmsc>;
0757 ti,sci-dev-id = <245>;
0758 ti,sci-proc-ids = <0x06 0xff>;
0759 resets = <&k3_reset 245 1>;
0760 firmware-name = "j7200-main-r5f0_0-fw";
0761 ti,atcm-enable = <1>;
0762 ti,btcm-enable = <1>;
0763 ti,loczrama = <1>;
0764 };
0765
0766 main_r5fss0_core1: r5f@5d00000 {
0767 compatible = "ti,j7200-r5f";
0768 reg = <0x5d00000 0x00008000>,
0769 <0x5d10000 0x00008000>;
0770 reg-names = "atcm", "btcm";
0771 ti,sci = <&dmsc>;
0772 ti,sci-dev-id = <246>;
0773 ti,sci-proc-ids = <0x07 0xff>;
0774 resets = <&k3_reset 246 1>;
0775 firmware-name = "j7200-main-r5f0_1-fw";
0776 ti,atcm-enable = <1>;
0777 ti,btcm-enable = <1>;
0778 ti,loczrama = <1>;
0779 };
0780 };
0781 };
