0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM6 SoC Family
0004 *
0005 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/k3.h>
0012 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0013
0014 / {
0015 model = "Texas Instruments K3 AM654 SoC";
0016 compatible = "ti,am654";
0017 interrupt-parent = <&gic500>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 serial0 = &wkup_uart0;
0023 serial1 = &mcu_uart0;
0024 serial2 = &main_uart0;
0025 serial3 = &main_uart1;
0026 serial4 = &main_uart2;
0027 i2c0 = &wkup_i2c0;
0028 i2c1 = &mcu_i2c0;
0029 i2c2 = &main_i2c0;
0030 i2c3 = &main_i2c1;
0031 i2c4 = &main_i2c2;
0032 i2c5 = &main_i2c3;
0033 ethernet0 = &cpsw_port1;
0034 mmc0 = &sdhci0;
0035 mmc1 = &sdhci1;
0036 };
0037
0038 chosen { };
0039
0040 firmware {
0041 optee {
0042 compatible = "linaro,optee-tz";
0043 method = "smc";
0044 };
0045
0046 psci: psci {
0047 compatible = "arm,psci-1.0";
0048 method = "smc";
0049 };
0050 };
0051
0052 a53_timer0: timer-cl0-cpu0 {
0053 compatible = "arm,armv8-timer";
0054 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
0055 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
0056 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
0057 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
0058 };
0059
0060 pmu: pmu {
0061 compatible = "arm,cortex-a53-pmu";
0062 /* Recommendation from GIC500 TRM Table A.3 */
0063 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0064 };
0065
0066 cbass_main: bus@100000 {
0067 compatible = "simple-bus";
0068 #address-cells = <2>;
0069 #size-cells = <2>;
0070 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
0071 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
0072 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
0073 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
0074 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
0075 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
0076 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
0077 /* MCUSS Range */
0078 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
0079 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
0080 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
0081 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
0082 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
0083 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
0084 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
0085 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
0086 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
0087 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
0088 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
0089 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
0090 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
0091 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
0092 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
0093
0094 cbass_mcu: bus@28380000 {
0095 compatible = "simple-bus";
0096 #address-cells = <2>;
0097 #size-cells = <2>;
0098 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
0099 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
0100 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
0101 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
0102 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
0103 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
0104 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
0105 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
0106 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
0107 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
0108 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
0109 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
0110 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
0111
0112 cbass_wakeup: bus@42040000 {
0113 compatible = "simple-bus";
0114 #address-cells = <1>;
0115 #size-cells = <1>;
0116 /* WKUP Basic peripherals */
0117 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
0118 };
0119 };
0120 };
0121 };
0122
0123 /* Now include the peripherals for each bus segments */
0124 #include "k3-am65-main.dtsi"
0125 #include "k3-am65-mcu.dtsi"
0126 #include "k3-am65-wakeup.dtsi"
