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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
0004  *
0005  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007 
0008 &cbass_mcu {
0009         mcu_conf: scm-conf@40f00000 {
0010                 compatible = "syscon", "simple-mfd";
0011                 reg = <0x0 0x40f00000 0x0 0x20000>;
0012                 #address-cells = <1>;
0013                 #size-cells = <1>;
0014                 ranges = <0x0 0x0 0x40f00000 0x20000>;
0015 
0016                 phy_gmii_sel: phy@4040 {
0017                         compatible = "ti,am654-phy-gmii-sel";
0018                         reg = <0x4040 0x4>;
0019                         #phy-cells = <1>;
0020                 };
0021         };
0022 
0023         mcu_uart0: serial@40a00000 {
0024                 compatible = "ti,am654-uart";
0025                         reg = <0x00 0x40a00000 0x00 0x100>;
0026                         interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
0027                         clock-frequency = <96000000>;
0028                         current-speed = <115200>;
0029                         power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
0030         };
0031 
0032         mcu_ram: sram@41c00000 {
0033                 compatible = "mmio-sram";
0034                 reg = <0x00 0x41c00000 0x00 0x80000>;
0035                 ranges = <0x0 0x00 0x41c00000 0x80000>;
0036                 #address-cells = <1>;
0037                 #size-cells = <1>;
0038         };
0039 
0040         mcu_i2c0: i2c@40b00000 {
0041                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
0042                 reg = <0x0 0x40b00000 0x0 0x100>;
0043                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
0044                 #address-cells = <1>;
0045                 #size-cells = <0>;
0046                 clock-names = "fck";
0047                 clocks = <&k3_clks 114 1>;
0048                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0049         };
0050 
0051         mcu_spi0: spi@40300000 {
0052                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0053                 reg = <0x0 0x40300000 0x0 0x400>;
0054                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
0055                 clocks = <&k3_clks 142 1>;
0056                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
0057                 #address-cells = <1>;
0058                 #size-cells = <0>;
0059         };
0060 
0061         mcu_spi1: spi@40310000 {
0062                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0063                 reg = <0x0 0x40310000 0x0 0x400>;
0064                 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
0065                 clocks = <&k3_clks 143 1>;
0066                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
0067                 #address-cells = <1>;
0068                 #size-cells = <0>;
0069         };
0070 
0071         mcu_spi2: spi@40320000 {
0072                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0073                 reg = <0x0 0x40320000 0x0 0x400>;
0074                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
0075                 clocks = <&k3_clks 144 1>;
0076                 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
0077                 #address-cells = <1>;
0078                 #size-cells = <0>;
0079         };
0080 
0081         tscadc0: tscadc@40200000 {
0082                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
0083                 reg = <0x0 0x40200000 0x0 0x1000>;
0084                 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
0085                 clocks = <&k3_clks 0 2>;
0086                 assigned-clocks = <&k3_clks 0 2>;
0087                 assigned-clock-rates = <60000000>;
0088                 clock-names = "adc_tsc_fck";
0089                 dmas = <&mcu_udmap 0x7100>,
0090                         <&mcu_udmap 0x7101 >;
0091                 dma-names = "fifo0", "fifo1";
0092 
0093                 adc {
0094                         #io-channel-cells = <1>;
0095                         compatible = "ti,am654-adc", "ti,am3359-adc";
0096                 };
0097         };
0098 
0099         tscadc1: tscadc@40210000 {
0100                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
0101                 reg = <0x0 0x40210000 0x0 0x1000>;
0102                 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
0103                 clocks = <&k3_clks 1 2>;
0104                 assigned-clocks = <&k3_clks 1 2>;
0105                 assigned-clock-rates = <60000000>;
0106                 clock-names = "adc_tsc_fck";
0107                 dmas = <&mcu_udmap 0x7102>,
0108                         <&mcu_udmap 0x7103>;
0109                 dma-names = "fifo0", "fifo1";
0110 
0111                 adc {
0112                         #io-channel-cells = <1>;
0113                         compatible = "ti,am654-adc", "ti,am3359-adc";
0114                 };
0115         };
0116 
0117         mcu_navss: bus@28380000 {
0118                 compatible = "simple-mfd";
0119                 #address-cells = <2>;
0120                 #size-cells = <2>;
0121                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
0122                 dma-coherent;
0123                 dma-ranges;
0124 
0125                 ti,sci-dev-id = <119>;
0126 
0127                 mcu_ringacc: ringacc@2b800000 {
0128                         compatible = "ti,am654-navss-ringacc";
0129                         reg =   <0x0 0x2b800000 0x0 0x400000>,
0130                                 <0x0 0x2b000000 0x0 0x400000>,
0131                                 <0x0 0x28590000 0x0 0x100>,
0132                                 <0x0 0x2a500000 0x0 0x40000>;
0133                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0134                         ti,num-rings = <286>;
0135                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0136                         ti,sci = <&dmsc>;
0137                         ti,sci-dev-id = <195>;
0138                         msi-parent = <&inta_main_udmass>;
0139                 };
0140 
0141                 mcu_udmap: dma-controller@285c0000 {
0142                         compatible = "ti,am654-navss-mcu-udmap";
0143                         reg =   <0x0 0x285c0000 0x0 0x100>,
0144                                 <0x0 0x2a800000 0x0 0x40000>,
0145                                 <0x0 0x2aa00000 0x0 0x40000>;
0146                         reg-names = "gcfg", "rchanrt", "tchanrt";
0147                         msi-parent = <&inta_main_udmass>;
0148                         #dma-cells = <1>;
0149 
0150                         ti,sci = <&dmsc>;
0151                         ti,sci-dev-id = <194>;
0152                         ti,ringacc = <&mcu_ringacc>;
0153 
0154                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
0155                                                 <0xd>; /* TX_CHAN */
0156                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
0157                                                 <0xa>; /* RX_CHAN */
0158                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
0159                 };
0160         };
0161 
0162         m_can0: mcan@40528000 {
0163                 compatible = "bosch,m_can";
0164                 reg = <0x0 0x40528000 0x0 0x400>,
0165                       <0x0 0x40500000 0x0 0x4400>;
0166                 reg-names = "m_can", "message_ram";
0167                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
0168                 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
0169                 clock-names = "hclk", "cclk";
0170                 interrupt-parent = <&gic500>;
0171                 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
0172                              <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
0173                 interrupt-names = "int0", "int1";
0174                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0175         };
0176 
0177         m_can1: mcan@40568000 {
0178                 compatible = "bosch,m_can";
0179                 reg = <0x0 0x40568000 0x0 0x400>,
0180                       <0x0 0x40540000 0x0 0x4400>;
0181                 reg-names = "m_can", "message_ram";
0182                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
0183                 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
0184                 clock-names = "hclk", "cclk";
0185                 interrupt-parent = <&gic500>;
0186                 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
0187                              <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
0188                 interrupt-names = "int0", "int1";
0189                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0190         };
0191 
0192         fss: fss@47000000 {
0193                 compatible = "simple-bus";
0194                 #address-cells = <2>;
0195                 #size-cells = <2>;
0196                 ranges;
0197 
0198                 ospi0: spi@47040000 {
0199                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
0200                         reg = <0x0 0x47040000 0x0 0x100>,
0201                                 <0x5 0x00000000 0x1 0x0000000>;
0202                         interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
0203                         cdns,fifo-depth = <256>;
0204                         cdns,fifo-width = <4>;
0205                         cdns,trigger-address = <0x0>;
0206                         clocks = <&k3_clks 248 0>;
0207                         assigned-clocks = <&k3_clks 248 0>;
0208                         assigned-clock-parents = <&k3_clks 248 2>;
0209                         assigned-clock-rates = <166666666>;
0210                         power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
0211                         #address-cells = <1>;
0212                         #size-cells = <0>;
0213                 };
0214 
0215                 ospi1: spi@47050000 {
0216                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
0217                         reg = <0x0 0x47050000 0x0 0x100>,
0218                                 <0x7 0x00000000 0x1 0x00000000>;
0219                         interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
0220                         cdns,fifo-depth = <256>;
0221                         cdns,fifo-width = <4>;
0222                         cdns,trigger-address = <0x0>;
0223                         clocks = <&k3_clks 249 6>;
0224                         power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
0225                         #address-cells = <1>;
0226                         #size-cells = <0>;
0227                 };
0228         };
0229 
0230         mcu_cpsw: ethernet@46000000 {
0231                 compatible = "ti,am654-cpsw-nuss";
0232                 #address-cells = <2>;
0233                 #size-cells = <2>;
0234                 reg = <0x0 0x46000000 0x0 0x200000>;
0235                 reg-names = "cpsw_nuss";
0236                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
0237                 dma-coherent;
0238                 clocks = <&k3_clks 5 10>;
0239                 clock-names = "fck";
0240                 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
0241 
0242                 dmas = <&mcu_udmap 0xf000>,
0243                        <&mcu_udmap 0xf001>,
0244                        <&mcu_udmap 0xf002>,
0245                        <&mcu_udmap 0xf003>,
0246                        <&mcu_udmap 0xf004>,
0247                        <&mcu_udmap 0xf005>,
0248                        <&mcu_udmap 0xf006>,
0249                        <&mcu_udmap 0xf007>,
0250                        <&mcu_udmap 0x7000>;
0251                 dma-names = "tx0", "tx1", "tx2", "tx3",
0252                             "tx4", "tx5", "tx6", "tx7",
0253                             "rx";
0254 
0255                 ethernet-ports {
0256                         #address-cells = <1>;
0257                         #size-cells = <0>;
0258 
0259                         cpsw_port1: port@1 {
0260                                 reg = <1>;
0261                                 ti,mac-only;
0262                                 label = "port1";
0263                                 ti,syscon-efuse = <&mcu_conf 0x200>;
0264                                 phys = <&phy_gmii_sel 1>;
0265                         };
0266                 };
0267 
0268                 davinci_mdio: mdio@f00 {
0269                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0270                         reg = <0x0 0xf00 0x0 0x100>;
0271                         #address-cells = <1>;
0272                         #size-cells = <0>;
0273                         clocks = <&k3_clks 5 10>;
0274                         clock-names = "fck";
0275                         bus_freq = <1000000>;
0276                 };
0277 
0278                 cpts@3d000 {
0279                         compatible = "ti,am65-cpts";
0280                         reg = <0x0 0x3d000 0x0 0x400>;
0281                         clocks = <&mcu_cpsw_cpts_mux>;
0282                         clock-names = "cpts";
0283                         interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
0284                         interrupt-names = "cpts";
0285                         ti,cpts-ext-ts-inputs = <4>;
0286                         ti,cpts-periodic-outputs = <2>;
0287 
0288                         mcu_cpsw_cpts_mux: refclk-mux {
0289                                 #clock-cells = <0>;
0290                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
0291                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
0292                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
0293                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
0294                                 assigned-clocks = <&mcu_cpsw_cpts_mux>;
0295                                 assigned-clock-parents = <&k3_clks 118 5>;
0296                         };
0297                 };
0298         };
0299 
0300         mcu_r5fss0: r5fss@41000000 {
0301                 compatible = "ti,am654-r5fss";
0302                 ti,cluster-mode = <1>;
0303                 #address-cells = <1>;
0304                 #size-cells = <1>;
0305                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
0306                          <0x41400000 0x00 0x41400000 0x20000>;
0307                 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
0308 
0309                 mcu_r5fss0_core0: r5f@41000000 {
0310                         compatible = "ti,am654-r5f";
0311                         reg = <0x41000000 0x00008000>,
0312                               <0x41010000 0x00008000>;
0313                         reg-names = "atcm", "btcm";
0314                         ti,sci = <&dmsc>;
0315                         ti,sci-dev-id = <159>;
0316                         ti,sci-proc-ids = <0x01 0xff>;
0317                         resets = <&k3_reset 159 1>;
0318                         firmware-name = "am65x-mcu-r5f0_0-fw";
0319                         ti,atcm-enable = <1>;
0320                         ti,btcm-enable = <1>;
0321                         ti,loczrama = <1>;
0322                 };
0323 
0324                 mcu_r5fss0_core1: r5f@41400000 {
0325                         compatible = "ti,am654-r5f";
0326                         reg = <0x41400000 0x00008000>,
0327                               <0x41410000 0x00008000>;
0328                         reg-names = "atcm", "btcm";
0329                         ti,sci = <&dmsc>;
0330                         ti,sci-dev-id = <245>;
0331                         ti,sci-proc-ids = <0x02 0xff>;
0332                         resets = <&k3_reset 245 1>;
0333                         firmware-name = "am65x-mcu-r5f0_1-fw";
0334                         ti,atcm-enable = <1>;
0335                         ti,btcm-enable = <1>;
0336                         ti,loczrama = <1>;
0337                 };
0338         };
0339 
0340         mcu_rti1: watchdog@40610000 {
0341                 compatible = "ti,j7-rti-wdt";
0342                 reg = <0x0 0x40610000 0x0 0x100>;
0343                 clocks = <&k3_clks 135 0>;
0344                 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
0345                 assigned-clocks = <&k3_clks 135 0>;
0346                 assigned-clock-parents = <&k3_clks 135 4>;
0347         };
0348 };