0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM6 SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007 #include <dt-bindings/phy/phy-am654-serdes.h>
0008
0009 &cbass_main {
0010 msmc_ram: sram@70000000 {
0011 compatible = "mmio-sram";
0012 reg = <0x0 0x70000000 0x0 0x200000>;
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 ranges = <0x0 0x0 0x70000000 0x200000>;
0016
0017 atf-sram@0 {
0018 reg = <0x0 0x20000>;
0019 };
0020
0021 sysfw-sram@f0000 {
0022 reg = <0xf0000 0x10000>;
0023 };
0024
0025 l3cache-sram@100000 {
0026 reg = <0x100000 0x100000>;
0027 };
0028 };
0029
0030 gic500: interrupt-controller@1800000 {
0031 compatible = "arm,gic-v3";
0032 #address-cells = <2>;
0033 #size-cells = <2>;
0034 ranges;
0035 #interrupt-cells = <3>;
0036 interrupt-controller;
0037 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
0038 <0x00 0x01880000 0x00 0x90000>, /* GICR */
0039 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
0040 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
0041 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
0042 /*
0043 * vcpumntirq:
0044 * virtual CPU interface maintenance interrupt
0045 */
0046 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0047
0048 gic_its: msi-controller@1820000 {
0049 compatible = "arm,gic-v3-its";
0050 reg = <0x00 0x01820000 0x00 0x10000>;
0051 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0052 msi-controller;
0053 #msi-cells = <1>;
0054 };
0055 };
0056
0057 serdes0: serdes@900000 {
0058 compatible = "ti,phy-am654-serdes";
0059 reg = <0x0 0x900000 0x0 0x2000>;
0060 reg-names = "serdes";
0061 #phy-cells = <2>;
0062 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
0063 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
0064 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
0065 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
0066 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
0067 ti,serdes-clk = <&serdes0_clk>;
0068 #clock-cells = <1>;
0069 mux-controls = <&serdes_mux 0>;
0070 };
0071
0072 serdes1: serdes@910000 {
0073 compatible = "ti,phy-am654-serdes";
0074 reg = <0x0 0x910000 0x0 0x2000>;
0075 reg-names = "serdes";
0076 #phy-cells = <2>;
0077 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
0078 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
0079 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
0080 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
0081 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
0082 ti,serdes-clk = <&serdes1_clk>;
0083 #clock-cells = <1>;
0084 mux-controls = <&serdes_mux 1>;
0085 };
0086
0087 main_uart0: serial@2800000 {
0088 compatible = "ti,am654-uart";
0089 reg = <0x00 0x02800000 0x00 0x100>;
0090 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0091 clock-frequency = <48000000>;
0092 current-speed = <115200>;
0093 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0094 };
0095
0096 main_uart1: serial@2810000 {
0097 compatible = "ti,am654-uart";
0098 reg = <0x00 0x02810000 0x00 0x100>;
0099 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0100 clock-frequency = <48000000>;
0101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
0102 };
0103
0104 main_uart2: serial@2820000 {
0105 compatible = "ti,am654-uart";
0106 reg = <0x00 0x02820000 0x00 0x100>;
0107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0108 clock-frequency = <48000000>;
0109 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
0110 };
0111
0112 crypto: crypto@4e00000 {
0113 compatible = "ti,am654-sa2ul";
0114 reg = <0x0 0x4e00000 0x0 0x1200>;
0115 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
0116 #address-cells = <2>;
0117 #size-cells = <2>;
0118 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
0119
0120 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
0121 <&main_udmap 0x4001>;
0122 dma-names = "tx", "rx1", "rx2";
0123 dma-coherent;
0124
0125 rng: rng@4e10000 {
0126 compatible = "inside-secure,safexcel-eip76";
0127 reg = <0x0 0x4e10000 0x0 0x7d>;
0128 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0129 clocks = <&k3_clks 136 1>;
0130 };
0131 };
0132
0133 main_pmx0: pinctrl@11c000 {
0134 compatible = "pinctrl-single";
0135 reg = <0x0 0x11c000 0x0 0x2e4>;
0136 #pinctrl-cells = <1>;
0137 pinctrl-single,register-width = <32>;
0138 pinctrl-single,function-mask = <0xffffffff>;
0139 };
0140
0141 main_pmx1: pinctrl@11c2e8 {
0142 compatible = "pinctrl-single";
0143 reg = <0x0 0x11c2e8 0x0 0x24>;
0144 #pinctrl-cells = <1>;
0145 pinctrl-single,register-width = <32>;
0146 pinctrl-single,function-mask = <0xffffffff>;
0147 };
0148
0149 main_i2c0: i2c@2000000 {
0150 compatible = "ti,am654-i2c", "ti,omap4-i2c";
0151 reg = <0x0 0x2000000 0x0 0x100>;
0152 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 clock-names = "fck";
0156 clocks = <&k3_clks 110 1>;
0157 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
0158 };
0159
0160 main_i2c1: i2c@2010000 {
0161 compatible = "ti,am654-i2c", "ti,omap4-i2c";
0162 reg = <0x0 0x2010000 0x0 0x100>;
0163 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166 clock-names = "fck";
0167 clocks = <&k3_clks 111 1>;
0168 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
0169 };
0170
0171 main_i2c2: i2c@2020000 {
0172 compatible = "ti,am654-i2c", "ti,omap4-i2c";
0173 reg = <0x0 0x2020000 0x0 0x100>;
0174 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0175 #address-cells = <1>;
0176 #size-cells = <0>;
0177 clock-names = "fck";
0178 clocks = <&k3_clks 112 1>;
0179 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
0180 };
0181
0182 main_i2c3: i2c@2030000 {
0183 compatible = "ti,am654-i2c", "ti,omap4-i2c";
0184 reg = <0x0 0x2030000 0x0 0x100>;
0185 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0186 #address-cells = <1>;
0187 #size-cells = <0>;
0188 clock-names = "fck";
0189 clocks = <&k3_clks 113 1>;
0190 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
0191 };
0192
0193 ecap0: pwm@3100000 {
0194 compatible = "ti,am654-ecap", "ti,am3352-ecap";
0195 #pwm-cells = <3>;
0196 reg = <0x0 0x03100000 0x0 0x60>;
0197 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
0198 clocks = <&k3_clks 39 0>;
0199 clock-names = "fck";
0200 };
0201
0202 main_spi0: spi@2100000 {
0203 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0204 reg = <0x0 0x2100000 0x0 0x400>;
0205 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0206 clocks = <&k3_clks 137 1>;
0207 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
0208 #address-cells = <1>;
0209 #size-cells = <0>;
0210 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
0211 dma-names = "tx0", "rx0";
0212 };
0213
0214 main_spi1: spi@2110000 {
0215 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0216 reg = <0x0 0x2110000 0x0 0x400>;
0217 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&k3_clks 138 1>;
0219 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
0220 #address-cells = <1>;
0221 #size-cells = <0>;
0222 assigned-clocks = <&k3_clks 137 1>;
0223 assigned-clock-rates = <48000000>;
0224 };
0225
0226 main_spi2: spi@2120000 {
0227 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0228 reg = <0x0 0x2120000 0x0 0x400>;
0229 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0230 clocks = <&k3_clks 139 1>;
0231 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
0232 #address-cells = <1>;
0233 #size-cells = <0>;
0234 };
0235
0236 main_spi3: spi@2130000 {
0237 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0238 reg = <0x0 0x2130000 0x0 0x400>;
0239 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
0240 clocks = <&k3_clks 140 1>;
0241 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244 };
0245
0246 main_spi4: spi@2140000 {
0247 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0248 reg = <0x0 0x2140000 0x0 0x400>;
0249 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0250 clocks = <&k3_clks 141 1>;
0251 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
0252 #address-cells = <1>;
0253 #size-cells = <0>;
0254 };
0255
0256 sdhci0: mmc@4f80000 {
0257 compatible = "ti,am654-sdhci-5.1";
0258 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
0259 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
0260 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
0261 clock-names = "clk_ahb", "clk_xin";
0262 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0263 mmc-ddr-1_8v;
0264 mmc-hs200-1_8v;
0265 ti,otap-del-sel-legacy = <0x0>;
0266 ti,otap-del-sel-mmc-hs = <0x0>;
0267 ti,otap-del-sel-sd-hs = <0x0>;
0268 ti,otap-del-sel-sdr12 = <0x0>;
0269 ti,otap-del-sel-sdr25 = <0x0>;
0270 ti,otap-del-sel-sdr50 = <0x8>;
0271 ti,otap-del-sel-sdr104 = <0x7>;
0272 ti,otap-del-sel-ddr50 = <0x5>;
0273 ti,otap-del-sel-ddr52 = <0x5>;
0274 ti,otap-del-sel-hs200 = <0x5>;
0275 ti,otap-del-sel-hs400 = <0x0>;
0276 ti,trm-icp = <0x8>;
0277 dma-coherent;
0278 };
0279
0280 sdhci1: mmc@4fa0000 {
0281 compatible = "ti,am654-sdhci-5.1";
0282 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
0283 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
0284 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
0285 clock-names = "clk_ahb", "clk_xin";
0286 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
0287 ti,otap-del-sel-legacy = <0x0>;
0288 ti,otap-del-sel-mmc-hs = <0x0>;
0289 ti,otap-del-sel-sd-hs = <0x0>;
0290 ti,otap-del-sel-sdr12 = <0x0>;
0291 ti,otap-del-sel-sdr25 = <0x0>;
0292 ti,otap-del-sel-sdr50 = <0x8>;
0293 ti,otap-del-sel-sdr104 = <0x7>;
0294 ti,otap-del-sel-ddr50 = <0x4>;
0295 ti,otap-del-sel-ddr52 = <0x4>;
0296 ti,otap-del-sel-hs200 = <0x7>;
0297 ti,clkbuf-sel = <0x7>;
0298 ti,otap-del-sel = <0x2>;
0299 ti,trm-icp = <0x8>;
0300 dma-coherent;
0301 };
0302
0303 scm_conf: scm-conf@100000 {
0304 compatible = "syscon", "simple-mfd";
0305 reg = <0 0x00100000 0 0x1c000>;
0306 #address-cells = <1>;
0307 #size-cells = <1>;
0308 ranges = <0x0 0x0 0x00100000 0x1c000>;
0309
0310 pcie0_mode: pcie-mode@4060 {
0311 compatible = "syscon";
0312 reg = <0x00004060 0x4>;
0313 };
0314
0315 pcie1_mode: pcie-mode@4070 {
0316 compatible = "syscon";
0317 reg = <0x00004070 0x4>;
0318 };
0319
0320 pcie_devid: pcie-devid@210 {
0321 compatible = "syscon";
0322 reg = <0x00000210 0x4>;
0323 };
0324
0325 serdes0_clk: clock@4080 {
0326 compatible = "syscon";
0327 reg = <0x00004080 0x4>;
0328 };
0329
0330 serdes1_clk: clock@4090 {
0331 compatible = "syscon";
0332 reg = <0x00004090 0x4>;
0333 };
0334
0335 serdes_mux: mux-controller {
0336 compatible = "mmio-mux";
0337 #mux-control-cells = <1>;
0338 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
0339 <0x4090 0x3>; /* SERDES1 lane select */
0340 };
0341
0342 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
0343 compatible = "syscon";
0344 reg = <0x0000041e0 0x14>;
0345 };
0346
0347 ehrpwm_tbclk: clock@4140 {
0348 compatible = "ti,am654-ehrpwm-tbclk", "syscon";
0349 reg = <0x4140 0x18>;
0350 #clock-cells = <1>;
0351 };
0352 };
0353
0354 dwc3_0: dwc3@4000000 {
0355 compatible = "ti,am654-dwc3";
0356 reg = <0x0 0x4000000 0x0 0x4000>;
0357 #address-cells = <1>;
0358 #size-cells = <1>;
0359 ranges = <0x0 0x0 0x4000000 0x20000>;
0360 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0361 dma-coherent;
0362 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
0363 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
0364 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
0365 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
0366 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
0367
0368 usb0: usb@10000 {
0369 compatible = "snps,dwc3";
0370 reg = <0x10000 0x10000>;
0371 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0372 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0373 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0374 interrupt-names = "peripheral",
0375 "host",
0376 "otg";
0377 maximum-speed = "high-speed";
0378 dr_mode = "otg";
0379 phys = <&usb0_phy>;
0380 phy-names = "usb2-phy";
0381 snps,dis_u3_susphy_quirk;
0382 };
0383 };
0384
0385 usb0_phy: phy@4100000 {
0386 compatible = "ti,am654-usb2", "ti,omap-usb2";
0387 reg = <0x0 0x4100000 0x0 0x54>;
0388 syscon-phy-power = <&scm_conf 0x4000>;
0389 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
0390 clock-names = "wkupclk", "refclk";
0391 #phy-cells = <0>;
0392 };
0393
0394 dwc3_1: dwc3@4020000 {
0395 compatible = "ti,am654-dwc3";
0396 reg = <0x0 0x4020000 0x0 0x4000>;
0397 #address-cells = <1>;
0398 #size-cells = <1>;
0399 ranges = <0x0 0x0 0x4020000 0x20000>;
0400 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0401 dma-coherent;
0402 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
0403 clocks = <&k3_clks 152 2>;
0404 assigned-clocks = <&k3_clks 152 2>;
0405 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
0406
0407 usb1: usb@10000 {
0408 compatible = "snps,dwc3";
0409 reg = <0x10000 0x10000>;
0410 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0411 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0412 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0413 interrupt-names = "peripheral",
0414 "host",
0415 "otg";
0416 maximum-speed = "high-speed";
0417 dr_mode = "otg";
0418 phys = <&usb1_phy>;
0419 phy-names = "usb2-phy";
0420 };
0421 };
0422
0423 usb1_phy: phy@4110000 {
0424 compatible = "ti,am654-usb2", "ti,omap-usb2";
0425 reg = <0x0 0x4110000 0x0 0x54>;
0426 syscon-phy-power = <&scm_conf 0x4020>;
0427 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
0428 clock-names = "wkupclk", "refclk";
0429 #phy-cells = <0>;
0430 };
0431
0432 intr_main_gpio: interrupt-controller@a00000 {
0433 compatible = "ti,sci-intr";
0434 reg = <0x0 0x00a00000 0x0 0x400>;
0435 ti,intr-trigger-type = <1>;
0436 interrupt-controller;
0437 interrupt-parent = <&gic500>;
0438 #interrupt-cells = <1>;
0439 ti,sci = <&dmsc>;
0440 ti,sci-dev-id = <100>;
0441 ti,interrupt-ranges = <0 392 32>;
0442 };
0443
0444 main_navss: bus@30800000 {
0445 compatible = "simple-mfd";
0446 #address-cells = <2>;
0447 #size-cells = <2>;
0448 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
0449 dma-coherent;
0450 dma-ranges;
0451
0452 ti,sci-dev-id = <118>;
0453
0454 intr_main_navss: interrupt-controller@310e0000 {
0455 compatible = "ti,sci-intr";
0456 reg = <0x0 0x310e0000 0x0 0x2000>;
0457 ti,intr-trigger-type = <4>;
0458 interrupt-controller;
0459 interrupt-parent = <&gic500>;
0460 #interrupt-cells = <1>;
0461 ti,sci = <&dmsc>;
0462 ti,sci-dev-id = <182>;
0463 ti,interrupt-ranges = <0 64 64>,
0464 <64 448 64>;
0465 };
0466
0467 inta_main_udmass: interrupt-controller@33d00000 {
0468 compatible = "ti,sci-inta";
0469 reg = <0x0 0x33d00000 0x0 0x100000>;
0470 interrupt-controller;
0471 interrupt-parent = <&intr_main_navss>;
0472 msi-controller;
0473 #interrupt-cells = <0>;
0474 ti,sci = <&dmsc>;
0475 ti,sci-dev-id = <179>;
0476 ti,interrupt-ranges = <0 0 256>;
0477 };
0478
0479 secure_proxy_main: mailbox@32c00000 {
0480 compatible = "ti,am654-secure-proxy";
0481 #mbox-cells = <1>;
0482 reg-names = "target_data", "rt", "scfg";
0483 reg = <0x00 0x32c00000 0x00 0x100000>,
0484 <0x00 0x32400000 0x00 0x100000>,
0485 <0x00 0x32800000 0x00 0x100000>;
0486 interrupt-names = "rx_011";
0487 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0488 };
0489
0490 hwspinlock: spinlock@30e00000 {
0491 compatible = "ti,am654-hwspinlock";
0492 reg = <0x00 0x30e00000 0x00 0x1000>;
0493 #hwlock-cells = <1>;
0494 };
0495
0496 mailbox0_cluster0: mailbox@31f80000 {
0497 compatible = "ti,am654-mailbox";
0498 reg = <0x00 0x31f80000 0x00 0x200>;
0499 #mbox-cells = <1>;
0500 ti,mbox-num-users = <4>;
0501 ti,mbox-num-fifos = <16>;
0502 interrupt-parent = <&intr_main_navss>;
0503 };
0504
0505 mailbox0_cluster1: mailbox@31f81000 {
0506 compatible = "ti,am654-mailbox";
0507 reg = <0x00 0x31f81000 0x00 0x200>;
0508 #mbox-cells = <1>;
0509 ti,mbox-num-users = <4>;
0510 ti,mbox-num-fifos = <16>;
0511 interrupt-parent = <&intr_main_navss>;
0512 };
0513
0514 mailbox0_cluster2: mailbox@31f82000 {
0515 compatible = "ti,am654-mailbox";
0516 reg = <0x00 0x31f82000 0x00 0x200>;
0517 #mbox-cells = <1>;
0518 ti,mbox-num-users = <4>;
0519 ti,mbox-num-fifos = <16>;
0520 interrupt-parent = <&intr_main_navss>;
0521 };
0522
0523 mailbox0_cluster3: mailbox@31f83000 {
0524 compatible = "ti,am654-mailbox";
0525 reg = <0x00 0x31f83000 0x00 0x200>;
0526 #mbox-cells = <1>;
0527 ti,mbox-num-users = <4>;
0528 ti,mbox-num-fifos = <16>;
0529 interrupt-parent = <&intr_main_navss>;
0530 };
0531
0532 mailbox0_cluster4: mailbox@31f84000 {
0533 compatible = "ti,am654-mailbox";
0534 reg = <0x00 0x31f84000 0x00 0x200>;
0535 #mbox-cells = <1>;
0536 ti,mbox-num-users = <4>;
0537 ti,mbox-num-fifos = <16>;
0538 interrupt-parent = <&intr_main_navss>;
0539 };
0540
0541 mailbox0_cluster5: mailbox@31f85000 {
0542 compatible = "ti,am654-mailbox";
0543 reg = <0x00 0x31f85000 0x00 0x200>;
0544 #mbox-cells = <1>;
0545 ti,mbox-num-users = <4>;
0546 ti,mbox-num-fifos = <16>;
0547 interrupt-parent = <&intr_main_navss>;
0548 };
0549
0550 mailbox0_cluster6: mailbox@31f86000 {
0551 compatible = "ti,am654-mailbox";
0552 reg = <0x00 0x31f86000 0x00 0x200>;
0553 #mbox-cells = <1>;
0554 ti,mbox-num-users = <4>;
0555 ti,mbox-num-fifos = <16>;
0556 interrupt-parent = <&intr_main_navss>;
0557 };
0558
0559 mailbox0_cluster7: mailbox@31f87000 {
0560 compatible = "ti,am654-mailbox";
0561 reg = <0x00 0x31f87000 0x00 0x200>;
0562 #mbox-cells = <1>;
0563 ti,mbox-num-users = <4>;
0564 ti,mbox-num-fifos = <16>;
0565 interrupt-parent = <&intr_main_navss>;
0566 };
0567
0568 mailbox0_cluster8: mailbox@31f88000 {
0569 compatible = "ti,am654-mailbox";
0570 reg = <0x00 0x31f88000 0x00 0x200>;
0571 #mbox-cells = <1>;
0572 ti,mbox-num-users = <4>;
0573 ti,mbox-num-fifos = <16>;
0574 interrupt-parent = <&intr_main_navss>;
0575 };
0576
0577 mailbox0_cluster9: mailbox@31f89000 {
0578 compatible = "ti,am654-mailbox";
0579 reg = <0x00 0x31f89000 0x00 0x200>;
0580 #mbox-cells = <1>;
0581 ti,mbox-num-users = <4>;
0582 ti,mbox-num-fifos = <16>;
0583 interrupt-parent = <&intr_main_navss>;
0584 };
0585
0586 mailbox0_cluster10: mailbox@31f8a000 {
0587 compatible = "ti,am654-mailbox";
0588 reg = <0x00 0x31f8a000 0x00 0x200>;
0589 #mbox-cells = <1>;
0590 ti,mbox-num-users = <4>;
0591 ti,mbox-num-fifos = <16>;
0592 interrupt-parent = <&intr_main_navss>;
0593 };
0594
0595 mailbox0_cluster11: mailbox@31f8b000 {
0596 compatible = "ti,am654-mailbox";
0597 reg = <0x00 0x31f8b000 0x00 0x200>;
0598 #mbox-cells = <1>;
0599 ti,mbox-num-users = <4>;
0600 ti,mbox-num-fifos = <16>;
0601 interrupt-parent = <&intr_main_navss>;
0602 };
0603
0604 ringacc: ringacc@3c000000 {
0605 compatible = "ti,am654-navss-ringacc";
0606 reg = <0x0 0x3c000000 0x0 0x400000>,
0607 <0x0 0x38000000 0x0 0x400000>,
0608 <0x0 0x31120000 0x0 0x100>,
0609 <0x0 0x33000000 0x0 0x40000>;
0610 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0611 ti,num-rings = <818>;
0612 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0613 ti,sci = <&dmsc>;
0614 ti,sci-dev-id = <187>;
0615 msi-parent = <&inta_main_udmass>;
0616 };
0617
0618 main_udmap: dma-controller@31150000 {
0619 compatible = "ti,am654-navss-main-udmap";
0620 reg = <0x0 0x31150000 0x0 0x100>,
0621 <0x0 0x34000000 0x0 0x100000>,
0622 <0x0 0x35000000 0x0 0x100000>;
0623 reg-names = "gcfg", "rchanrt", "tchanrt";
0624 msi-parent = <&inta_main_udmass>;
0625 #dma-cells = <1>;
0626
0627 ti,sci = <&dmsc>;
0628 ti,sci-dev-id = <188>;
0629 ti,ringacc = <&ringacc>;
0630
0631 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
0632 <0xd>; /* TX_CHAN */
0633 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
0634 <0xa>; /* RX_CHAN */
0635 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
0636 };
0637
0638 cpts@310d0000 {
0639 compatible = "ti,am65-cpts";
0640 reg = <0x0 0x310d0000 0x0 0x400>;
0641 reg-names = "cpts";
0642 clocks = <&main_cpts_mux>;
0643 clock-names = "cpts";
0644 interrupts-extended = <&intr_main_navss 391>;
0645 interrupt-names = "cpts";
0646 ti,cpts-periodic-outputs = <6>;
0647 ti,cpts-ext-ts-inputs = <8>;
0648
0649 main_cpts_mux: refclk-mux {
0650 #clock-cells = <0>;
0651 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
0652 <&k3_clks 118 6>, <&k3_clks 118 3>,
0653 <&k3_clks 118 8>, <&k3_clks 118 14>,
0654 <&k3_clks 120 3>, <&k3_clks 121 3>;
0655 assigned-clocks = <&main_cpts_mux>;
0656 assigned-clock-parents = <&k3_clks 118 5>;
0657 };
0658 };
0659 };
0660
0661 main_gpio0: gpio@600000 {
0662 compatible = "ti,am654-gpio", "ti,keystone-gpio";
0663 reg = <0x0 0x600000 0x0 0x100>;
0664 gpio-controller;
0665 #gpio-cells = <2>;
0666 interrupt-parent = <&intr_main_gpio>;
0667 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
0668 interrupt-controller;
0669 #interrupt-cells = <2>;
0670 ti,ngpio = <96>;
0671 ti,davinci-gpio-unbanked = <0>;
0672 clocks = <&k3_clks 57 0>;
0673 clock-names = "gpio";
0674 };
0675
0676 main_gpio1: gpio@601000 {
0677 compatible = "ti,am654-gpio", "ti,keystone-gpio";
0678 reg = <0x0 0x601000 0x0 0x100>;
0679 gpio-controller;
0680 #gpio-cells = <2>;
0681 interrupt-parent = <&intr_main_gpio>;
0682 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
0683 interrupt-controller;
0684 #interrupt-cells = <2>;
0685 ti,ngpio = <90>;
0686 ti,davinci-gpio-unbanked = <0>;
0687 clocks = <&k3_clks 58 0>;
0688 clock-names = "gpio";
0689 };
0690
0691 pcie0_rc: pcie@5500000 {
0692 compatible = "ti,am654-pcie-rc";
0693 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
0694 reg-names = "app", "dbics", "config", "atu";
0695 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
0696 #address-cells = <3>;
0697 #size-cells = <2>;
0698 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
0699 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
0700 ti,syscon-pcie-id = <&pcie_devid>;
0701 ti,syscon-pcie-mode = <&pcie0_mode>;
0702 bus-range = <0x0 0xff>;
0703 num-viewport = <16>;
0704 max-link-speed = <2>;
0705 dma-coherent;
0706 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
0707 msi-map = <0x0 &gic_its 0x0 0x10000>;
0708 device_type = "pci";
0709 };
0710
0711 pcie0_ep: pcie-ep@5500000 {
0712 compatible = "ti,am654-pcie-ep";
0713 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
0714 reg-names = "app", "dbics", "addr_space", "atu";
0715 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
0716 ti,syscon-pcie-mode = <&pcie0_mode>;
0717 num-ib-windows = <16>;
0718 num-ob-windows = <16>;
0719 max-link-speed = <2>;
0720 dma-coherent;
0721 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
0722 };
0723
0724 pcie1_rc: pcie@5600000 {
0725 compatible = "ti,am654-pcie-rc";
0726 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
0727 reg-names = "app", "dbics", "config", "atu";
0728 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
0729 #address-cells = <3>;
0730 #size-cells = <2>;
0731 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
0732 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
0733 ti,syscon-pcie-id = <&pcie_devid>;
0734 ti,syscon-pcie-mode = <&pcie1_mode>;
0735 bus-range = <0x0 0xff>;
0736 num-viewport = <16>;
0737 max-link-speed = <2>;
0738 dma-coherent;
0739 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
0740 msi-map = <0x0 &gic_its 0x10000 0x10000>;
0741 device_type = "pci";
0742 };
0743
0744 pcie1_ep: pcie-ep@5600000 {
0745 compatible = "ti,am654-pcie-ep";
0746 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
0747 reg-names = "app", "dbics", "addr_space", "atu";
0748 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
0749 ti,syscon-pcie-mode = <&pcie1_mode>;
0750 num-ib-windows = <16>;
0751 num-ob-windows = <16>;
0752 max-link-speed = <2>;
0753 dma-coherent;
0754 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
0755 };
0756
0757 mcasp0: mcasp@2b00000 {
0758 compatible = "ti,am33xx-mcasp-audio";
0759 reg = <0x0 0x02b00000 0x0 0x2000>,
0760 <0x0 0x02b08000 0x0 0x1000>;
0761 reg-names = "mpu","dat";
0762 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0763 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0764 interrupt-names = "tx", "rx";
0765
0766 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
0767 dma-names = "tx", "rx";
0768
0769 clocks = <&k3_clks 104 0>;
0770 clock-names = "fck";
0771 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
0772 };
0773
0774 mcasp1: mcasp@2b10000 {
0775 compatible = "ti,am33xx-mcasp-audio";
0776 reg = <0x0 0x02b10000 0x0 0x2000>,
0777 <0x0 0x02b18000 0x0 0x1000>;
0778 reg-names = "mpu","dat";
0779 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0780 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
0781 interrupt-names = "tx", "rx";
0782
0783 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
0784 dma-names = "tx", "rx";
0785
0786 clocks = <&k3_clks 105 0>;
0787 clock-names = "fck";
0788 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
0789 };
0790
0791 mcasp2: mcasp@2b20000 {
0792 compatible = "ti,am33xx-mcasp-audio";
0793 reg = <0x0 0x02b20000 0x0 0x2000>,
0794 <0x0 0x02b28000 0x0 0x1000>;
0795 reg-names = "mpu","dat";
0796 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0797 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
0798 interrupt-names = "tx", "rx";
0799
0800 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
0801 dma-names = "tx", "rx";
0802
0803 clocks = <&k3_clks 106 0>;
0804 clock-names = "fck";
0805 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
0806 };
0807
0808 cal: cal@6f03000 {
0809 compatible = "ti,am654-cal";
0810 reg = <0x0 0x06f03000 0x0 0x400>,
0811 <0x0 0x06f03800 0x0 0x40>;
0812 reg-names = "cal_top",
0813 "cal_rx_core0";
0814 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0815 ti,camerrx-control = <&scm_conf 0x40c0>;
0816 clock-names = "fck";
0817 clocks = <&k3_clks 2 0>;
0818 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
0819
0820 ports {
0821 #address-cells = <1>;
0822 #size-cells = <0>;
0823
0824 csi2_0: port@0 {
0825 reg = <0>;
0826 };
0827 };
0828 };
0829
0830 dss: dss@4a00000 {
0831 compatible = "ti,am65x-dss";
0832 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
0833 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
0834 <0x0 0x04a06000 0x0 0x1000>, /* vid */
0835 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
0836 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
0837 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
0838 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
0839 reg-names = "common", "vidl1", "vid",
0840 "ovr1", "ovr2", "vp1", "vp2";
0841
0842 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
0843
0844 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
0845
0846 clocks = <&k3_clks 67 1>,
0847 <&k3_clks 216 1>,
0848 <&k3_clks 67 2>;
0849 clock-names = "fck", "vp1", "vp2";
0850
0851 /*
0852 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
0853 * DIV1. See "Figure 12-3365. DSS Integration"
0854 * in AM65x TRM for details.
0855 */
0856 assigned-clocks = <&k3_clks 67 2>;
0857 assigned-clock-parents = <&k3_clks 67 5>;
0858
0859 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
0860
0861 dma-coherent;
0862
0863 dss_ports: ports {
0864 #address-cells = <1>;
0865 #size-cells = <0>;
0866 };
0867 };
0868
0869 ehrpwm0: pwm@3000000 {
0870 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0871 #pwm-cells = <3>;
0872 reg = <0x0 0x3000000 0x0 0x100>;
0873 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
0874 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
0875 clock-names = "tbclk", "fck";
0876 };
0877
0878 ehrpwm1: pwm@3010000 {
0879 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0880 #pwm-cells = <3>;
0881 reg = <0x0 0x3010000 0x0 0x100>;
0882 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
0883 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
0884 clock-names = "tbclk", "fck";
0885 };
0886
0887 ehrpwm2: pwm@3020000 {
0888 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0889 #pwm-cells = <3>;
0890 reg = <0x0 0x3020000 0x0 0x100>;
0891 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
0892 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
0893 clock-names = "tbclk", "fck";
0894 };
0895
0896 ehrpwm3: pwm@3030000 {
0897 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0898 #pwm-cells = <3>;
0899 reg = <0x0 0x3030000 0x0 0x100>;
0900 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
0901 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
0902 clock-names = "tbclk", "fck";
0903 };
0904
0905 ehrpwm4: pwm@3040000 {
0906 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0907 #pwm-cells = <3>;
0908 reg = <0x0 0x3040000 0x0 0x100>;
0909 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
0910 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
0911 clock-names = "tbclk", "fck";
0912 };
0913
0914 ehrpwm5: pwm@3050000 {
0915 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
0916 #pwm-cells = <3>;
0917 reg = <0x0 0x3050000 0x0 0x100>;
0918 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
0919 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
0920 clock-names = "tbclk", "fck";
0921 };
0922
0923 icssg0: icssg@b000000 {
0924 compatible = "ti,am654-icssg";
0925 reg = <0x00 0xb000000 0x00 0x80000>;
0926 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
0927 #address-cells = <1>;
0928 #size-cells = <1>;
0929 ranges = <0x0 0x00 0xb000000 0x80000>;
0930
0931 icssg0_mem: memories@0 {
0932 reg = <0x0 0x2000>,
0933 <0x2000 0x2000>,
0934 <0x10000 0x10000>;
0935 reg-names = "dram0", "dram1",
0936 "shrdram2";
0937 };
0938
0939 icssg0_cfg: cfg@26000 {
0940 compatible = "ti,pruss-cfg", "syscon";
0941 reg = <0x26000 0x200>;
0942 #address-cells = <1>;
0943 #size-cells = <1>;
0944 ranges = <0x0 0x26000 0x2000>;
0945
0946 clocks {
0947 #address-cells = <1>;
0948 #size-cells = <0>;
0949
0950 icssg0_coreclk_mux: coreclk-mux@3c {
0951 reg = <0x3c>;
0952 #clock-cells = <0>;
0953 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
0954 <&k3_clks 62 3>; /* icssg0_iclk */
0955 assigned-clocks = <&icssg0_coreclk_mux>;
0956 assigned-clock-parents = <&k3_clks 62 3>;
0957 };
0958
0959 icssg0_iepclk_mux: iepclk-mux@30 {
0960 reg = <0x30>;
0961 #clock-cells = <0>;
0962 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
0963 <&icssg0_coreclk_mux>; /* core_clk */
0964 assigned-clocks = <&icssg0_iepclk_mux>;
0965 assigned-clock-parents = <&icssg0_coreclk_mux>;
0966 };
0967 };
0968 };
0969
0970 icssg0_mii_rt: mii-rt@32000 {
0971 compatible = "ti,pruss-mii", "syscon";
0972 reg = <0x32000 0x100>;
0973 };
0974
0975 icssg0_mii_g_rt: mii-g-rt@33000 {
0976 compatible = "ti,pruss-mii-g", "syscon";
0977 reg = <0x33000 0x1000>;
0978 };
0979
0980 icssg0_intc: interrupt-controller@20000 {
0981 compatible = "ti,icssg-intc";
0982 reg = <0x20000 0x2000>;
0983 interrupt-controller;
0984 #interrupt-cells = <3>;
0985 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
0986 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
0987 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
0988 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
0989 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
0990 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
0991 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
0992 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
0993 interrupt-names = "host_intr0", "host_intr1",
0994 "host_intr2", "host_intr3",
0995 "host_intr4", "host_intr5",
0996 "host_intr6", "host_intr7";
0997 };
0998
0999 pru0_0: pru@34000 {
1000 compatible = "ti,am654-pru";
1001 reg = <0x34000 0x4000>,
1002 <0x22000 0x100>,
1003 <0x22400 0x100>;
1004 reg-names = "iram", "control", "debug";
1005 firmware-name = "am65x-pru0_0-fw";
1006 };
1007
1008 rtu0_0: rtu@4000 {
1009 compatible = "ti,am654-rtu";
1010 reg = <0x4000 0x2000>,
1011 <0x23000 0x100>,
1012 <0x23400 0x100>;
1013 reg-names = "iram", "control", "debug";
1014 firmware-name = "am65x-rtu0_0-fw";
1015 };
1016
1017 tx_pru0_0: txpru@a000 {
1018 compatible = "ti,am654-tx-pru";
1019 reg = <0xa000 0x1800>,
1020 <0x25000 0x100>,
1021 <0x25400 0x100>;
1022 reg-names = "iram", "control", "debug";
1023 firmware-name = "am65x-txpru0_0-fw";
1024 };
1025
1026 pru0_1: pru@38000 {
1027 compatible = "ti,am654-pru";
1028 reg = <0x38000 0x4000>,
1029 <0x24000 0x100>,
1030 <0x24400 0x100>;
1031 reg-names = "iram", "control", "debug";
1032 firmware-name = "am65x-pru0_1-fw";
1033 };
1034
1035 rtu0_1: rtu@6000 {
1036 compatible = "ti,am654-rtu";
1037 reg = <0x6000 0x2000>,
1038 <0x23800 0x100>,
1039 <0x23c00 0x100>;
1040 reg-names = "iram", "control", "debug";
1041 firmware-name = "am65x-rtu0_1-fw";
1042 };
1043
1044 tx_pru0_1: txpru@c000 {
1045 compatible = "ti,am654-tx-pru";
1046 reg = <0xc000 0x1800>,
1047 <0x25800 0x100>,
1048 <0x25c00 0x100>;
1049 reg-names = "iram", "control", "debug";
1050 firmware-name = "am65x-txpru0_1-fw";
1051 };
1052
1053 icssg0_mdio: mdio@32400 {
1054 compatible = "ti,davinci_mdio";
1055 reg = <0x32400 0x100>;
1056 clocks = <&k3_clks 62 3>;
1057 clock-names = "fck";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 bus_freq = <1000000>;
1061 };
1062 };
1063
1064 icssg1: icssg@b100000 {
1065 compatible = "ti,am654-icssg";
1066 reg = <0x00 0xb100000 0x00 0x80000>;
1067 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070 ranges = <0x0 0x00 0xb100000 0x80000>;
1071
1072 icssg1_mem: memories@0 {
1073 reg = <0x0 0x2000>,
1074 <0x2000 0x2000>,
1075 <0x10000 0x10000>;
1076 reg-names = "dram0", "dram1",
1077 "shrdram2";
1078 };
1079
1080 icssg1_cfg: cfg@26000 {
1081 compatible = "ti,pruss-cfg", "syscon";
1082 reg = <0x26000 0x200>;
1083 #address-cells = <1>;
1084 #size-cells = <1>;
1085 ranges = <0x0 0x26000 0x2000>;
1086
1087 clocks {
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090
1091 icssg1_coreclk_mux: coreclk-mux@3c {
1092 reg = <0x3c>;
1093 #clock-cells = <0>;
1094 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1095 <&k3_clks 63 3>; /* icssg1_iclk */
1096 assigned-clocks = <&icssg1_coreclk_mux>;
1097 assigned-clock-parents = <&k3_clks 63 3>;
1098 };
1099
1100 icssg1_iepclk_mux: iepclk-mux@30 {
1101 reg = <0x30>;
1102 #clock-cells = <0>;
1103 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
1104 <&icssg1_coreclk_mux>; /* core_clk */
1105 assigned-clocks = <&icssg1_iepclk_mux>;
1106 assigned-clock-parents = <&icssg1_coreclk_mux>;
1107 };
1108 };
1109 };
1110
1111 icssg1_mii_rt: mii-rt@32000 {
1112 compatible = "ti,pruss-mii", "syscon";
1113 reg = <0x32000 0x100>;
1114 };
1115
1116 icssg1_mii_g_rt: mii-g-rt@33000 {
1117 compatible = "ti,pruss-mii-g", "syscon";
1118 reg = <0x33000 0x1000>;
1119 };
1120
1121 icssg1_intc: interrupt-controller@20000 {
1122 compatible = "ti,icssg-intc";
1123 reg = <0x20000 0x2000>;
1124 interrupt-controller;
1125 #interrupt-cells = <3>;
1126 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1134 interrupt-names = "host_intr0", "host_intr1",
1135 "host_intr2", "host_intr3",
1136 "host_intr4", "host_intr5",
1137 "host_intr6", "host_intr7";
1138 };
1139
1140 pru1_0: pru@34000 {
1141 compatible = "ti,am654-pru";
1142 reg = <0x34000 0x4000>,
1143 <0x22000 0x100>,
1144 <0x22400 0x100>;
1145 reg-names = "iram", "control", "debug";
1146 firmware-name = "am65x-pru1_0-fw";
1147 };
1148
1149 rtu1_0: rtu@4000 {
1150 compatible = "ti,am654-rtu";
1151 reg = <0x4000 0x2000>,
1152 <0x23000 0x100>,
1153 <0x23400 0x100>;
1154 reg-names = "iram", "control", "debug";
1155 firmware-name = "am65x-rtu1_0-fw";
1156 };
1157
1158 tx_pru1_0: txpru@a000 {
1159 compatible = "ti,am654-tx-pru";
1160 reg = <0xa000 0x1800>,
1161 <0x25000 0x100>,
1162 <0x25400 0x100>;
1163 reg-names = "iram", "control", "debug";
1164 firmware-name = "am65x-txpru1_0-fw";
1165 };
1166
1167 pru1_1: pru@38000 {
1168 compatible = "ti,am654-pru";
1169 reg = <0x38000 0x4000>,
1170 <0x24000 0x100>,
1171 <0x24400 0x100>;
1172 reg-names = "iram", "control", "debug";
1173 firmware-name = "am65x-pru1_1-fw";
1174 };
1175
1176 rtu1_1: rtu@6000 {
1177 compatible = "ti,am654-rtu";
1178 reg = <0x6000 0x2000>,
1179 <0x23800 0x100>,
1180 <0x23c00 0x100>;
1181 reg-names = "iram", "control", "debug";
1182 firmware-name = "am65x-rtu1_1-fw";
1183 };
1184
1185 tx_pru1_1: txpru@c000 {
1186 compatible = "ti,am654-tx-pru";
1187 reg = <0xc000 0x1800>,
1188 <0x25800 0x100>,
1189 <0x25c00 0x100>;
1190 reg-names = "iram", "control", "debug";
1191 firmware-name = "am65x-txpru1_1-fw";
1192 };
1193
1194 icssg1_mdio: mdio@32400 {
1195 compatible = "ti,davinci_mdio";
1196 reg = <0x32400 0x100>;
1197 clocks = <&k3_clks 63 3>;
1198 clock-names = "fck";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 bus_freq = <1000000>;
1202 };
1203 };
1204
1205 icssg2: icssg@b200000 {
1206 compatible = "ti,am654-icssg";
1207 reg = <0x00 0xb200000 0x00 0x80000>;
1208 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1209 #address-cells = <1>;
1210 #size-cells = <1>;
1211 ranges = <0x0 0x00 0xb200000 0x80000>;
1212
1213 icssg2_mem: memories@0 {
1214 reg = <0x0 0x2000>,
1215 <0x2000 0x2000>,
1216 <0x10000 0x10000>;
1217 reg-names = "dram0", "dram1",
1218 "shrdram2";
1219 };
1220
1221 icssg2_cfg: cfg@26000 {
1222 compatible = "ti,pruss-cfg", "syscon";
1223 reg = <0x26000 0x200>;
1224 #address-cells = <1>;
1225 #size-cells = <1>;
1226 ranges = <0x0 0x26000 0x2000>;
1227
1228 clocks {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231
1232 icssg2_coreclk_mux: coreclk-mux@3c {
1233 reg = <0x3c>;
1234 #clock-cells = <0>;
1235 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1236 <&k3_clks 64 3>; /* icssg1_iclk */
1237 assigned-clocks = <&icssg2_coreclk_mux>;
1238 assigned-clock-parents = <&k3_clks 64 3>;
1239 };
1240
1241 icssg2_iepclk_mux: iepclk-mux@30 {
1242 reg = <0x30>;
1243 #clock-cells = <0>;
1244 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
1245 <&icssg2_coreclk_mux>; /* core_clk */
1246 assigned-clocks = <&icssg2_iepclk_mux>;
1247 assigned-clock-parents = <&icssg2_coreclk_mux>;
1248 };
1249 };
1250 };
1251
1252 icssg2_mii_rt: mii-rt@32000 {
1253 compatible = "ti,pruss-mii", "syscon";
1254 reg = <0x32000 0x100>;
1255 };
1256
1257 icssg2_mii_g_rt: mii-g-rt@33000 {
1258 compatible = "ti,pruss-mii-g", "syscon";
1259 reg = <0x33000 0x1000>;
1260 };
1261
1262 icssg2_intc: interrupt-controller@20000 {
1263 compatible = "ti,icssg-intc";
1264 reg = <0x20000 0x2000>;
1265 interrupt-controller;
1266 #interrupt-cells = <3>;
1267 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1275 interrupt-names = "host_intr0", "host_intr1",
1276 "host_intr2", "host_intr3",
1277 "host_intr4", "host_intr5",
1278 "host_intr6", "host_intr7";
1279 };
1280
1281 pru2_0: pru@34000 {
1282 compatible = "ti,am654-pru";
1283 reg = <0x34000 0x4000>,
1284 <0x22000 0x100>,
1285 <0x22400 0x100>;
1286 reg-names = "iram", "control", "debug";
1287 firmware-name = "am65x-pru2_0-fw";
1288 };
1289
1290 rtu2_0: rtu@4000 {
1291 compatible = "ti,am654-rtu";
1292 reg = <0x4000 0x2000>,
1293 <0x23000 0x100>,
1294 <0x23400 0x100>;
1295 reg-names = "iram", "control", "debug";
1296 firmware-name = "am65x-rtu2_0-fw";
1297 };
1298
1299 tx_pru2_0: txpru@a000 {
1300 compatible = "ti,am654-tx-pru";
1301 reg = <0xa000 0x1800>,
1302 <0x25000 0x100>,
1303 <0x25400 0x100>;
1304 reg-names = "iram", "control", "debug";
1305 firmware-name = "am65x-txpru2_0-fw";
1306 };
1307
1308 pru2_1: pru@38000 {
1309 compatible = "ti,am654-pru";
1310 reg = <0x38000 0x4000>,
1311 <0x24000 0x100>,
1312 <0x24400 0x100>;
1313 reg-names = "iram", "control", "debug";
1314 firmware-name = "am65x-pru2_1-fw";
1315 };
1316
1317 rtu2_1: rtu@6000 {
1318 compatible = "ti,am654-rtu";
1319 reg = <0x6000 0x2000>,
1320 <0x23800 0x100>,
1321 <0x23c00 0x100>;
1322 reg-names = "iram", "control", "debug";
1323 firmware-name = "am65x-rtu2_1-fw";
1324 };
1325
1326 tx_pru2_1: txpru@c000 {
1327 compatible = "ti,am654-tx-pru";
1328 reg = <0xc000 0x1800>,
1329 <0x25800 0x100>,
1330 <0x25c00 0x100>;
1331 reg-names = "iram", "control", "debug";
1332 firmware-name = "am65x-txpru2_1-fw";
1333 };
1334
1335 icssg2_mdio: mdio@32400 {
1336 compatible = "ti,davinci_mdio";
1337 reg = <0x32400 0x100>;
1338 clocks = <&k3_clks 64 3>;
1339 clock-names = "fck";
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 bus_freq = <1000000>;
1343 };
1344 };
1345 };
