0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM642 SoC family in Dual core configuration
0004 *
0005 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "k3-am64.dtsi"
0011
0012 / {
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu-map {
0018 cluster0: cluster0 {
0019 core0 {
0020 cpu = <&cpu0>;
0021 };
0022
0023 core1 {
0024 cpu = <&cpu1>;
0025 };
0026 };
0027 };
0028
0029 cpu0: cpu@0 {
0030 compatible = "arm,cortex-a53";
0031 reg = <0x000>;
0032 device_type = "cpu";
0033 enable-method = "psci";
0034 i-cache-size = <0x8000>;
0035 i-cache-line-size = <64>;
0036 i-cache-sets = <256>;
0037 d-cache-size = <0x8000>;
0038 d-cache-line-size = <64>;
0039 d-cache-sets = <128>;
0040 next-level-cache = <&L2_0>;
0041 };
0042
0043 cpu1: cpu@1 {
0044 compatible = "arm,cortex-a53";
0045 reg = <0x001>;
0046 device_type = "cpu";
0047 enable-method = "psci";
0048 i-cache-size = <0x8000>;
0049 i-cache-line-size = <64>;
0050 i-cache-sets = <256>;
0051 d-cache-size = <0x8000>;
0052 d-cache-line-size = <64>;
0053 d-cache-sets = <128>;
0054 next-level-cache = <&L2_0>;
0055 };
0056 };
0057
0058 L2_0: l2-cache0 {
0059 compatible = "cache";
0060 cache-level = <2>;
0061 cache-size = <0x40000>;
0062 cache-line-size = <64>;
0063 cache-sets = <256>;
0064 };
0065 };
