0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/mux/ti-serdes.h>
0009 #include <dt-bindings/phy/phy.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/net/ti-dp83867.h>
0012 #include "k3-am642.dtsi"
0013
0014 / {
0015 compatible = "ti,am642-sk", "ti,am642";
0016 model = "Texas Instruments AM642 SK";
0017
0018 chosen {
0019 stdout-path = "serial2:115200n8";
0020 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
0021 };
0022
0023 memory@80000000 {
0024 device_type = "memory";
0025 /* 2G RAM */
0026 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
0027
0028 };
0029
0030 reserved-memory {
0031 #address-cells = <2>;
0032 #size-cells = <2>;
0033 ranges;
0034
0035 secure_ddr: optee@9e800000 {
0036 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
0037 alignment = <0x1000>;
0038 no-map;
0039 };
0040
0041 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
0042 compatible = "shared-dma-pool";
0043 reg = <0x00 0xa0000000 0x00 0x100000>;
0044 no-map;
0045 };
0046
0047 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
0048 compatible = "shared-dma-pool";
0049 reg = <0x00 0xa0100000 0x00 0xf00000>;
0050 no-map;
0051 };
0052
0053 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
0054 compatible = "shared-dma-pool";
0055 reg = <0x00 0xa1000000 0x00 0x100000>;
0056 no-map;
0057 };
0058
0059 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
0060 compatible = "shared-dma-pool";
0061 reg = <0x00 0xa1100000 0x00 0xf00000>;
0062 no-map;
0063 };
0064
0065 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
0066 compatible = "shared-dma-pool";
0067 reg = <0x00 0xa2000000 0x00 0x100000>;
0068 no-map;
0069 };
0070
0071 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
0072 compatible = "shared-dma-pool";
0073 reg = <0x00 0xa2100000 0x00 0xf00000>;
0074 no-map;
0075 };
0076
0077 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
0078 compatible = "shared-dma-pool";
0079 reg = <0x00 0xa3000000 0x00 0x100000>;
0080 no-map;
0081 };
0082
0083 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
0084 compatible = "shared-dma-pool";
0085 reg = <0x00 0xa3100000 0x00 0xf00000>;
0086 no-map;
0087 };
0088
0089 rtos_ipc_memory_region: ipc-memories@a5000000 {
0090 reg = <0x00 0xa5000000 0x00 0x00800000>;
0091 alignment = <0x1000>;
0092 no-map;
0093 };
0094 };
0095
0096 vusb_main: fixed-regulator-vusb-main5v0 {
0097 /* USB MAIN INPUT 5V DC */
0098 compatible = "regulator-fixed";
0099 regulator-name = "vusb_main5v0";
0100 regulator-min-microvolt = <5000000>;
0101 regulator-max-microvolt = <5000000>;
0102 regulator-always-on;
0103 regulator-boot-on;
0104 };
0105
0106 vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
0107 /* output of LP8733xx */
0108 compatible = "regulator-fixed";
0109 regulator-name = "vcc_3v3_sys";
0110 regulator-min-microvolt = <3300000>;
0111 regulator-max-microvolt = <3300000>;
0112 vin-supply = <&vusb_main>;
0113 regulator-always-on;
0114 regulator-boot-on;
0115 };
0116
0117 vdd_mmc1: fixed-regulator-sd {
0118 /* TPS2051BD */
0119 compatible = "regulator-fixed";
0120 regulator-name = "vdd_mmc1";
0121 regulator-min-microvolt = <3300000>;
0122 regulator-max-microvolt = <3300000>;
0123 regulator-boot-on;
0124 enable-active-high;
0125 vin-supply = <&vcc_3v3_sys>;
0126 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
0127 };
0128
0129 com8_ls_en: regulator-1 {
0130 compatible = "regulator-fixed";
0131 regulator-name = "com8_ls_en";
0132 regulator-min-microvolt = <3300000>;
0133 regulator-max-microvolt = <3300000>;
0134 regulator-always-on;
0135 regulator-boot-on;
0136 pinctrl-0 = <&main_com8_ls_en_pins_default>;
0137 pinctrl-names = "default";
0138 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
0139 };
0140
0141 wlan_en: regulator-2 {
0142 /* output of SN74AVC4T245RSVR */
0143 compatible = "regulator-fixed";
0144 regulator-name = "wlan_en";
0145 regulator-min-microvolt = <1800000>;
0146 regulator-max-microvolt = <1800000>;
0147 enable-active-high;
0148 pinctrl-0 = <&main_wlan_en_pins_default>;
0149 pinctrl-names = "default";
0150 vin-supply = <&com8_ls_en>;
0151 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
0152 };
0153 };
0154
0155 &main_pmx0 {
0156 main_mmc1_pins_default: main-mmc1-pins-default {
0157 pinctrl-single,pins = <
0158 AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
0159 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
0160 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
0161 AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
0162 AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
0163 AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
0164 AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
0165 AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
0166 >;
0167 };
0168
0169 main_uart0_pins_default: main-uart0-pins-default {
0170 pinctrl-single,pins = <
0171 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
0172 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
0173 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
0174 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
0175 >;
0176 };
0177
0178 main_usb0_pins_default: main-usb0-pins-default {
0179 pinctrl-single,pins = <
0180 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
0181 >;
0182 };
0183
0184 main_i2c1_pins_default: main-i2c1-pins-default {
0185 pinctrl-single,pins = <
0186 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
0187 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
0188 >;
0189 };
0190
0191 mdio1_pins_default: mdio1-pins-default {
0192 pinctrl-single,pins = <
0193 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
0194 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
0195 >;
0196 };
0197
0198 rgmii1_pins_default: rgmii1-pins-default {
0199 pinctrl-single,pins = <
0200 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
0201 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
0202 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
0203 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
0204 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
0205 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
0206 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
0207 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
0208 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
0209 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
0210 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
0211 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
0212 >;
0213 };
0214
0215 rgmii2_pins_default: rgmii2-pins-default {
0216 pinctrl-single,pins = <
0217 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
0218 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
0219 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
0220 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
0221 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
0222 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
0223 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
0224 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
0225 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
0226 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
0227 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
0228 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
0229 >;
0230 };
0231
0232 ospi0_pins_default: ospi0-pins-default {
0233 pinctrl-single,pins = <
0234 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
0235 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
0236 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
0237 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
0238 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
0239 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
0240 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
0241 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
0242 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
0243 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
0244 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
0245 >;
0246 };
0247
0248 main_ecap0_pins_default: main-ecap0-pins-default {
0249 pinctrl-single,pins = <
0250 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
0251 >;
0252 };
0253 main_wlan_en_pins_default: main-wlan-en-pins-default {
0254 pinctrl-single,pins = <
0255 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
0256 >;
0257 };
0258
0259 main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
0260 pinctrl-single,pins = <
0261 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
0262 >;
0263 };
0264
0265 main_wlan_pins_default: main-wlan-pins-default {
0266 pinctrl-single,pins = <
0267 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
0268 >;
0269 };
0270 };
0271
0272 &mcu_uart0 {
0273 status = "disabled";
0274 };
0275
0276 &mcu_uart1 {
0277 status = "disabled";
0278 };
0279
0280 &main_uart0 {
0281 pinctrl-names = "default";
0282 pinctrl-0 = <&main_uart0_pins_default>;
0283 };
0284
0285 &main_uart1 {
0286 /* main_uart1 is reserved for firmware usage */
0287 status = "reserved";
0288 };
0289
0290 &main_uart2 {
0291 status = "disabled";
0292 };
0293
0294 &main_uart3 {
0295 status = "disabled";
0296 };
0297
0298 &main_uart4 {
0299 status = "disabled";
0300 };
0301
0302 &main_uart5 {
0303 status = "disabled";
0304 };
0305
0306 &main_uart6 {
0307 status = "disabled";
0308 };
0309
0310 &mcu_i2c0 {
0311 status = "disabled";
0312 };
0313
0314 &mcu_i2c1 {
0315 status = "disabled";
0316 };
0317
0318 &main_i2c1 {
0319 pinctrl-names = "default";
0320 pinctrl-0 = <&main_i2c1_pins_default>;
0321 clock-frequency = <400000>;
0322
0323 exp1: gpio@70 {
0324 compatible = "nxp,pca9538";
0325 reg = <0x70>;
0326 gpio-controller;
0327 #gpio-cells = <2>;
0328 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
0329 "PRU_DETECT", "MMC1_SD_EN",
0330 "VPP_LDO_EN", "RPI_PS_3V3_En",
0331 "RPI_PS_5V0_En", "RPI_HAT_DETECT";
0332 };
0333 };
0334
0335 &main_i2c3 {
0336 status = "disabled";
0337 };
0338
0339 &mcu_spi0 {
0340 status = "disabled";
0341 };
0342
0343 &mcu_spi1 {
0344 status = "disabled";
0345 };
0346
0347 /* mcu_gpio0 is reserved for mcu firmware usage */
0348 &mcu_gpio0 {
0349 status = "reserved";
0350 };
0351
0352 &sdhci0 {
0353 vmmc-supply = <&wlan_en>;
0354 bus-width = <4>;
0355 non-removable;
0356 cap-power-off-card;
0357 keep-power-in-suspend;
0358 ti,driver-strength-ohm = <50>;
0359
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 wlcore: wlcore@2 {
0363 compatible = "ti,wl1837";
0364 reg = <2>;
0365 pinctrl-0 = <&main_wlan_pins_default>;
0366 pinctrl-names = "default";
0367 interrupt-parent = <&main_gpio0>;
0368 interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
0369 };
0370 };
0371
0372 &sdhci1 {
0373 /* SD/MMC */
0374 vmmc-supply = <&vdd_mmc1>;
0375 pinctrl-names = "default";
0376 bus-width = <4>;
0377 pinctrl-0 = <&main_mmc1_pins_default>;
0378 ti,driver-strength-ohm = <50>;
0379 disable-wp;
0380 };
0381
0382 &serdes_ln_ctrl {
0383 idle-states = <AM64_SERDES0_LANE0_USB>;
0384 };
0385
0386 &serdes0 {
0387 serdes0_usb_link: phy@0 {
0388 reg = <0>;
0389 cdns,num-lanes = <1>;
0390 #phy-cells = <0>;
0391 cdns,phy-type = <PHY_TYPE_USB3>;
0392 resets = <&serdes_wiz0 1>;
0393 };
0394 };
0395
0396 &usbss0 {
0397 ti,vbus-divider;
0398 };
0399
0400 &usb0 {
0401 dr_mode = "host";
0402 maximum-speed = "super-speed";
0403 pinctrl-names = "default";
0404 pinctrl-0 = <&main_usb0_pins_default>;
0405 phys = <&serdes0_usb_link>;
0406 phy-names = "cdns3,usb3-phy";
0407 };
0408
0409 &cpsw3g {
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&mdio1_pins_default
0412 &rgmii1_pins_default
0413 &rgmii2_pins_default>;
0414 };
0415
0416 &cpsw_port1 {
0417 phy-mode = "rgmii-rxid";
0418 phy-handle = <&cpsw3g_phy0>;
0419 };
0420
0421 &cpsw_port2 {
0422 phy-mode = "rgmii-rxid";
0423 phy-handle = <&cpsw3g_phy1>;
0424 };
0425
0426 &cpsw3g_mdio {
0427 cpsw3g_phy0: ethernet-phy@0 {
0428 reg = <0>;
0429 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0430 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0431 };
0432
0433 cpsw3g_phy1: ethernet-phy@1 {
0434 reg = <1>;
0435 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0436 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0437 };
0438 };
0439
0440 &tscadc0 {
0441 status = "disabled";
0442 };
0443
0444 &ospi0 {
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&ospi0_pins_default>;
0447
0448 flash@0 {
0449 compatible = "jedec,spi-nor";
0450 reg = <0x0>;
0451 spi-tx-bus-width = <8>;
0452 spi-rx-bus-width = <8>;
0453 spi-max-frequency = <25000000>;
0454 cdns,tshsl-ns = <60>;
0455 cdns,tsd2d-ns = <60>;
0456 cdns,tchsh-ns = <60>;
0457 cdns,tslch-ns = <60>;
0458 cdns,read-delay = <4>;
0459 };
0460 };
0461
0462 &mailbox0_cluster2 {
0463 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
0464 ti,mbox-rx = <0 0 2>;
0465 ti,mbox-tx = <1 0 2>;
0466 };
0467
0468 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
0469 ti,mbox-rx = <2 0 2>;
0470 ti,mbox-tx = <3 0 2>;
0471 };
0472 };
0473
0474 &mailbox0_cluster3 {
0475 status = "disabled";
0476 };
0477
0478 &mailbox0_cluster4 {
0479 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
0480 ti,mbox-rx = <0 0 2>;
0481 ti,mbox-tx = <1 0 2>;
0482 };
0483
0484 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
0485 ti,mbox-rx = <2 0 2>;
0486 ti,mbox-tx = <3 0 2>;
0487 };
0488 };
0489
0490 &mailbox0_cluster5 {
0491 status = "disabled";
0492 };
0493
0494 &mailbox0_cluster6 {
0495 mbox_m4_0: mbox-m4-0 {
0496 ti,mbox-rx = <0 0 2>;
0497 ti,mbox-tx = <1 0 2>;
0498 };
0499 };
0500
0501 &mailbox0_cluster7 {
0502 status = "disabled";
0503 };
0504
0505 &main_r5fss0_core0 {
0506 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
0507 memory-region = <&main_r5fss0_core0_dma_memory_region>,
0508 <&main_r5fss0_core0_memory_region>;
0509 };
0510
0511 &main_r5fss0_core1 {
0512 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
0513 memory-region = <&main_r5fss0_core1_dma_memory_region>,
0514 <&main_r5fss0_core1_memory_region>;
0515 };
0516
0517 &main_r5fss1_core0 {
0518 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
0519 memory-region = <&main_r5fss1_core0_dma_memory_region>,
0520 <&main_r5fss1_core0_memory_region>;
0521 };
0522
0523 &main_r5fss1_core1 {
0524 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
0525 memory-region = <&main_r5fss1_core1_dma_memory_region>,
0526 <&main_r5fss1_core1_memory_region>;
0527 };
0528
0529 &pcie0_rc {
0530 status = "disabled";
0531 };
0532
0533 &pcie0_ep {
0534 status = "disabled";
0535 };
0536
0537 &ecap0 {
0538 /* PWM is available on Pin 1 of header J3 */
0539 pinctrl-names = "default";
0540 pinctrl-0 = <&main_ecap0_pins_default>;
0541 };
0542
0543 &ecap1 {
0544 status = "disabled";
0545 };
0546
0547 &ecap2 {
0548 status = "disabled";
0549 };
0550
0551 &epwm0 {
0552 status = "disabled";
0553 };
0554
0555 &epwm1 {
0556 status = "disabled";
0557 };
0558
0559 &epwm2 {
0560 status = "disabled";
0561 };
0562
0563 &epwm3 {
0564 status = "disabled";
0565 };
0566
0567 &epwm4 {
0568 /*
0569 * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat)
0570 * But RPi Hat will be used for other use cases, so marking epwm4 as disabled.
0571 */
0572 status = "disabled";
0573 };
0574
0575 &epwm5 {
0576 /*
0577 * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat)
0578 * But RPi Hat will be used for other use cases, so marking epwm5 as disabled.
0579 */
0580 status = "disabled";
0581 };
0582
0583 &epwm6 {
0584 status = "disabled";
0585 };
0586
0587 &epwm7 {
0588 status = "disabled";
0589 };
0590
0591 &epwm8 {
0592 status = "disabled";
0593 };
0594
0595 &icssg0_mdio {
0596 status = "disabled";
0597 };
0598
0599 &icssg1_mdio {
0600 status = "disabled";
0601 };
0602
0603 &main_mcan0 {
0604 status = "disabled";
0605 };
0606
0607 &main_mcan1 {
0608 status = "disabled";
0609 };
