0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/phy/phy.h>
0009 #include <dt-bindings/mux/ti-serdes.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/net/ti-dp83867.h>
0013 #include "k3-am642.dtsi"
0014
0015 / {
0016 compatible = "ti,am642-evm", "ti,am642";
0017 model = "Texas Instruments AM642 EVM";
0018
0019 chosen {
0020 stdout-path = "serial2:115200n8";
0021 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
0022 };
0023
0024 memory@80000000 {
0025 device_type = "memory";
0026 /* 2G RAM */
0027 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
0028
0029 };
0030
0031 reserved-memory {
0032 #address-cells = <2>;
0033 #size-cells = <2>;
0034 ranges;
0035
0036 secure_ddr: optee@9e800000 {
0037 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
0038 alignment = <0x1000>;
0039 no-map;
0040 };
0041
0042 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
0043 compatible = "shared-dma-pool";
0044 reg = <0x00 0xa0000000 0x00 0x100000>;
0045 no-map;
0046 };
0047
0048 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
0049 compatible = "shared-dma-pool";
0050 reg = <0x00 0xa0100000 0x00 0xf00000>;
0051 no-map;
0052 };
0053
0054 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
0055 compatible = "shared-dma-pool";
0056 reg = <0x00 0xa1000000 0x00 0x100000>;
0057 no-map;
0058 };
0059
0060 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
0061 compatible = "shared-dma-pool";
0062 reg = <0x00 0xa1100000 0x00 0xf00000>;
0063 no-map;
0064 };
0065
0066 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
0067 compatible = "shared-dma-pool";
0068 reg = <0x00 0xa2000000 0x00 0x100000>;
0069 no-map;
0070 };
0071
0072 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
0073 compatible = "shared-dma-pool";
0074 reg = <0x00 0xa2100000 0x00 0xf00000>;
0075 no-map;
0076 };
0077
0078 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
0079 compatible = "shared-dma-pool";
0080 reg = <0x00 0xa3000000 0x00 0x100000>;
0081 no-map;
0082 };
0083
0084 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
0085 compatible = "shared-dma-pool";
0086 reg = <0x00 0xa3100000 0x00 0xf00000>;
0087 no-map;
0088 };
0089
0090 rtos_ipc_memory_region: ipc-memories@a5000000 {
0091 reg = <0x00 0xa5000000 0x00 0x00800000>;
0092 alignment = <0x1000>;
0093 no-map;
0094 };
0095 };
0096
0097 evm_12v0: fixedregulator-evm12v0 {
0098 /* main DC jack */
0099 compatible = "regulator-fixed";
0100 regulator-name = "evm_12v0";
0101 regulator-min-microvolt = <12000000>;
0102 regulator-max-microvolt = <12000000>;
0103 regulator-always-on;
0104 regulator-boot-on;
0105 };
0106
0107 vsys_5v0: fixedregulator-vsys5v0 {
0108 /* output of LM5140 */
0109 compatible = "regulator-fixed";
0110 regulator-name = "vsys_5v0";
0111 regulator-min-microvolt = <5000000>;
0112 regulator-max-microvolt = <5000000>;
0113 vin-supply = <&evm_12v0>;
0114 regulator-always-on;
0115 regulator-boot-on;
0116 };
0117
0118 vsys_3v3: fixedregulator-vsys3v3 {
0119 /* output of LM5140 */
0120 compatible = "regulator-fixed";
0121 regulator-name = "vsys_3v3";
0122 regulator-min-microvolt = <3300000>;
0123 regulator-max-microvolt = <3300000>;
0124 vin-supply = <&evm_12v0>;
0125 regulator-always-on;
0126 regulator-boot-on;
0127 };
0128
0129 vdd_mmc1: fixed-regulator-sd {
0130 /* TPS2051BD */
0131 compatible = "regulator-fixed";
0132 regulator-name = "vdd_mmc1";
0133 regulator-min-microvolt = <3300000>;
0134 regulator-max-microvolt = <3300000>;
0135 regulator-boot-on;
0136 enable-active-high;
0137 vin-supply = <&vsys_3v3>;
0138 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
0139 };
0140
0141 vddb: fixedregulator-vddb {
0142 compatible = "regulator-fixed";
0143 regulator-name = "vddb_3v3_display";
0144 regulator-min-microvolt = <3300000>;
0145 regulator-max-microvolt = <3300000>;
0146 vin-supply = <&vsys_3v3>;
0147 regulator-always-on;
0148 regulator-boot-on;
0149 };
0150
0151 leds {
0152 compatible = "gpio-leds";
0153
0154 led-0 {
0155 label = "am64-evm:red:heartbeat";
0156 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
0157 linux,default-trigger = "heartbeat";
0158 function = LED_FUNCTION_HEARTBEAT;
0159 default-state = "off";
0160 };
0161 };
0162
0163 mdio_mux: mux-controller {
0164 compatible = "gpio-mux";
0165 #mux-control-cells = <0>;
0166
0167 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
0168 };
0169
0170 mdio-mux-1 {
0171 compatible = "mdio-mux-multiplexer";
0172 mux-controls = <&mdio_mux>;
0173 mdio-parent-bus = <&cpsw3g_mdio>;
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176
0177 mdio@1 {
0178 reg = <0x1>;
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181
0182 cpsw3g_phy3: ethernet-phy@3 {
0183 reg = <3>;
0184 };
0185 };
0186 };
0187
0188 transceiver1: can-phy0 {
0189 compatible = "ti,tcan1042";
0190 #phy-cells = <0>;
0191 max-bitrate = <5000000>;
0192 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
0193 };
0194
0195 transceiver2: can-phy1 {
0196 compatible = "ti,tcan1042";
0197 #phy-cells = <0>;
0198 max-bitrate = <5000000>;
0199 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
0200 };
0201 };
0202
0203 &main_pmx0 {
0204 main_mmc1_pins_default: main-mmc1-pins-default {
0205 pinctrl-single,pins = <
0206 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
0207 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
0208 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
0209 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
0210 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
0211 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
0212 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
0213 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
0214 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
0215 >;
0216 };
0217
0218 main_uart0_pins_default: main-uart0-pins-default {
0219 pinctrl-single,pins = <
0220 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
0221 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
0222 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
0223 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
0224 >;
0225 };
0226
0227 main_spi0_pins_default: main-spi0-pins-default {
0228 pinctrl-single,pins = <
0229 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
0230 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
0231 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
0232 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
0233 >;
0234 };
0235
0236 main_i2c1_pins_default: main-i2c1-pins-default {
0237 pinctrl-single,pins = <
0238 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
0239 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
0240 >;
0241 };
0242
0243 mdio1_pins_default: mdio1-pins-default {
0244 pinctrl-single,pins = <
0245 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
0246 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
0247 >;
0248 };
0249
0250 rgmii1_pins_default: rgmii1-pins-default {
0251 pinctrl-single,pins = <
0252 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
0253 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
0254 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
0255 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
0256 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
0257 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
0258 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
0259 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
0260 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
0261 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
0262 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
0263 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
0264 >;
0265 };
0266
0267 rgmii2_pins_default: rgmii2-pins-default {
0268 pinctrl-single,pins = <
0269 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
0270 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
0271 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
0272 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
0273 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
0274 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
0275 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
0276 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
0277 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
0278 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
0279 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
0280 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
0281 >;
0282 };
0283
0284 main_usb0_pins_default: main-usb0-pins-default {
0285 pinctrl-single,pins = <
0286 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
0287 >;
0288 };
0289
0290 ospi0_pins_default: ospi0-pins-default {
0291 pinctrl-single,pins = <
0292 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
0293 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
0294 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
0295 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
0296 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
0297 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
0298 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
0299 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
0300 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
0301 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
0302 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
0303 >;
0304 };
0305
0306 main_ecap0_pins_default: main-ecap0-pins-default {
0307 pinctrl-single,pins = <
0308 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
0309 >;
0310 };
0311
0312 main_mcan0_pins_default: main-mcan0-pins-default {
0313 pinctrl-single,pins = <
0314 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
0315 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
0316 >;
0317 };
0318
0319 main_mcan1_pins_default: main-mcan1-pins-default {
0320 pinctrl-single,pins = <
0321 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
0322 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
0323 >;
0324 };
0325 };
0326
0327 &main_uart0 {
0328 pinctrl-names = "default";
0329 pinctrl-0 = <&main_uart0_pins_default>;
0330 };
0331
0332 /* main_uart1 is reserved for firmware usage */
0333 &main_uart1 {
0334 status = "reserved";
0335 };
0336
0337 &main_uart2 {
0338 status = "disabled";
0339 };
0340
0341 &main_uart3 {
0342 status = "disabled";
0343 };
0344
0345 &main_uart4 {
0346 status = "disabled";
0347 };
0348
0349 &main_uart5 {
0350 status = "disabled";
0351 };
0352
0353 &main_uart6 {
0354 status = "disabled";
0355 };
0356
0357 &mcu_uart0 {
0358 status = "disabled";
0359 };
0360
0361 &mcu_uart1 {
0362 status = "disabled";
0363 };
0364
0365 &main_i2c1 {
0366 pinctrl-names = "default";
0367 pinctrl-0 = <&main_i2c1_pins_default>;
0368 clock-frequency = <400000>;
0369
0370 exp1: gpio@22 {
0371 compatible = "ti,tca6424";
0372 reg = <0x22>;
0373 gpio-controller;
0374 #gpio-cells = <2>;
0375 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
0376 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
0377 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
0378 "MMC1_SD_EN", "FSI_FET_SEL",
0379 "MCAN0_STB_3V3", "MCAN1_STB_3V3",
0380 "CPSW_FET_SEL", "CPSW_FET2_SEL",
0381 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
0382 "GPIO_OLED_RESETn", "VPP_LDO_EN",
0383 "TEST_LED1", "TP92", "TP90", "TP88",
0384 "TP87", "TP86", "TP89", "TP91";
0385 };
0386
0387 /* osd9616p0899-10 */
0388 display@3c {
0389 compatible = "solomon,ssd1306fb-i2c";
0390 reg = <0x3c>;
0391 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
0392 vbat-supply = <&vddb>;
0393 solomon,height = <16>;
0394 solomon,width = <96>;
0395 solomon,com-seq;
0396 solomon,com-invdir;
0397 solomon,page-offset = <0>;
0398 solomon,prechargep1 = <2>;
0399 solomon,prechargep2 = <13>;
0400 };
0401 };
0402
0403 /* mcu_gpio0 is reserved for mcu firmware usage */
0404 &mcu_gpio0 {
0405 status = "reserved";
0406 };
0407
0408 &mcu_i2c0 {
0409 status = "disabled";
0410 };
0411
0412 &mcu_i2c1 {
0413 status = "disabled";
0414 };
0415
0416 &mcu_spi0 {
0417 status = "disabled";
0418 };
0419
0420 &mcu_spi1 {
0421 status = "disabled";
0422 };
0423
0424 &main_spi0 {
0425 pinctrl-names = "default";
0426 pinctrl-0 = <&main_spi0_pins_default>;
0427 ti,pindir-d0-out-d1-in;
0428 eeprom@0 {
0429 compatible = "microchip,93lc46b";
0430 reg = <0>;
0431 spi-max-frequency = <1000000>;
0432 spi-cs-high;
0433 data-size = <16>;
0434 };
0435 };
0436
0437 &sdhci0 {
0438 /* emmc */
0439 bus-width = <8>;
0440 non-removable;
0441 ti,driver-strength-ohm = <50>;
0442 disable-wp;
0443 };
0444
0445 &sdhci1 {
0446 /* SD/MMC */
0447 vmmc-supply = <&vdd_mmc1>;
0448 pinctrl-names = "default";
0449 bus-width = <4>;
0450 pinctrl-0 = <&main_mmc1_pins_default>;
0451 ti,driver-strength-ohm = <50>;
0452 disable-wp;
0453 };
0454
0455 &usbss0 {
0456 ti,vbus-divider;
0457 ti,usb2-only;
0458 };
0459
0460 &usb0 {
0461 dr_mode = "otg";
0462 maximum-speed = "high-speed";
0463 pinctrl-names = "default";
0464 pinctrl-0 = <&main_usb0_pins_default>;
0465 };
0466
0467 &cpsw3g {
0468 pinctrl-names = "default";
0469 pinctrl-0 = <&mdio1_pins_default
0470 &rgmii1_pins_default
0471 &rgmii2_pins_default>;
0472 };
0473
0474 &cpsw_port1 {
0475 phy-mode = "rgmii-rxid";
0476 phy-handle = <&cpsw3g_phy0>;
0477 };
0478
0479 &cpsw_port2 {
0480 phy-mode = "rgmii-rxid";
0481 phy-handle = <&cpsw3g_phy3>;
0482 };
0483
0484 &cpsw3g_mdio {
0485 cpsw3g_phy0: ethernet-phy@0 {
0486 reg = <0>;
0487 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0488 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0489 };
0490 };
0491
0492 &tscadc0 {
0493 /* ADC is reserved for R5 usage */
0494 status = "reserved";
0495 };
0496
0497 &ospi0 {
0498 pinctrl-names = "default";
0499 pinctrl-0 = <&ospi0_pins_default>;
0500
0501 flash@0 {
0502 compatible = "jedec,spi-nor";
0503 reg = <0x0>;
0504 spi-tx-bus-width = <8>;
0505 spi-rx-bus-width = <8>;
0506 spi-max-frequency = <25000000>;
0507 cdns,tshsl-ns = <60>;
0508 cdns,tsd2d-ns = <60>;
0509 cdns,tchsh-ns = <60>;
0510 cdns,tslch-ns = <60>;
0511 cdns,read-delay = <4>;
0512 };
0513 };
0514
0515 &mailbox0_cluster2 {
0516 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
0517 ti,mbox-rx = <0 0 2>;
0518 ti,mbox-tx = <1 0 2>;
0519 };
0520
0521 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
0522 ti,mbox-rx = <2 0 2>;
0523 ti,mbox-tx = <3 0 2>;
0524 };
0525 };
0526
0527 &mailbox0_cluster3 {
0528 status = "disabled";
0529 };
0530
0531 &mailbox0_cluster4 {
0532 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
0533 ti,mbox-rx = <0 0 2>;
0534 ti,mbox-tx = <1 0 2>;
0535 };
0536
0537 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
0538 ti,mbox-rx = <2 0 2>;
0539 ti,mbox-tx = <3 0 2>;
0540 };
0541 };
0542
0543 &mailbox0_cluster5 {
0544 status = "disabled";
0545 };
0546
0547 &mailbox0_cluster6 {
0548 mbox_m4_0: mbox-m4-0 {
0549 ti,mbox-rx = <0 0 2>;
0550 ti,mbox-tx = <1 0 2>;
0551 };
0552 };
0553
0554 &mailbox0_cluster7 {
0555 status = "disabled";
0556 };
0557
0558 &main_r5fss0_core0 {
0559 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
0560 memory-region = <&main_r5fss0_core0_dma_memory_region>,
0561 <&main_r5fss0_core0_memory_region>;
0562 };
0563
0564 &main_r5fss0_core1 {
0565 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
0566 memory-region = <&main_r5fss0_core1_dma_memory_region>,
0567 <&main_r5fss0_core1_memory_region>;
0568 };
0569
0570 &main_r5fss1_core0 {
0571 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
0572 memory-region = <&main_r5fss1_core0_dma_memory_region>,
0573 <&main_r5fss1_core0_memory_region>;
0574 };
0575
0576 &main_r5fss1_core1 {
0577 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
0578 memory-region = <&main_r5fss1_core1_dma_memory_region>,
0579 <&main_r5fss1_core1_memory_region>;
0580 };
0581
0582 &serdes_ln_ctrl {
0583 idle-states = <AM64_SERDES0_LANE0_PCIE0>;
0584 };
0585
0586 &serdes0 {
0587 serdes0_pcie_link: phy@0 {
0588 reg = <0>;
0589 cdns,num-lanes = <1>;
0590 #phy-cells = <0>;
0591 cdns,phy-type = <PHY_TYPE_PCIE>;
0592 resets = <&serdes_wiz0 1>;
0593 };
0594 };
0595
0596 &pcie0_rc {
0597 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
0598 phys = <&serdes0_pcie_link>;
0599 phy-names = "pcie-phy";
0600 num-lanes = <1>;
0601 };
0602
0603 &pcie0_ep {
0604 phys = <&serdes0_pcie_link>;
0605 phy-names = "pcie-phy";
0606 num-lanes = <1>;
0607 status = "disabled";
0608 };
0609
0610 &ecap0 {
0611 /* PWM is available on Pin 1 of header J12 */
0612 pinctrl-names = "default";
0613 pinctrl-0 = <&main_ecap0_pins_default>;
0614 };
0615
0616 &ecap1 {
0617 status = "disabled";
0618 };
0619
0620 &ecap2 {
0621 status = "disabled";
0622 };
0623
0624 &epwm0 {
0625 status = "disabled";
0626 };
0627
0628 &epwm1 {
0629 status = "disabled";
0630 };
0631
0632 &epwm2 {
0633 status = "disabled";
0634 };
0635
0636 &epwm3 {
0637 status = "disabled";
0638 };
0639
0640 &epwm4 {
0641 status = "disabled";
0642 };
0643
0644 &epwm5 {
0645 status = "disabled";
0646 };
0647
0648 &epwm6 {
0649 status = "disabled";
0650 };
0651
0652 &epwm7 {
0653 status = "disabled";
0654 };
0655
0656 &epwm8 {
0657 status = "disabled";
0658 };
0659
0660 &icssg0_mdio {
0661 status = "disabled";
0662 };
0663
0664 &icssg1_mdio {
0665 status = "disabled";
0666 };
0667
0668 &main_mcan0 {
0669 pinctrl-names = "default";
0670 pinctrl-0 = <&main_mcan0_pins_default>;
0671 phys = <&transceiver1>;
0672 };
0673
0674 &main_mcan1 {
0675 pinctrl-names = "default";
0676 pinctrl-0 = <&main_mcan1_pins_default>;
0677 phys = <&transceiver2>;
0678 };
