0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM642 SoC Family
0004 *
0005 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/k3.h>
0012 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0013
0014 / {
0015 model = "Texas Instruments K3 AM642 SoC";
0016 compatible = "ti,am642";
0017 interrupt-parent = <&gic500>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 serial0 = &mcu_uart0;
0023 serial1 = &mcu_uart1;
0024 serial2 = &main_uart0;
0025 serial3 = &main_uart1;
0026 serial4 = &main_uart2;
0027 serial5 = &main_uart3;
0028 serial6 = &main_uart4;
0029 serial7 = &main_uart5;
0030 serial8 = &main_uart6;
0031 ethernet0 = &cpsw_port1;
0032 ethernet1 = &cpsw_port2;
0033 mmc0 = &sdhci0;
0034 mmc1 = &sdhci1;
0035 };
0036
0037 chosen { };
0038
0039 firmware {
0040 optee {
0041 compatible = "linaro,optee-tz";
0042 method = "smc";
0043 };
0044
0045 psci: psci {
0046 compatible = "arm,psci-1.0";
0047 method = "smc";
0048 };
0049 };
0050
0051 a53_timer0: timer-cl0-cpu0 {
0052 compatible = "arm,armv8-timer";
0053 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
0054 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
0055 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
0056 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
0057 };
0058
0059 pmu: pmu {
0060 compatible = "arm,cortex-a53-pmu";
0061 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0062 };
0063
0064 cbass_main: bus@f4000 {
0065 compatible = "simple-bus";
0066 #address-cells = <2>;
0067 #size-cells = <2>;
0068 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
0069 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
0070 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
0071 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
0072 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
0073 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
0074 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
0075 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
0076 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
0077 <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
0078 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
0079 <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
0080 <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
0081 <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
0082 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
0083 <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
0084 <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
0085 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
0086 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
0087 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
0088 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
0089 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
0090 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
0091 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
0092 <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
0093 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
0094 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
0095 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
0096
0097 /* MCU Domain Range */
0098 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
0099
0100 cbass_mcu: bus@4000000 {
0101 compatible = "simple-bus";
0102 #address-cells = <2>;
0103 #size-cells = <2>;
0104 ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
0105 };
0106 };
0107 };
0108
0109 /* Now include the peripherals for each bus segments */
0110 #include "k3-am64-main.dtsi"
0111 #include "k3-am64-mcu.dtsi"
