0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM642 SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/phy/phy-cadence.h>
0009 #include <dt-bindings/phy/phy-ti.h>
0010
0011 / {
0012 serdes_refclk: clock-cmnrefclk {
0013 #clock-cells = <0>;
0014 compatible = "fixed-clock";
0015 clock-frequency = <0>;
0016 };
0017 };
0018
0019 &cbass_main {
0020 oc_sram: sram@70000000 {
0021 compatible = "mmio-sram";
0022 reg = <0x00 0x70000000 0x00 0x200000>;
0023 #address-cells = <1>;
0024 #size-cells = <1>;
0025 ranges = <0x0 0x00 0x70000000 0x200000>;
0026
0027 tfa-sram@1c0000 {
0028 reg = <0x1c0000 0x20000>;
0029 };
0030
0031 dmsc-sram@1e0000 {
0032 reg = <0x1e0000 0x1c000>;
0033 };
0034
0035 sproxy-sram@1fc000 {
0036 reg = <0x1fc000 0x4000>;
0037 };
0038 };
0039
0040 main_conf: syscon@43000000 {
0041 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
0042 reg = <0x0 0x43000000 0x0 0x20000>;
0043 #address-cells = <1>;
0044 #size-cells = <1>;
0045 ranges = <0x0 0x0 0x43000000 0x20000>;
0046
0047 serdes_ln_ctrl: mux-controller {
0048 compatible = "mmio-mux";
0049 #mux-control-cells = <1>;
0050 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
0051 };
0052 };
0053
0054 gic500: interrupt-controller@1800000 {
0055 compatible = "arm,gic-v3";
0056 #address-cells = <2>;
0057 #size-cells = <2>;
0058 ranges;
0059 #interrupt-cells = <3>;
0060 interrupt-controller;
0061 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
0062 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
0063 <0x01 0x00000000 0x00 0x2000>, /* GICC */
0064 <0x01 0x00010000 0x00 0x1000>, /* GICH */
0065 <0x01 0x00020000 0x00 0x2000>; /* GICV */
0066 /*
0067 * vcpumntirq:
0068 * virtual CPU interface maintenance interrupt
0069 */
0070 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0071
0072 gic_its: msi-controller@1820000 {
0073 compatible = "arm,gic-v3-its";
0074 reg = <0x00 0x01820000 0x00 0x10000>;
0075 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0076 msi-controller;
0077 #msi-cells = <1>;
0078 };
0079 };
0080
0081 dmss: bus@48000000 {
0082 compatible = "simple-mfd";
0083 #address-cells = <2>;
0084 #size-cells = <2>;
0085 dma-ranges;
0086 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
0087
0088 ti,sci-dev-id = <25>;
0089
0090 secure_proxy_main: mailbox@4d000000 {
0091 compatible = "ti,am654-secure-proxy";
0092 #mbox-cells = <1>;
0093 reg-names = "target_data", "rt", "scfg";
0094 reg = <0x00 0x4d000000 0x00 0x80000>,
0095 <0x00 0x4a600000 0x00 0x80000>,
0096 <0x00 0x4a400000 0x00 0x80000>;
0097 interrupt-names = "rx_012";
0098 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0099 };
0100
0101 inta_main_dmss: interrupt-controller@48000000 {
0102 compatible = "ti,sci-inta";
0103 reg = <0x00 0x48000000 0x00 0x100000>;
0104 #interrupt-cells = <0>;
0105 interrupt-controller;
0106 interrupt-parent = <&gic500>;
0107 msi-controller;
0108 ti,sci = <&dmsc>;
0109 ti,sci-dev-id = <28>;
0110 ti,interrupt-ranges = <4 68 36>;
0111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
0112 };
0113
0114 main_bcdma: dma-controller@485c0100 {
0115 compatible = "ti,am64-dmss-bcdma";
0116 reg = <0x00 0x485c0100 0x00 0x100>,
0117 <0x00 0x4c000000 0x00 0x20000>,
0118 <0x00 0x4a820000 0x00 0x20000>,
0119 <0x00 0x4aa40000 0x00 0x20000>,
0120 <0x00 0x4bc00000 0x00 0x100000>;
0121 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
0122 msi-parent = <&inta_main_dmss>;
0123 #dma-cells = <3>;
0124
0125 ti,sci = <&dmsc>;
0126 ti,sci-dev-id = <26>;
0127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
0128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
0129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
0130 };
0131
0132 main_pktdma: dma-controller@485c0000 {
0133 compatible = "ti,am64-dmss-pktdma";
0134 reg = <0x00 0x485c0000 0x00 0x100>,
0135 <0x00 0x4a800000 0x00 0x20000>,
0136 <0x00 0x4aa00000 0x00 0x40000>,
0137 <0x00 0x4b800000 0x00 0x400000>;
0138 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
0139 msi-parent = <&inta_main_dmss>;
0140 #dma-cells = <2>;
0141
0142 ti,sci = <&dmsc>;
0143 ti,sci-dev-id = <30>;
0144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
0145 <0x24>, /* CPSW_TX_CHAN */
0146 <0x25>, /* SAUL_TX_0_CHAN */
0147 <0x26>, /* SAUL_TX_1_CHAN */
0148 <0x27>, /* ICSSG_0_TX_CHAN */
0149 <0x28>; /* ICSSG_1_TX_CHAN */
0150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
0151 <0x11>, /* RING_CPSW_TX_CHAN */
0152 <0x12>, /* RING_SAUL_TX_0_CHAN */
0153 <0x13>, /* RING_SAUL_TX_1_CHAN */
0154 <0x14>, /* RING_ICSSG_0_TX_CHAN */
0155 <0x15>; /* RING_ICSSG_1_TX_CHAN */
0156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
0157 <0x2b>, /* CPSW_RX_CHAN */
0158 <0x2d>, /* SAUL_RX_0_CHAN */
0159 <0x2f>, /* SAUL_RX_1_CHAN */
0160 <0x31>, /* SAUL_RX_2_CHAN */
0161 <0x33>, /* SAUL_RX_3_CHAN */
0162 <0x35>, /* ICSSG_0_RX_CHAN */
0163 <0x37>; /* ICSSG_1_RX_CHAN */
0164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
0165 <0x2c>, /* FLOW_CPSW_RX_CHAN */
0166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
0167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
0168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
0169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
0170 };
0171 };
0172
0173 dmsc: system-controller@44043000 {
0174 compatible = "ti,k2g-sci";
0175 ti,host-id = <12>;
0176 mbox-names = "rx", "tx";
0177 mboxes = <&secure_proxy_main 12>,
0178 <&secure_proxy_main 13>;
0179 reg-names = "debug_messages";
0180 reg = <0x00 0x44043000 0x00 0xfe0>;
0181
0182 k3_pds: power-controller {
0183 compatible = "ti,sci-pm-domain";
0184 #power-domain-cells = <2>;
0185 };
0186
0187 k3_clks: clock-controller {
0188 compatible = "ti,k2g-sci-clk";
0189 #clock-cells = <2>;
0190 };
0191
0192 k3_reset: reset-controller {
0193 compatible = "ti,sci-reset";
0194 #reset-cells = <2>;
0195 };
0196 };
0197
0198 main_pmx0: pinctrl@f4000 {
0199 compatible = "pinctrl-single";
0200 reg = <0x00 0xf4000 0x00 0x2d0>;
0201 #pinctrl-cells = <1>;
0202 pinctrl-single,register-width = <32>;
0203 pinctrl-single,function-mask = <0xffffffff>;
0204 };
0205
0206 main_conf: syscon@43000000 {
0207 compatible = "syscon", "simple-mfd";
0208 reg = <0x00 0x43000000 0x00 0x20000>;
0209 #address-cells = <1>;
0210 #size-cells = <1>;
0211 ranges = <0x00 0x00 0x43000000 0x20000>;
0212
0213 chipid@14 {
0214 compatible = "ti,am654-chipid";
0215 reg = <0x00000014 0x4>;
0216 };
0217
0218 phy_gmii_sel: phy@4044 {
0219 compatible = "ti,am654-phy-gmii-sel";
0220 reg = <0x4044 0x8>;
0221 #phy-cells = <1>;
0222 };
0223
0224 epwm_tbclk: clock@4140 {
0225 compatible = "ti,am64-epwm-tbclk", "syscon";
0226 reg = <0x4130 0x4>;
0227 #clock-cells = <1>;
0228 };
0229 };
0230
0231 main_uart0: serial@2800000 {
0232 compatible = "ti,am64-uart", "ti,am654-uart";
0233 reg = <0x00 0x02800000 0x00 0x100>;
0234 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0235 clock-frequency = <48000000>;
0236 current-speed = <115200>;
0237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0238 clocks = <&k3_clks 146 0>;
0239 clock-names = "fclk";
0240 };
0241
0242 main_uart1: serial@2810000 {
0243 compatible = "ti,am64-uart", "ti,am654-uart";
0244 reg = <0x00 0x02810000 0x00 0x100>;
0245 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0246 clock-frequency = <48000000>;
0247 current-speed = <115200>;
0248 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
0249 clocks = <&k3_clks 152 0>;
0250 clock-names = "fclk";
0251 };
0252
0253 main_uart2: serial@2820000 {
0254 compatible = "ti,am64-uart", "ti,am654-uart";
0255 reg = <0x00 0x02820000 0x00 0x100>;
0256 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0257 clock-frequency = <48000000>;
0258 current-speed = <115200>;
0259 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
0260 clocks = <&k3_clks 153 0>;
0261 clock-names = "fclk";
0262 };
0263
0264 main_uart3: serial@2830000 {
0265 compatible = "ti,am64-uart", "ti,am654-uart";
0266 reg = <0x00 0x02830000 0x00 0x100>;
0267 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
0268 clock-frequency = <48000000>;
0269 current-speed = <115200>;
0270 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
0271 clocks = <&k3_clks 154 0>;
0272 clock-names = "fclk";
0273 };
0274
0275 main_uart4: serial@2840000 {
0276 compatible = "ti,am64-uart", "ti,am654-uart";
0277 reg = <0x00 0x02840000 0x00 0x100>;
0278 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
0279 clock-frequency = <48000000>;
0280 current-speed = <115200>;
0281 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
0282 clocks = <&k3_clks 155 0>;
0283 clock-names = "fclk";
0284 };
0285
0286 main_uart5: serial@2850000 {
0287 compatible = "ti,am64-uart", "ti,am654-uart";
0288 reg = <0x00 0x02850000 0x00 0x100>;
0289 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0290 clock-frequency = <48000000>;
0291 current-speed = <115200>;
0292 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
0293 clocks = <&k3_clks 156 0>;
0294 clock-names = "fclk";
0295 };
0296
0297 main_uart6: serial@2860000 {
0298 compatible = "ti,am64-uart", "ti,am654-uart";
0299 reg = <0x00 0x02860000 0x00 0x100>;
0300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0301 clock-frequency = <48000000>;
0302 current-speed = <115200>;
0303 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
0304 clocks = <&k3_clks 158 0>;
0305 clock-names = "fclk";
0306 };
0307
0308 main_i2c0: i2c@20000000 {
0309 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0310 reg = <0x00 0x20000000 0x00 0x100>;
0311 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
0315 clocks = <&k3_clks 102 2>;
0316 clock-names = "fck";
0317 };
0318
0319 main_i2c1: i2c@20010000 {
0320 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0321 reg = <0x00 0x20010000 0x00 0x100>;
0322 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
0323 #address-cells = <1>;
0324 #size-cells = <0>;
0325 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
0326 clocks = <&k3_clks 103 2>;
0327 clock-names = "fck";
0328 };
0329
0330 main_i2c2: i2c@20020000 {
0331 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0332 reg = <0x00 0x20020000 0x00 0x100>;
0333 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0334 #address-cells = <1>;
0335 #size-cells = <0>;
0336 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
0337 clocks = <&k3_clks 104 2>;
0338 clock-names = "fck";
0339 };
0340
0341 main_i2c3: i2c@20030000 {
0342 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0343 reg = <0x00 0x20030000 0x00 0x100>;
0344 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
0345 #address-cells = <1>;
0346 #size-cells = <0>;
0347 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
0348 clocks = <&k3_clks 105 2>;
0349 clock-names = "fck";
0350 };
0351
0352 main_spi0: spi@20100000 {
0353 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
0354 reg = <0x00 0x20100000 0x00 0x400>;
0355 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0356 #address-cells = <1>;
0357 #size-cells = <0>;
0358 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
0359 clocks = <&k3_clks 141 0>;
0360 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
0361 dma-names = "tx0", "rx0";
0362 };
0363
0364 main_spi1: spi@20110000 {
0365 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0366 reg = <0x00 0x20110000 0x00 0x400>;
0367 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0368 #address-cells = <1>;
0369 #size-cells = <0>;
0370 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
0371 clocks = <&k3_clks 142 0>;
0372 };
0373
0374 main_spi2: spi@20120000 {
0375 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0376 reg = <0x00 0x20120000 0x00 0x400>;
0377 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0378 #address-cells = <1>;
0379 #size-cells = <0>;
0380 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
0381 clocks = <&k3_clks 143 0>;
0382 };
0383
0384 main_spi3: spi@20130000 {
0385 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0386 reg = <0x00 0x20130000 0x00 0x400>;
0387 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0388 #address-cells = <1>;
0389 #size-cells = <0>;
0390 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
0391 clocks = <&k3_clks 144 0>;
0392 };
0393
0394 main_spi4: spi@20140000 {
0395 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0396 reg = <0x00 0x20140000 0x00 0x400>;
0397 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
0401 clocks = <&k3_clks 145 0>;
0402 };
0403
0404 main_gpio_intr: interrupt-controller@a00000 {
0405 compatible = "ti,sci-intr";
0406 reg = <0x00 0x00a00000 0x00 0x800>;
0407 ti,intr-trigger-type = <1>;
0408 interrupt-controller;
0409 interrupt-parent = <&gic500>;
0410 #interrupt-cells = <1>;
0411 ti,sci = <&dmsc>;
0412 ti,sci-dev-id = <3>;
0413 ti,interrupt-ranges = <0 32 16>;
0414 };
0415
0416 main_gpio0: gpio@600000 {
0417 compatible = "ti,am64-gpio", "ti,keystone-gpio";
0418 reg = <0x0 0x00600000 0x0 0x100>;
0419 gpio-controller;
0420 #gpio-cells = <2>;
0421 interrupt-parent = <&main_gpio_intr>;
0422 interrupts = <190>, <191>, <192>,
0423 <193>, <194>, <195>;
0424 interrupt-controller;
0425 #interrupt-cells = <2>;
0426 ti,ngpio = <87>;
0427 ti,davinci-gpio-unbanked = <0>;
0428 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
0429 clocks = <&k3_clks 77 0>;
0430 clock-names = "gpio";
0431 };
0432
0433 main_gpio1: gpio@601000 {
0434 compatible = "ti,am64-gpio", "ti,keystone-gpio";
0435 reg = <0x0 0x00601000 0x0 0x100>;
0436 gpio-controller;
0437 #gpio-cells = <2>;
0438 interrupt-parent = <&main_gpio_intr>;
0439 interrupts = <180>, <181>, <182>,
0440 <183>, <184>, <185>;
0441 interrupt-controller;
0442 #interrupt-cells = <2>;
0443 ti,ngpio = <88>;
0444 ti,davinci-gpio-unbanked = <0>;
0445 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
0446 clocks = <&k3_clks 78 0>;
0447 clock-names = "gpio";
0448 };
0449
0450 sdhci0: mmc@fa10000 {
0451 compatible = "ti,am64-sdhci-8bit";
0452 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
0453 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0454 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
0455 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
0456 clock-names = "clk_ahb", "clk_xin";
0457 mmc-ddr-1_8v;
0458 mmc-hs200-1_8v;
0459 ti,trm-icp = <0x2>;
0460 ti,otap-del-sel-legacy = <0x0>;
0461 ti,otap-del-sel-mmc-hs = <0x0>;
0462 ti,otap-del-sel-ddr52 = <0x6>;
0463 ti,otap-del-sel-hs200 = <0x7>;
0464 };
0465
0466 sdhci1: mmc@fa00000 {
0467 compatible = "ti,am64-sdhci-4bit";
0468 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
0469 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0470 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
0471 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
0472 clock-names = "clk_ahb", "clk_xin";
0473 ti,trm-icp = <0x2>;
0474 ti,otap-del-sel-legacy = <0x0>;
0475 ti,otap-del-sel-sd-hs = <0xf>;
0476 ti,otap-del-sel-sdr12 = <0xf>;
0477 ti,otap-del-sel-sdr25 = <0xf>;
0478 ti,otap-del-sel-sdr50 = <0xc>;
0479 ti,otap-del-sel-sdr104 = <0x6>;
0480 ti,otap-del-sel-ddr50 = <0x9>;
0481 ti,clkbuf-sel = <0x7>;
0482 };
0483
0484 cpsw3g: ethernet@8000000 {
0485 compatible = "ti,am642-cpsw-nuss";
0486 #address-cells = <2>;
0487 #size-cells = <2>;
0488 reg = <0x0 0x8000000 0x0 0x200000>;
0489 reg-names = "cpsw_nuss";
0490 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
0491 clocks = <&k3_clks 13 0>;
0492 assigned-clocks = <&k3_clks 13 1>;
0493 assigned-clock-parents = <&k3_clks 13 9>;
0494 clock-names = "fck";
0495 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
0496
0497 dmas = <&main_pktdma 0xC500 15>,
0498 <&main_pktdma 0xC501 15>,
0499 <&main_pktdma 0xC502 15>,
0500 <&main_pktdma 0xC503 15>,
0501 <&main_pktdma 0xC504 15>,
0502 <&main_pktdma 0xC505 15>,
0503 <&main_pktdma 0xC506 15>,
0504 <&main_pktdma 0xC507 15>,
0505 <&main_pktdma 0x4500 15>;
0506 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
0507 "tx7", "rx";
0508
0509 ethernet-ports {
0510 #address-cells = <1>;
0511 #size-cells = <0>;
0512
0513 cpsw_port1: port@1 {
0514 reg = <1>;
0515 ti,mac-only;
0516 label = "port1";
0517 phys = <&phy_gmii_sel 1>;
0518 mac-address = [00 00 00 00 00 00];
0519 ti,syscon-efuse = <&main_conf 0x200>;
0520 };
0521
0522 cpsw_port2: port@2 {
0523 reg = <2>;
0524 ti,mac-only;
0525 label = "port2";
0526 phys = <&phy_gmii_sel 2>;
0527 mac-address = [00 00 00 00 00 00];
0528 };
0529 };
0530
0531 cpsw3g_mdio: mdio@f00 {
0532 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0533 reg = <0x0 0xf00 0x0 0x100>;
0534 #address-cells = <1>;
0535 #size-cells = <0>;
0536 clocks = <&k3_clks 13 0>;
0537 clock-names = "fck";
0538 bus_freq = <1000000>;
0539 };
0540
0541 cpts@3d000 {
0542 compatible = "ti,j721e-cpts";
0543 reg = <0x0 0x3d000 0x0 0x400>;
0544 clocks = <&k3_clks 13 1>;
0545 clock-names = "cpts";
0546 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0547 interrupt-names = "cpts";
0548 ti,cpts-ext-ts-inputs = <4>;
0549 ti,cpts-periodic-outputs = <2>;
0550 };
0551 };
0552
0553 cpts@39000000 {
0554 compatible = "ti,j721e-cpts";
0555 reg = <0x0 0x39000000 0x0 0x400>;
0556 reg-names = "cpts";
0557 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
0558 clocks = <&k3_clks 84 0>;
0559 clock-names = "cpts";
0560 assigned-clocks = <&k3_clks 84 0>;
0561 assigned-clock-parents = <&k3_clks 84 8>;
0562 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0563 interrupt-names = "cpts";
0564 ti,cpts-periodic-outputs = <6>;
0565 ti,cpts-ext-ts-inputs = <8>;
0566 };
0567
0568 timesync_router: pinctrl@a40000 {
0569 compatible = "pinctrl-single";
0570 reg = <0x0 0xa40000 0x0 0x800>;
0571 #pinctrl-cells = <1>;
0572 pinctrl-single,register-width = <32>;
0573 pinctrl-single,function-mask = <0x000107ff>;
0574 };
0575
0576 usbss0: cdns-usb@f900000{
0577 compatible = "ti,am64-usb";
0578 reg = <0x00 0xf900000 0x00 0x100>;
0579 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
0580 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
0581 clock-names = "ref", "lpm";
0582 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
0583 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
0584 #address-cells = <2>;
0585 #size-cells = <2>;
0586 ranges;
0587 usb0: usb@f400000{
0588 compatible = "cdns,usb3";
0589 reg = <0x00 0xf400000 0x00 0x10000>,
0590 <0x00 0xf410000 0x00 0x10000>,
0591 <0x00 0xf420000 0x00 0x10000>;
0592 reg-names = "otg",
0593 "xhci",
0594 "dev";
0595 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
0596 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
0597 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
0598 interrupt-names = "host",
0599 "peripheral",
0600 "otg";
0601 maximum-speed = "super-speed";
0602 dr_mode = "otg";
0603 };
0604 };
0605
0606 tscadc0: tscadc@28001000 {
0607 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
0608 reg = <0x00 0x28001000 0x00 0x1000>;
0609 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0610 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
0611 clocks = <&k3_clks 0 0>;
0612 assigned-clocks = <&k3_clks 0 0>;
0613 assigned-clock-parents = <&k3_clks 0 3>;
0614 assigned-clock-rates = <60000000>;
0615 clock-names = "adc_tsc_fck";
0616
0617 adc {
0618 #io-channel-cells = <1>;
0619 compatible = "ti,am654-adc", "ti,am3359-adc";
0620 };
0621 };
0622
0623 fss: bus@fc00000 {
0624 compatible = "simple-bus";
0625 reg = <0x00 0x0fc00000 0x00 0x70000>;
0626 #address-cells = <2>;
0627 #size-cells = <2>;
0628 ranges;
0629
0630 ospi0: spi@fc40000 {
0631 compatible = "ti,am654-ospi", "cdns,qspi-nor";
0632 reg = <0x00 0x0fc40000 0x00 0x100>,
0633 <0x05 0x00000000 0x01 0x00000000>;
0634 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0635 cdns,fifo-depth = <256>;
0636 cdns,fifo-width = <4>;
0637 cdns,trigger-address = <0x0>;
0638 #address-cells = <0x1>;
0639 #size-cells = <0x0>;
0640 clocks = <&k3_clks 75 6>;
0641 assigned-clocks = <&k3_clks 75 6>;
0642 assigned-clock-parents = <&k3_clks 75 7>;
0643 assigned-clock-rates = <166666666>;
0644 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
0645 };
0646 };
0647
0648 hwspinlock: spinlock@2a000000 {
0649 compatible = "ti,am64-hwspinlock";
0650 reg = <0x00 0x2a000000 0x00 0x1000>;
0651 #hwlock-cells = <1>;
0652 };
0653
0654 mailbox0_cluster2: mailbox@29020000 {
0655 compatible = "ti,am64-mailbox";
0656 reg = <0x00 0x29020000 0x00 0x200>;
0657 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0658 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0659 #mbox-cells = <1>;
0660 ti,mbox-num-users = <4>;
0661 ti,mbox-num-fifos = <16>;
0662 };
0663
0664 mailbox0_cluster3: mailbox@29030000 {
0665 compatible = "ti,am64-mailbox";
0666 reg = <0x00 0x29030000 0x00 0x200>;
0667 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0668 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0669 #mbox-cells = <1>;
0670 ti,mbox-num-users = <4>;
0671 ti,mbox-num-fifos = <16>;
0672 };
0673
0674 mailbox0_cluster4: mailbox@29040000 {
0675 compatible = "ti,am64-mailbox";
0676 reg = <0x00 0x29040000 0x00 0x200>;
0677 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0678 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0679 #mbox-cells = <1>;
0680 ti,mbox-num-users = <4>;
0681 ti,mbox-num-fifos = <16>;
0682 };
0683
0684 mailbox0_cluster5: mailbox@29050000 {
0685 compatible = "ti,am64-mailbox";
0686 reg = <0x00 0x29050000 0x00 0x200>;
0687 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0688 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0689 #mbox-cells = <1>;
0690 ti,mbox-num-users = <4>;
0691 ti,mbox-num-fifos = <16>;
0692 };
0693
0694 mailbox0_cluster6: mailbox@29060000 {
0695 compatible = "ti,am64-mailbox";
0696 reg = <0x00 0x29060000 0x00 0x200>;
0697 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0698 #mbox-cells = <1>;
0699 ti,mbox-num-users = <4>;
0700 ti,mbox-num-fifos = <16>;
0701 };
0702
0703 mailbox0_cluster7: mailbox@29070000 {
0704 compatible = "ti,am64-mailbox";
0705 reg = <0x00 0x29070000 0x00 0x200>;
0706 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0707 #mbox-cells = <1>;
0708 ti,mbox-num-users = <4>;
0709 ti,mbox-num-fifos = <16>;
0710 };
0711
0712 main_r5fss0: r5fss@78000000 {
0713 compatible = "ti,am64-r5fss";
0714 ti,cluster-mode = <0>;
0715 #address-cells = <1>;
0716 #size-cells = <1>;
0717 ranges = <0x78000000 0x00 0x78000000 0x10000>,
0718 <0x78100000 0x00 0x78100000 0x10000>,
0719 <0x78200000 0x00 0x78200000 0x08000>,
0720 <0x78300000 0x00 0x78300000 0x08000>;
0721 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
0722
0723 main_r5fss0_core0: r5f@78000000 {
0724 compatible = "ti,am64-r5f";
0725 reg = <0x78000000 0x00010000>,
0726 <0x78100000 0x00010000>;
0727 reg-names = "atcm", "btcm";
0728 ti,sci = <&dmsc>;
0729 ti,sci-dev-id = <121>;
0730 ti,sci-proc-ids = <0x01 0xff>;
0731 resets = <&k3_reset 121 1>;
0732 firmware-name = "am64-main-r5f0_0-fw";
0733 ti,atcm-enable = <1>;
0734 ti,btcm-enable = <1>;
0735 ti,loczrama = <1>;
0736 };
0737
0738 main_r5fss0_core1: r5f@78200000 {
0739 compatible = "ti,am64-r5f";
0740 reg = <0x78200000 0x00008000>,
0741 <0x78300000 0x00008000>;
0742 reg-names = "atcm", "btcm";
0743 ti,sci = <&dmsc>;
0744 ti,sci-dev-id = <122>;
0745 ti,sci-proc-ids = <0x02 0xff>;
0746 resets = <&k3_reset 122 1>;
0747 firmware-name = "am64-main-r5f0_1-fw";
0748 ti,atcm-enable = <1>;
0749 ti,btcm-enable = <1>;
0750 ti,loczrama = <1>;
0751 };
0752 };
0753
0754 main_r5fss1: r5fss@78400000 {
0755 compatible = "ti,am64-r5fss";
0756 ti,cluster-mode = <0>;
0757 #address-cells = <1>;
0758 #size-cells = <1>;
0759 ranges = <0x78400000 0x00 0x78400000 0x10000>,
0760 <0x78500000 0x00 0x78500000 0x10000>,
0761 <0x78600000 0x00 0x78600000 0x08000>,
0762 <0x78700000 0x00 0x78700000 0x08000>;
0763 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
0764
0765 main_r5fss1_core0: r5f@78400000 {
0766 compatible = "ti,am64-r5f";
0767 reg = <0x78400000 0x00010000>,
0768 <0x78500000 0x00010000>;
0769 reg-names = "atcm", "btcm";
0770 ti,sci = <&dmsc>;
0771 ti,sci-dev-id = <123>;
0772 ti,sci-proc-ids = <0x06 0xff>;
0773 resets = <&k3_reset 123 1>;
0774 firmware-name = "am64-main-r5f1_0-fw";
0775 ti,atcm-enable = <1>;
0776 ti,btcm-enable = <1>;
0777 ti,loczrama = <1>;
0778 };
0779
0780 main_r5fss1_core1: r5f@78600000 {
0781 compatible = "ti,am64-r5f";
0782 reg = <0x78600000 0x00008000>,
0783 <0x78700000 0x00008000>;
0784 reg-names = "atcm", "btcm";
0785 ti,sci = <&dmsc>;
0786 ti,sci-dev-id = <124>;
0787 ti,sci-proc-ids = <0x07 0xff>;
0788 resets = <&k3_reset 124 1>;
0789 firmware-name = "am64-main-r5f1_1-fw";
0790 ti,atcm-enable = <1>;
0791 ti,btcm-enable = <1>;
0792 ti,loczrama = <1>;
0793 };
0794 };
0795
0796 serdes_wiz0: wiz@f000000 {
0797 compatible = "ti,am64-wiz-10g";
0798 #address-cells = <1>;
0799 #size-cells = <1>;
0800 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
0801 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
0802 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0803 num-lanes = <1>;
0804 #reset-cells = <1>;
0805 #clock-cells = <1>;
0806 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
0807
0808 assigned-clocks = <&k3_clks 162 1>;
0809 assigned-clock-parents = <&k3_clks 162 5>;
0810
0811 serdes0: serdes@f000000 {
0812 compatible = "ti,j721e-serdes-10g";
0813 reg = <0x0f000000 0x00010000>;
0814 reg-names = "torrent_phy";
0815 resets = <&serdes_wiz0 0>;
0816 reset-names = "torrent_reset";
0817 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
0818 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
0819 clock-names = "refclk", "phy_en_refclk";
0820 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
0821 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
0822 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
0823 assigned-clock-parents = <&k3_clks 162 1>,
0824 <&k3_clks 162 1>,
0825 <&k3_clks 162 1>;
0826 #address-cells = <1>;
0827 #size-cells = <0>;
0828 #clock-cells = <1>;
0829 };
0830 };
0831
0832 pcie0_rc: pcie@f102000 {
0833 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
0834 reg = <0x00 0x0f102000 0x00 0x1000>,
0835 <0x00 0x0f100000 0x00 0x400>,
0836 <0x00 0x0d000000 0x00 0x00800000>,
0837 <0x00 0x68000000 0x00 0x00001000>;
0838 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0839 interrupt-names = "link_state";
0840 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
0841 device_type = "pci";
0842 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
0843 max-link-speed = <2>;
0844 num-lanes = <1>;
0845 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0846 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
0847 clock-names = "fck", "pcie_refclk";
0848 #address-cells = <3>;
0849 #size-cells = <2>;
0850 bus-range = <0x0 0xff>;
0851 cdns,no-bar-match-nbits = <64>;
0852 vendor-id = <0x104c>;
0853 device-id = <0xb010>;
0854 msi-map = <0x0 &gic_its 0x0 0x10000>;
0855 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
0856 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
0857 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
0858 };
0859
0860 pcie0_ep: pcie-ep@f102000 {
0861 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
0862 reg = <0x00 0x0f102000 0x00 0x1000>,
0863 <0x00 0x0f100000 0x00 0x400>,
0864 <0x00 0x0d000000 0x00 0x00800000>,
0865 <0x00 0x68000000 0x00 0x08000000>;
0866 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0867 interrupt-names = "link_state";
0868 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
0869 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
0870 max-link-speed = <2>;
0871 num-lanes = <1>;
0872 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0873 clocks = <&k3_clks 114 0>;
0874 clock-names = "fck";
0875 max-functions = /bits/ 8 <1>;
0876 };
0877
0878 epwm0: pwm@23000000 {
0879 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0880 #pwm-cells = <3>;
0881 reg = <0x0 0x23000000 0x0 0x100>;
0882 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
0883 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
0884 clock-names = "tbclk", "fck";
0885 };
0886
0887 epwm1: pwm@23010000 {
0888 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0889 #pwm-cells = <3>;
0890 reg = <0x0 0x23010000 0x0 0x100>;
0891 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
0892 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
0893 clock-names = "tbclk", "fck";
0894 };
0895
0896 epwm2: pwm@23020000 {
0897 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0898 #pwm-cells = <3>;
0899 reg = <0x0 0x23020000 0x0 0x100>;
0900 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
0901 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
0902 clock-names = "tbclk", "fck";
0903 };
0904
0905 epwm3: pwm@23030000 {
0906 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0907 #pwm-cells = <3>;
0908 reg = <0x0 0x23030000 0x0 0x100>;
0909 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
0910 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
0911 clock-names = "tbclk", "fck";
0912 };
0913
0914 epwm4: pwm@23040000 {
0915 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0916 #pwm-cells = <3>;
0917 reg = <0x0 0x23040000 0x0 0x100>;
0918 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
0919 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
0920 clock-names = "tbclk", "fck";
0921 };
0922
0923 epwm5: pwm@23050000 {
0924 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0925 #pwm-cells = <3>;
0926 reg = <0x0 0x23050000 0x0 0x100>;
0927 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
0928 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
0929 clock-names = "tbclk", "fck";
0930 };
0931
0932 epwm6: pwm@23060000 {
0933 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0934 #pwm-cells = <3>;
0935 reg = <0x0 0x23060000 0x0 0x100>;
0936 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
0937 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
0938 clock-names = "tbclk", "fck";
0939 };
0940
0941 epwm7: pwm@23070000 {
0942 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0943 #pwm-cells = <3>;
0944 reg = <0x0 0x23070000 0x0 0x100>;
0945 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
0946 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
0947 clock-names = "tbclk", "fck";
0948 };
0949
0950 epwm8: pwm@23080000 {
0951 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
0952 #pwm-cells = <3>;
0953 reg = <0x0 0x23080000 0x0 0x100>;
0954 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
0955 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
0956 clock-names = "tbclk", "fck";
0957 };
0958
0959 ecap0: pwm@23100000 {
0960 compatible = "ti,am64-ecap", "ti,am3352-ecap";
0961 #pwm-cells = <3>;
0962 reg = <0x0 0x23100000 0x0 0x60>;
0963 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
0964 clocks = <&k3_clks 51 0>;
0965 clock-names = "fck";
0966 };
0967
0968 ecap1: pwm@23110000 {
0969 compatible = "ti,am64-ecap", "ti,am3352-ecap";
0970 #pwm-cells = <3>;
0971 reg = <0x0 0x23110000 0x0 0x60>;
0972 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
0973 clocks = <&k3_clks 52 0>;
0974 clock-names = "fck";
0975 };
0976
0977 ecap2: pwm@23120000 {
0978 compatible = "ti,am64-ecap", "ti,am3352-ecap";
0979 #pwm-cells = <3>;
0980 reg = <0x0 0x23120000 0x0 0x60>;
0981 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
0982 clocks = <&k3_clks 53 0>;
0983 clock-names = "fck";
0984 };
0985
0986 main_rti0: watchdog@e000000 {
0987 compatible = "ti,j7-rti-wdt";
0988 reg = <0x00 0xe000000 0x00 0x100>;
0989 clocks = <&k3_clks 125 0>;
0990 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
0991 assigned-clocks = <&k3_clks 125 0>;
0992 assigned-clock-parents = <&k3_clks 125 2>;
0993 };
0994
0995 main_rti1: watchdog@e010000 {
0996 compatible = "ti,j7-rti-wdt";
0997 reg = <0x00 0xe010000 0x00 0x100>;
0998 clocks = <&k3_clks 126 0>;
0999 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
1000 assigned-clocks = <&k3_clks 126 0>;
1001 assigned-clock-parents = <&k3_clks 126 2>;
1002 };
1003
1004 icssg0: icssg@30000000 {
1005 compatible = "ti,am642-icssg";
1006 reg = <0x00 0x30000000 0x00 0x80000>;
1007 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1010 ranges = <0x0 0x00 0x30000000 0x80000>;
1011
1012 icssg0_mem: memories@0 {
1013 reg = <0x0 0x2000>,
1014 <0x2000 0x2000>,
1015 <0x10000 0x10000>;
1016 reg-names = "dram0", "dram1", "shrdram2";
1017 };
1018
1019 icssg0_cfg: cfg@26000 {
1020 compatible = "ti,pruss-cfg", "syscon";
1021 reg = <0x26000 0x200>;
1022 #address-cells = <1>;
1023 #size-cells = <1>;
1024 ranges = <0x0 0x26000 0x2000>;
1025
1026 clocks {
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029
1030 icssg0_coreclk_mux: coreclk-mux@3c {
1031 reg = <0x3c>;
1032 #clock-cells = <0>;
1033 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1034 <&k3_clks 81 20>; /* icssg0_iclk */
1035 assigned-clocks = <&icssg0_coreclk_mux>;
1036 assigned-clock-parents = <&k3_clks 81 20>;
1037 };
1038
1039 icssg0_iepclk_mux: iepclk-mux@30 {
1040 reg = <0x30>;
1041 #clock-cells = <0>;
1042 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
1043 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
1044 assigned-clocks = <&icssg0_iepclk_mux>;
1045 assigned-clock-parents = <&icssg0_coreclk_mux>;
1046 };
1047 };
1048 };
1049
1050 icssg0_mii_rt: mii-rt@32000 {
1051 compatible = "ti,pruss-mii", "syscon";
1052 reg = <0x32000 0x100>;
1053 };
1054
1055 icssg0_mii_g_rt: mii-g-rt@33000 {
1056 compatible = "ti,pruss-mii-g", "syscon";
1057 reg = <0x33000 0x1000>;
1058 };
1059
1060 icssg0_intc: interrupt-controller@20000 {
1061 compatible = "ti,icssg-intc";
1062 reg = <0x20000 0x2000>;
1063 interrupt-controller;
1064 #interrupt-cells = <3>;
1065 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1073 interrupt-names = "host_intr0", "host_intr1",
1074 "host_intr2", "host_intr3",
1075 "host_intr4", "host_intr5",
1076 "host_intr6", "host_intr7";
1077 };
1078
1079 pru0_0: pru@34000 {
1080 compatible = "ti,am642-pru";
1081 reg = <0x34000 0x3000>,
1082 <0x22000 0x100>,
1083 <0x22400 0x100>;
1084 reg-names = "iram", "control", "debug";
1085 firmware-name = "am64x-pru0_0-fw";
1086 };
1087
1088 rtu0_0: rtu@4000 {
1089 compatible = "ti,am642-rtu";
1090 reg = <0x4000 0x2000>,
1091 <0x23000 0x100>,
1092 <0x23400 0x100>;
1093 reg-names = "iram", "control", "debug";
1094 firmware-name = "am64x-rtu0_0-fw";
1095 };
1096
1097 tx_pru0_0: txpru@a000 {
1098 compatible = "ti,am642-tx-pru";
1099 reg = <0xa000 0x1800>,
1100 <0x25000 0x100>,
1101 <0x25400 0x100>;
1102 reg-names = "iram", "control", "debug";
1103 firmware-name = "am64x-txpru0_0-fw";
1104 };
1105
1106 pru0_1: pru@38000 {
1107 compatible = "ti,am642-pru";
1108 reg = <0x38000 0x3000>,
1109 <0x24000 0x100>,
1110 <0x24400 0x100>;
1111 reg-names = "iram", "control", "debug";
1112 firmware-name = "am64x-pru0_1-fw";
1113 };
1114
1115 rtu0_1: rtu@6000 {
1116 compatible = "ti,am642-rtu";
1117 reg = <0x6000 0x2000>,
1118 <0x23800 0x100>,
1119 <0x23c00 0x100>;
1120 reg-names = "iram", "control", "debug";
1121 firmware-name = "am64x-rtu0_1-fw";
1122 };
1123
1124 tx_pru0_1: txpru@c000 {
1125 compatible = "ti,am642-tx-pru";
1126 reg = <0xc000 0x1800>,
1127 <0x25800 0x100>,
1128 <0x25c00 0x100>;
1129 reg-names = "iram", "control", "debug";
1130 firmware-name = "am64x-txpru0_1-fw";
1131 };
1132
1133 icssg0_mdio: mdio@32400 {
1134 compatible = "ti,davinci_mdio";
1135 reg = <0x32400 0x100>;
1136 clocks = <&k3_clks 62 3>;
1137 clock-names = "fck";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 bus_freq = <1000000>;
1141 };
1142 };
1143
1144 icssg1: icssg@30080000 {
1145 compatible = "ti,am642-icssg";
1146 reg = <0x00 0x30080000 0x00 0x80000>;
1147 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
1148 #address-cells = <1>;
1149 #size-cells = <1>;
1150 ranges = <0x0 0x00 0x30080000 0x80000>;
1151
1152 icssg1_mem: memories@0 {
1153 reg = <0x0 0x2000>,
1154 <0x2000 0x2000>,
1155 <0x10000 0x10000>;
1156 reg-names = "dram0", "dram1", "shrdram2";
1157 };
1158
1159 icssg1_cfg: cfg@26000 {
1160 compatible = "ti,pruss-cfg", "syscon";
1161 reg = <0x26000 0x200>;
1162 #address-cells = <1>;
1163 #size-cells = <1>;
1164 ranges = <0x0 0x26000 0x2000>;
1165
1166 clocks {
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1169
1170 icssg1_coreclk_mux: coreclk-mux@3c {
1171 reg = <0x3c>;
1172 #clock-cells = <0>;
1173 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1174 <&k3_clks 82 20>; /* icssg1_iclk */
1175 assigned-clocks = <&icssg1_coreclk_mux>;
1176 assigned-clock-parents = <&k3_clks 82 20>;
1177 };
1178
1179 icssg1_iepclk_mux: iepclk-mux@30 {
1180 reg = <0x30>;
1181 #clock-cells = <0>;
1182 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
1183 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
1184 assigned-clocks = <&icssg1_iepclk_mux>;
1185 assigned-clock-parents = <&icssg1_coreclk_mux>;
1186 };
1187 };
1188 };
1189
1190 icssg1_mii_rt: mii-rt@32000 {
1191 compatible = "ti,pruss-mii", "syscon";
1192 reg = <0x32000 0x100>;
1193 };
1194
1195 icssg1_mii_g_rt: mii-g-rt@33000 {
1196 compatible = "ti,pruss-mii-g", "syscon";
1197 reg = <0x33000 0x1000>;
1198 };
1199
1200 icssg1_intc: interrupt-controller@20000 {
1201 compatible = "ti,icssg-intc";
1202 reg = <0x20000 0x2000>;
1203 interrupt-controller;
1204 #interrupt-cells = <3>;
1205 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1213 interrupt-names = "host_intr0", "host_intr1",
1214 "host_intr2", "host_intr3",
1215 "host_intr4", "host_intr5",
1216 "host_intr6", "host_intr7";
1217 };
1218
1219 pru1_0: pru@34000 {
1220 compatible = "ti,am642-pru";
1221 reg = <0x34000 0x4000>,
1222 <0x22000 0x100>,
1223 <0x22400 0x100>;
1224 reg-names = "iram", "control", "debug";
1225 firmware-name = "am64x-pru1_0-fw";
1226 };
1227
1228 rtu1_0: rtu@4000 {
1229 compatible = "ti,am642-rtu";
1230 reg = <0x4000 0x2000>,
1231 <0x23000 0x100>,
1232 <0x23400 0x100>;
1233 reg-names = "iram", "control", "debug";
1234 firmware-name = "am64x-rtu1_0-fw";
1235 };
1236
1237 tx_pru1_0: txpru@a000 {
1238 compatible = "ti,am642-tx-pru";
1239 reg = <0xa000 0x1800>,
1240 <0x25000 0x100>,
1241 <0x25400 0x100>;
1242 reg-names = "iram", "control", "debug";
1243 firmware-name = "am64x-txpru1_0-fw";
1244 };
1245
1246 pru1_1: pru@38000 {
1247 compatible = "ti,am642-pru";
1248 reg = <0x38000 0x4000>,
1249 <0x24000 0x100>,
1250 <0x24400 0x100>;
1251 reg-names = "iram", "control", "debug";
1252 firmware-name = "am64x-pru1_1-fw";
1253 };
1254
1255 rtu1_1: rtu@6000 {
1256 compatible = "ti,am642-rtu";
1257 reg = <0x6000 0x2000>,
1258 <0x23800 0x100>,
1259 <0x23c00 0x100>;
1260 reg-names = "iram", "control", "debug";
1261 firmware-name = "am64x-rtu1_1-fw";
1262 };
1263
1264 tx_pru1_1: txpru@c000 {
1265 compatible = "ti,am642-tx-pru";
1266 reg = <0xc000 0x1800>,
1267 <0x25800 0x100>,
1268 <0x25c00 0x100>;
1269 reg-names = "iram", "control", "debug";
1270 firmware-name = "am64x-txpru1_1-fw";
1271 };
1272
1273 icssg1_mdio: mdio@32400 {
1274 compatible = "ti,davinci_mdio";
1275 reg = <0x32400 0x100>;
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1278 clocks = <&k3_clks 82 0>;
1279 clock-names = "fck";
1280 bus_freq = <1000000>;
1281 };
1282 };
1283
1284 main_mcan0: can@20701000 {
1285 compatible = "bosch,m_can";
1286 reg = <0x00 0x20701000 0x00 0x200>,
1287 <0x00 0x20708000 0x00 0x8000>;
1288 reg-names = "m_can", "message_ram";
1289 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
1290 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1291 clock-names = "hclk", "cclk";
1292 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1294 interrupt-names = "int0", "int1";
1295 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1296 };
1297
1298 main_mcan1: can@20711000 {
1299 compatible = "bosch,m_can";
1300 reg = <0x00 0x20711000 0x00 0x200>,
1301 <0x00 0x20718000 0x00 0x8000>;
1302 reg-names = "m_can", "message_ram";
1303 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
1304 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1305 clock-names = "hclk", "cclk";
1306 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1308 interrupt-names = "int0", "int1";
1309 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1310 };
1311 };
