0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM625 SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 &cbass_main {
0009 oc_sram: sram@70000000 {
0010 compatible = "mmio-sram";
0011 reg = <0x00 0x70000000 0x00 0x10000>;
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x0 0x00 0x70000000 0x10000>;
0015 };
0016
0017 gic500: interrupt-controller@1800000 {
0018 compatible = "arm,gic-v3";
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021 ranges;
0022 #interrupt-cells = <3>;
0023 interrupt-controller;
0024 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
0025 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
0026 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
0027 <0x01 0x00000000 0x00 0x2000>, /* GICC */
0028 <0x01 0x00010000 0x00 0x1000>, /* GICH */
0029 <0x01 0x00020000 0x00 0x2000>; /* GICV */
0030 /*
0031 * vcpumntirq:
0032 * virtual CPU interface maintenance interrupt
0033 */
0034 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0035
0036 gic_its: msi-controller@1820000 {
0037 compatible = "arm,gic-v3-its";
0038 reg = <0x00 0x01820000 0x00 0x10000>;
0039 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0040 msi-controller;
0041 #msi-cells = <1>;
0042 };
0043 };
0044
0045 main_conf: syscon@100000 {
0046 compatible = "syscon", "simple-mfd";
0047 reg = <0x00 0x00100000 0x00 0x20000>;
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 ranges = <0x0 0x00 0x00100000 0x20000>;
0051
0052 phy_gmii_sel: phy@4044 {
0053 compatible = "ti,am654-phy-gmii-sel";
0054 reg = <0x4044 0x8>;
0055 #phy-cells = <1>;
0056 };
0057 };
0058
0059 dmss: bus@48000000 {
0060 compatible = "simple-mfd";
0061 #address-cells = <2>;
0062 #size-cells = <2>;
0063 dma-ranges;
0064 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
0065
0066 ti,sci-dev-id = <25>;
0067
0068 secure_proxy_main: mailbox@4d000000 {
0069 compatible = "ti,am654-secure-proxy";
0070 #mbox-cells = <1>;
0071 reg-names = "target_data", "rt", "scfg";
0072 reg = <0x00 0x4d000000 0x00 0x80000>,
0073 <0x00 0x4a600000 0x00 0x80000>,
0074 <0x00 0x4a400000 0x00 0x80000>;
0075 interrupt-names = "rx_012";
0076 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0077 };
0078
0079 inta_main_dmss: interrupt-controller@48000000 {
0080 compatible = "ti,sci-inta";
0081 reg = <0x00 0x48000000 0x00 0x100000>;
0082 #interrupt-cells = <0>;
0083 interrupt-controller;
0084 interrupt-parent = <&gic500>;
0085 msi-controller;
0086 ti,sci = <&dmsc>;
0087 ti,sci-dev-id = <28>;
0088 ti,interrupt-ranges = <4 68 36>;
0089 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
0090 };
0091
0092 main_bcdma: dma-controller@485c0100 {
0093 compatible = "ti,am64-dmss-bcdma";
0094 reg = <0x00 0x485c0100 0x00 0x100>,
0095 <0x00 0x4c000000 0x00 0x20000>,
0096 <0x00 0x4a820000 0x00 0x20000>,
0097 <0x00 0x4aa40000 0x00 0x20000>,
0098 <0x00 0x4bc00000 0x00 0x100000>;
0099 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
0100 msi-parent = <&inta_main_dmss>;
0101 #dma-cells = <3>;
0102
0103 ti,sci = <&dmsc>;
0104 ti,sci-dev-id = <26>;
0105 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
0106 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
0107 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
0108 };
0109
0110 main_pktdma: dma-controller@485c0000 {
0111 compatible = "ti,am64-dmss-pktdma";
0112 reg = <0x00 0x485c0000 0x00 0x100>,
0113 <0x00 0x4a800000 0x00 0x20000>,
0114 <0x00 0x4aa00000 0x00 0x40000>,
0115 <0x00 0x4b800000 0x00 0x400000>;
0116 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
0117 msi-parent = <&inta_main_dmss>;
0118 #dma-cells = <2>;
0119
0120 ti,sci = <&dmsc>;
0121 ti,sci-dev-id = <30>;
0122 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
0123 <0x24>, /* CPSW_TX_CHAN */
0124 <0x25>, /* SAUL_TX_0_CHAN */
0125 <0x26>; /* SAUL_TX_1_CHAN */
0126 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
0127 <0x11>, /* RING_CPSW_TX_CHAN */
0128 <0x12>, /* RING_SAUL_TX_0_CHAN */
0129 <0x13>; /* RING_SAUL_TX_1_CHAN */
0130 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
0131 <0x2b>, /* CPSW_RX_CHAN */
0132 <0x2d>, /* SAUL_RX_0_CHAN */
0133 <0x2f>, /* SAUL_RX_1_CHAN */
0134 <0x31>, /* SAUL_RX_2_CHAN */
0135 <0x33>; /* SAUL_RX_3_CHAN */
0136 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
0137 <0x2c>, /* FLOW_CPSW_RX_CHAN */
0138 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
0139 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
0140 };
0141 };
0142
0143 dmsc: system-controller@44043000 {
0144 compatible = "ti,k2g-sci";
0145 ti,host-id = <12>;
0146 mbox-names = "rx", "tx";
0147 mboxes = <&secure_proxy_main 12>,
0148 <&secure_proxy_main 13>;
0149 reg-names = "debug_messages";
0150 reg = <0x00 0x44043000 0x00 0xfe0>;
0151
0152 k3_pds: power-controller {
0153 compatible = "ti,sci-pm-domain";
0154 #power-domain-cells = <2>;
0155 };
0156
0157 k3_clks: clock-controller {
0158 compatible = "ti,k2g-sci-clk";
0159 #clock-cells = <2>;
0160 };
0161
0162 k3_reset: reset-controller {
0163 compatible = "ti,sci-reset";
0164 #reset-cells = <2>;
0165 };
0166 };
0167
0168 crypto: crypto@40900000 {
0169 compatible = "ti,am62-sa3ul";
0170 reg = <0x00 0x40900000 0x00 0x1200>;
0171 power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
0172 #address-cells = <2>;
0173 #size-cells = <2>;
0174 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
0175
0176 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
0177 <&main_pktdma 0x7507 0>;
0178 dma-names = "tx", "rx1", "rx2";
0179 };
0180
0181 main_pmx0: pinctrl@f4000 {
0182 compatible = "pinctrl-single";
0183 reg = <0x00 0xf4000 0x00 0x2ac>;
0184 #pinctrl-cells = <1>;
0185 pinctrl-single,register-width = <32>;
0186 pinctrl-single,function-mask = <0xffffffff>;
0187 };
0188
0189 main_uart0: serial@2800000 {
0190 compatible = "ti,am64-uart", "ti,am654-uart";
0191 reg = <0x00 0x02800000 0x00 0x100>;
0192 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0193 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0194 clocks = <&k3_clks 146 0>;
0195 clock-names = "fclk";
0196 };
0197
0198 main_uart1: serial@2810000 {
0199 compatible = "ti,am64-uart", "ti,am654-uart";
0200 reg = <0x00 0x02810000 0x00 0x100>;
0201 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0202 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
0203 clocks = <&k3_clks 152 0>;
0204 clock-names = "fclk";
0205 };
0206
0207 main_uart2: serial@2820000 {
0208 compatible = "ti,am64-uart", "ti,am654-uart";
0209 reg = <0x00 0x02820000 0x00 0x100>;
0210 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0211 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
0212 clocks = <&k3_clks 153 0>;
0213 clock-names = "fclk";
0214 };
0215
0216 main_uart3: serial@2830000 {
0217 compatible = "ti,am64-uart", "ti,am654-uart";
0218 reg = <0x00 0x02830000 0x00 0x100>;
0219 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
0220 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
0221 clocks = <&k3_clks 154 0>;
0222 clock-names = "fclk";
0223 };
0224
0225 main_uart4: serial@2840000 {
0226 compatible = "ti,am64-uart", "ti,am654-uart";
0227 reg = <0x00 0x02840000 0x00 0x100>;
0228 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
0229 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
0230 clocks = <&k3_clks 155 0>;
0231 clock-names = "fclk";
0232 };
0233
0234 main_uart5: serial@2850000 {
0235 compatible = "ti,am64-uart", "ti,am654-uart";
0236 reg = <0x00 0x02850000 0x00 0x100>;
0237 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0238 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
0239 clocks = <&k3_clks 156 0>;
0240 clock-names = "fclk";
0241 };
0242
0243 main_uart6: serial@2860000 {
0244 compatible = "ti,am64-uart", "ti,am654-uart";
0245 reg = <0x00 0x02860000 0x00 0x100>;
0246 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0247 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
0248 clocks = <&k3_clks 158 0>;
0249 clock-names = "fclk";
0250 };
0251
0252 main_i2c0: i2c@20000000 {
0253 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0254 reg = <0x00 0x20000000 0x00 0x100>;
0255 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
0259 clocks = <&k3_clks 102 2>;
0260 clock-names = "fck";
0261 };
0262
0263 main_i2c1: i2c@20010000 {
0264 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0265 reg = <0x00 0x20010000 0x00 0x100>;
0266 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
0267 #address-cells = <1>;
0268 #size-cells = <0>;
0269 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
0270 clocks = <&k3_clks 103 2>;
0271 clock-names = "fck";
0272 };
0273
0274 main_i2c2: i2c@20020000 {
0275 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0276 reg = <0x00 0x20020000 0x00 0x100>;
0277 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
0281 clocks = <&k3_clks 104 2>;
0282 clock-names = "fck";
0283 };
0284
0285 main_i2c3: i2c@20030000 {
0286 compatible = "ti,am64-i2c", "ti,omap4-i2c";
0287 reg = <0x00 0x20030000 0x00 0x100>;
0288 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
0292 clocks = <&k3_clks 105 2>;
0293 clock-names = "fck";
0294 };
0295
0296 main_spi0: spi@20100000 {
0297 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
0298 reg = <0x00 0x20100000 0x00 0x400>;
0299 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
0303 clocks = <&k3_clks 172 0>;
0304 };
0305
0306 main_spi1: spi@20110000 {
0307 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0308 reg = <0x00 0x20110000 0x00 0x400>;
0309 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0310 #address-cells = <1>;
0311 #size-cells = <0>;
0312 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
0313 clocks = <&k3_clks 173 0>;
0314 };
0315
0316 main_spi2: spi@20120000 {
0317 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
0318 reg = <0x00 0x20120000 0x00 0x400>;
0319 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0320 #address-cells = <1>;
0321 #size-cells = <0>;
0322 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
0323 clocks = <&k3_clks 174 0>;
0324 };
0325
0326 main_gpio_intr: interrupt-controller@a00000 {
0327 compatible = "ti,sci-intr";
0328 reg = <0x00 0x00a00000 0x00 0x800>;
0329 ti,intr-trigger-type = <1>;
0330 interrupt-controller;
0331 interrupt-parent = <&gic500>;
0332 #interrupt-cells = <1>;
0333 ti,sci = <&dmsc>;
0334 ti,sci-dev-id = <3>;
0335 ti,interrupt-ranges = <0 32 16>;
0336 };
0337
0338 main_gpio0: gpio@600000 {
0339 compatible = "ti,am64-gpio", "ti,keystone-gpio";
0340 reg = <0x0 0x00600000 0x0 0x100>;
0341 gpio-controller;
0342 #gpio-cells = <2>;
0343 interrupt-parent = <&main_gpio_intr>;
0344 interrupts = <190>, <191>, <192>,
0345 <193>, <194>, <195>;
0346 interrupt-controller;
0347 #interrupt-cells = <2>;
0348 ti,ngpio = <87>;
0349 ti,davinci-gpio-unbanked = <0>;
0350 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
0351 clocks = <&k3_clks 77 0>;
0352 clock-names = "gpio";
0353 };
0354
0355 main_gpio1: gpio@601000 {
0356 compatible = "ti,am64-gpio", "ti,keystone-gpio";
0357 reg = <0x0 0x00601000 0x0 0x100>;
0358 gpio-controller;
0359 #gpio-cells = <2>;
0360 interrupt-parent = <&main_gpio_intr>;
0361 interrupts = <180>, <181>, <182>,
0362 <183>, <184>, <185>;
0363 interrupt-controller;
0364 #interrupt-cells = <2>;
0365 ti,ngpio = <88>;
0366 ti,davinci-gpio-unbanked = <0>;
0367 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
0368 clocks = <&k3_clks 78 0>;
0369 clock-names = "gpio";
0370 };
0371
0372 sdhci0: mmc@fa10000 {
0373 compatible = "ti,am62-sdhci";
0374 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
0375 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0376 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
0377 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
0378 clock-names = "clk_ahb", "clk_xin";
0379 assigned-clocks = <&k3_clks 57 6>;
0380 assigned-clock-parents = <&k3_clks 57 8>;
0381 mmc-ddr-1_8v;
0382 mmc-hs200-1_8v;
0383 ti,trm-icp = <0x2>;
0384 bus-width = <8>;
0385 ti,clkbuf-sel = <0x7>;
0386 ti,otap-del-sel-legacy = <0x0>;
0387 ti,otap-del-sel-mmc-hs = <0x0>;
0388 ti,otap-del-sel-ddr52 = <0x9>;
0389 ti,otap-del-sel-hs200 = <0x6>;
0390 };
0391
0392 sdhci1: mmc@fa00000 {
0393 compatible = "ti,am62-sdhci";
0394 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
0395 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0396 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
0397 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
0398 clock-names = "clk_ahb", "clk_xin";
0399 ti,trm-icp = <0x2>;
0400 ti,otap-del-sel-legacy = <0x0>;
0401 ti,otap-del-sel-sd-hs = <0x0>;
0402 ti,otap-del-sel-sdr12 = <0xf>;
0403 ti,otap-del-sel-sdr25 = <0xf>;
0404 ti,otap-del-sel-sdr50 = <0xc>;
0405 ti,otap-del-sel-sdr104 = <0x6>;
0406 ti,otap-del-sel-ddr50 = <0x9>;
0407 ti,itap-del-sel-legacy = <0x0>;
0408 ti,itap-del-sel-sd-hs = <0x0>;
0409 ti,itap-del-sel-sdr12 = <0x0>;
0410 ti,itap-del-sel-sdr25 = <0x0>;
0411 ti,clkbuf-sel = <0x7>;
0412 bus-width = <4>;
0413 };
0414
0415 sdhci2: mmc@fa20000 {
0416 compatible = "ti,am62-sdhci";
0417 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
0418 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0419 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
0420 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
0421 clock-names = "clk_ahb", "clk_xin";
0422 ti,trm-icp = <0x2>;
0423 ti,otap-del-sel-legacy = <0x0>;
0424 ti,otap-del-sel-sd-hs = <0x0>;
0425 ti,otap-del-sel-sdr12 = <0xf>;
0426 ti,otap-del-sel-sdr25 = <0xf>;
0427 ti,otap-del-sel-sdr50 = <0xc>;
0428 ti,otap-del-sel-sdr104 = <0x6>;
0429 ti,otap-del-sel-ddr50 = <0x9>;
0430 ti,itap-del-sel-legacy = <0x0>;
0431 ti,itap-del-sel-sd-hs = <0x0>;
0432 ti,itap-del-sel-sdr12 = <0x0>;
0433 ti,itap-del-sel-sdr25 = <0x0>;
0434 ti,clkbuf-sel = <0x7>;
0435 };
0436
0437 fss: bus@fc00000 {
0438 compatible = "simple-bus";
0439 reg = <0x00 0x0fc00000 0x00 0x70000>;
0440 #address-cells = <2>;
0441 #size-cells = <2>;
0442 ranges;
0443
0444 ospi0: spi@fc40000 {
0445 compatible = "ti,am654-ospi", "cdns,qspi-nor";
0446 reg = <0x00 0x0fc40000 0x00 0x100>,
0447 <0x05 0x00000000 0x01 0x00000000>;
0448 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0449 cdns,fifo-depth = <256>;
0450 cdns,fifo-width = <4>;
0451 cdns,trigger-address = <0x0>;
0452 clocks = <&k3_clks 75 7>;
0453 assigned-clocks = <&k3_clks 75 7>;
0454 assigned-clock-parents = <&k3_clks 75 8>;
0455 assigned-clock-rates = <166666666>;
0456 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459 };
0460 };
0461
0462 cpsw3g: ethernet@8000000 {
0463 compatible = "ti,am642-cpsw-nuss";
0464 #address-cells = <2>;
0465 #size-cells = <2>;
0466 reg = <0x00 0x08000000 0x00 0x200000>;
0467 reg-names = "cpsw_nuss";
0468 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
0469 clocks = <&k3_clks 13 0>;
0470 assigned-clocks = <&k3_clks 13 3>;
0471 assigned-clock-parents = <&k3_clks 13 11>;
0472 clock-names = "fck";
0473 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
0474
0475 dmas = <&main_pktdma 0xc600 15>,
0476 <&main_pktdma 0xc601 15>,
0477 <&main_pktdma 0xc602 15>,
0478 <&main_pktdma 0xc603 15>,
0479 <&main_pktdma 0xc604 15>,
0480 <&main_pktdma 0xc605 15>,
0481 <&main_pktdma 0xc606 15>,
0482 <&main_pktdma 0xc607 15>,
0483 <&main_pktdma 0x4600 15>;
0484 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
0485 "tx7", "rx";
0486
0487 ethernet-ports {
0488 #address-cells = <1>;
0489 #size-cells = <0>;
0490
0491 cpsw_port1: port@1 {
0492 reg = <1>;
0493 ti,mac-only;
0494 label = "port1";
0495 phys = <&phy_gmii_sel 1>;
0496 mac-address = [00 00 00 00 00 00];
0497 ti,syscon-efuse = <&wkup_conf 0x200>;
0498 };
0499
0500 cpsw_port2: port@2 {
0501 reg = <2>;
0502 ti,mac-only;
0503 label = "port2";
0504 phys = <&phy_gmii_sel 2>;
0505 mac-address = [00 00 00 00 00 00];
0506 };
0507 };
0508
0509 cpsw3g_mdio: mdio@f00 {
0510 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
0511 reg = <0x00 0xf00 0x00 0x100>;
0512 #address-cells = <1>;
0513 #size-cells = <0>;
0514 clocks = <&k3_clks 13 0>;
0515 clock-names = "fck";
0516 bus_freq = <1000000>;
0517 };
0518
0519 cpts@3d000 {
0520 compatible = "ti,j721e-cpts";
0521 reg = <0x00 0x3d000 0x00 0x400>;
0522 clocks = <&k3_clks 13 3>;
0523 clock-names = "cpts";
0524 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0525 interrupt-names = "cpts";
0526 ti,cpts-ext-ts-inputs = <4>;
0527 ti,cpts-periodic-outputs = <2>;
0528 };
0529 };
0530
0531 hwspinlock: spinlock@2a000000 {
0532 compatible = "ti,am64-hwspinlock";
0533 reg = <0x00 0x2a000000 0x00 0x1000>;
0534 #hwlock-cells = <1>;
0535 };
0536
0537 mailbox0_cluster0: mailbox@29000000 {
0538 compatible = "ti,am64-mailbox";
0539 reg = <0x00 0x29000000 0x00 0x200>;
0540 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0541 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0542 #mbox-cells = <1>;
0543 ti,mbox-num-users = <4>;
0544 ti,mbox-num-fifos = <16>;
0545 };
0546
0547 ecap0: pwm@23100000 {
0548 compatible = "ti,am3352-ecap";
0549 #pwm-cells = <3>;
0550 reg = <0x00 0x23100000 0x00 0x100>;
0551 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
0552 clocks = <&k3_clks 51 0>;
0553 clock-names = "fck";
0554 };
0555
0556 ecap1: pwm@23110000 {
0557 compatible = "ti,am3352-ecap";
0558 #pwm-cells = <3>;
0559 reg = <0x00 0x23110000 0x00 0x100>;
0560 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
0561 clocks = <&k3_clks 52 0>;
0562 clock-names = "fck";
0563 };
0564
0565 ecap2: pwm@23120000 {
0566 compatible = "ti,am3352-ecap";
0567 #pwm-cells = <3>;
0568 reg = <0x00 0x23120000 0x00 0x100>;
0569 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
0570 clocks = <&k3_clks 53 0>;
0571 clock-names = "fck";
0572 };
0573
0574 main_mcan0: can@20701000 {
0575 compatible = "bosch,m_can";
0576 reg = <0x00 0x20701000 0x00 0x200>,
0577 <0x00 0x20708000 0x00 0x8000>;
0578 reg-names = "m_can", "message_ram";
0579 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
0580 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
0581 clock-names = "hclk", "cclk";
0582 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0583 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0584 interrupt-names = "int0", "int1";
0585 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0586 };
0587 };
