0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Tesla Full Self-Driving SoC device tree source
0004 *
0005 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
0006 * https://www.samsung.com
0007 * Copyright (c) 2017-2022 Tesla, Inc.
0008 * https://www.tesla.com
0009 */
0010
0011 #include <dt-bindings/clock/fsd-clk.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013
0014 / {
0015 compatible = "tesla,fsd";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 i2c0 = &hsi2c_0;
0022 i2c1 = &hsi2c_1;
0023 i2c2 = &hsi2c_2;
0024 i2c3 = &hsi2c_3;
0025 i2c4 = &hsi2c_4;
0026 i2c5 = &hsi2c_5;
0027 i2c6 = &hsi2c_6;
0028 i2c7 = &hsi2c_7;
0029 pinctrl0 = &pinctrl_fsys0;
0030 pinctrl1 = &pinctrl_peric;
0031 pinctrl2 = &pinctrl_pmu;
0032 spi0 = &spi_0;
0033 spi1 = &spi_1;
0034 spi2 = &spi_2;
0035 };
0036
0037 cpus {
0038 #address-cells = <2>;
0039 #size-cells = <0>;
0040
0041 cpu-map {
0042 cluster0 {
0043 core0 {
0044 cpu = <&cpucl0_0>;
0045 };
0046 core1 {
0047 cpu = <&cpucl0_1>;
0048 };
0049 core2 {
0050 cpu = <&cpucl0_2>;
0051 };
0052 core3 {
0053 cpu = <&cpucl0_3>;
0054 };
0055 };
0056
0057 cluster1 {
0058 core0 {
0059 cpu = <&cpucl1_0>;
0060 };
0061 core1 {
0062 cpu = <&cpucl1_1>;
0063 };
0064 core2 {
0065 cpu = <&cpucl1_2>;
0066 };
0067 core3 {
0068 cpu = <&cpucl1_3>;
0069 };
0070 };
0071
0072 cluster2 {
0073 core0 {
0074 cpu = <&cpucl2_0>;
0075 };
0076 core1 {
0077 cpu = <&cpucl2_1>;
0078 };
0079 core2 {
0080 cpu = <&cpucl2_2>;
0081 };
0082 core3 {
0083 cpu = <&cpucl2_3>;
0084 };
0085 };
0086 };
0087
0088 /* Cluster 0 */
0089 cpucl0_0: cpu@0 {
0090 device_type = "cpu";
0091 compatible = "arm,cortex-a72";
0092 reg = <0x0 0x000>;
0093 enable-method = "psci";
0094 clock-frequency = <2400000000>;
0095 cpu-idle-states = <&CPU_SLEEP>;
0096 i-cache-size = <0xc000>;
0097 i-cache-line-size = <64>;
0098 i-cache-sets = <256>;
0099 d-cache-size = <0x8000>;
0100 d-cache-line-size = <64>;
0101 d-cache-sets = <256>;
0102 next-level-cache = <&cpucl_l2>;
0103 };
0104
0105 cpucl0_1: cpu@1 {
0106 device_type = "cpu";
0107 compatible = "arm,cortex-a72";
0108 reg = <0x0 0x001>;
0109 enable-method = "psci";
0110 clock-frequency = <2400000000>;
0111 cpu-idle-states = <&CPU_SLEEP>;
0112 i-cache-size = <0xc000>;
0113 i-cache-line-size = <64>;
0114 i-cache-sets = <256>;
0115 d-cache-size = <0x8000>;
0116 d-cache-line-size = <64>;
0117 d-cache-sets = <256>;
0118 next-level-cache = <&cpucl_l2>;
0119 };
0120
0121 cpucl0_2: cpu@2 {
0122 device_type = "cpu";
0123 compatible = "arm,cortex-a72";
0124 reg = <0x0 0x002>;
0125 enable-method = "psci";
0126 clock-frequency = <2400000000>;
0127 cpu-idle-states = <&CPU_SLEEP>;
0128 i-cache-size = <0xc000>;
0129 i-cache-line-size = <64>;
0130 i-cache-sets = <256>;
0131 d-cache-size = <0x8000>;
0132 d-cache-line-size = <64>;
0133 d-cache-sets = <256>;
0134 next-level-cache = <&cpucl_l2>;
0135 };
0136
0137 cpucl0_3: cpu@3 {
0138 device_type = "cpu";
0139 compatible = "arm,cortex-a72";
0140 reg = <0x0 0x003>;
0141 enable-method = "psci";
0142 cpu-idle-states = <&CPU_SLEEP>;
0143 i-cache-size = <0xc000>;
0144 i-cache-line-size = <64>;
0145 i-cache-sets = <256>;
0146 d-cache-size = <0x8000>;
0147 d-cache-line-size = <64>;
0148 d-cache-sets = <256>;
0149 next-level-cache = <&cpucl_l2>;
0150 };
0151
0152 /* Cluster 1 */
0153 cpucl1_0: cpu@100 {
0154 device_type = "cpu";
0155 compatible = "arm,cortex-a72";
0156 reg = <0x0 0x100>;
0157 enable-method = "psci";
0158 clock-frequency = <2400000000>;
0159 cpu-idle-states = <&CPU_SLEEP>;
0160 i-cache-size = <0xc000>;
0161 i-cache-line-size = <64>;
0162 i-cache-sets = <256>;
0163 d-cache-size = <0x8000>;
0164 d-cache-line-size = <64>;
0165 d-cache-sets = <256>;
0166 next-level-cache = <&cpucl_l2>;
0167 };
0168
0169 cpucl1_1: cpu@101 {
0170 device_type = "cpu";
0171 compatible = "arm,cortex-a72";
0172 reg = <0x0 0x101>;
0173 enable-method = "psci";
0174 clock-frequency = <2400000000>;
0175 cpu-idle-states = <&CPU_SLEEP>;
0176 i-cache-size = <0xc000>;
0177 i-cache-line-size = <64>;
0178 i-cache-sets = <256>;
0179 d-cache-size = <0x8000>;
0180 d-cache-line-size = <64>;
0181 d-cache-sets = <256>;
0182 next-level-cache = <&cpucl_l2>;
0183 };
0184
0185 cpucl1_2: cpu@102 {
0186 device_type = "cpu";
0187 compatible = "arm,cortex-a72";
0188 reg = <0x0 0x102>;
0189 enable-method = "psci";
0190 clock-frequency = <2400000000>;
0191 cpu-idle-states = <&CPU_SLEEP>;
0192 i-cache-size = <0xc000>;
0193 i-cache-line-size = <64>;
0194 i-cache-sets = <256>;
0195 d-cache-size = <0x8000>;
0196 d-cache-line-size = <64>;
0197 d-cache-sets = <256>;
0198 next-level-cache = <&cpucl_l2>;
0199 };
0200
0201 cpucl1_3: cpu@103 {
0202 device_type = "cpu";
0203 compatible = "arm,cortex-a72";
0204 reg = <0x0 0x103>;
0205 enable-method = "psci";
0206 clock-frequency = <2400000000>;
0207 cpu-idle-states = <&CPU_SLEEP>;
0208 i-cache-size = <0xc000>;
0209 i-cache-line-size = <64>;
0210 i-cache-sets = <256>;
0211 d-cache-size = <0x8000>;
0212 d-cache-line-size = <64>;
0213 d-cache-sets = <256>;
0214 next-level-cache = <&cpucl_l2>;
0215 };
0216
0217 /* Cluster 2 */
0218 cpucl2_0: cpu@200 {
0219 device_type = "cpu";
0220 compatible = "arm,cortex-a72";
0221 reg = <0x0 0x200>;
0222 enable-method = "psci";
0223 clock-frequency = <2400000000>;
0224 cpu-idle-states = <&CPU_SLEEP>;
0225 i-cache-size = <0xc000>;
0226 i-cache-line-size = <64>;
0227 i-cache-sets = <256>;
0228 d-cache-size = <0x8000>;
0229 d-cache-line-size = <64>;
0230 d-cache-sets = <256>;
0231 next-level-cache = <&cpucl_l2>;
0232 };
0233
0234 cpucl2_1: cpu@201 {
0235 device_type = "cpu";
0236 compatible = "arm,cortex-a72";
0237 reg = <0x0 0x201>;
0238 enable-method = "psci";
0239 clock-frequency = <2400000000>;
0240 cpu-idle-states = <&CPU_SLEEP>;
0241 i-cache-size = <0xc000>;
0242 i-cache-line-size = <64>;
0243 i-cache-sets = <256>;
0244 d-cache-size = <0x8000>;
0245 d-cache-line-size = <64>;
0246 d-cache-sets = <256>;
0247 next-level-cache = <&cpucl_l2>;
0248 };
0249
0250 cpucl2_2: cpu@202 {
0251 device_type = "cpu";
0252 compatible = "arm,cortex-a72";
0253 reg = <0x0 0x202>;
0254 enable-method = "psci";
0255 clock-frequency = <2400000000>;
0256 cpu-idle-states = <&CPU_SLEEP>;
0257 i-cache-size = <0xc000>;
0258 i-cache-line-size = <64>;
0259 i-cache-sets = <256>;
0260 d-cache-size = <0x8000>;
0261 d-cache-line-size = <64>;
0262 d-cache-sets = <256>;
0263 next-level-cache = <&cpucl_l2>;
0264 };
0265
0266 cpucl2_3: cpu@203 {
0267 device_type = "cpu";
0268 compatible = "arm,cortex-a72";
0269 reg = <0x0 0x203>;
0270 enable-method = "psci";
0271 clock-frequency = <2400000000>;
0272 cpu-idle-states = <&CPU_SLEEP>;
0273 i-cache-size = <0xc000>;
0274 i-cache-line-size = <64>;
0275 i-cache-sets = <256>;
0276 d-cache-size = <0x8000>;
0277 d-cache-line-size = <64>;
0278 d-cache-sets = <256>;
0279 next-level-cache = <&cpucl_l2>;
0280 };
0281
0282 cpucl_l2: l2-cache0 {
0283 compatible = "cache";
0284 cache-size = <0x400000>;
0285 cache-line-size = <64>;
0286 cache-sets = <4096>;
0287 };
0288
0289 idle-states {
0290 entry-method = "psci";
0291
0292 CPU_SLEEP: cpu-sleep {
0293 idle-state-name = "c2";
0294 compatible = "arm,idle-state";
0295 local-timer-stop;
0296 arm,psci-suspend-param = <0x0010000>;
0297 entry-latency-us = <30>;
0298 exit-latency-us = <75>;
0299 min-residency-us = <300>;
0300 };
0301 };
0302 };
0303
0304 arm-pmu {
0305 compatible = "arm,armv8-pmuv3";
0306 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
0307 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
0309 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
0310 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
0311 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
0312 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
0313 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
0314 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
0315 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
0316 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
0317 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
0318 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
0319 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
0320 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
0321 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
0322 };
0323
0324 psci {
0325 compatible = "arm,psci-1.0";
0326 method = "smc";
0327 };
0328
0329 timer {
0330 compatible = "arm,armv8-timer";
0331 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0332 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0333 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0334 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0335 };
0336
0337 fin_pll: clock {
0338 compatible = "fixed-clock";
0339 clock-output-names = "fin_pll";
0340 #clock-cells = <0>;
0341 };
0342
0343 soc: soc@0 {
0344 compatible = "simple-bus";
0345 #address-cells = <2>;
0346 #size-cells = <2>;
0347 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
0348 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
0349
0350 gic: interrupt-controller@10400000 {
0351 compatible = "arm,gic-v3";
0352 #interrupt-cells = <3>;
0353 interrupt-controller;
0354 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
0355 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
0356 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0357 };
0358
0359 smmu_imem: iommu@10200000 {
0360 compatible = "arm,mmu-500";
0361 reg = <0x0 0x10200000 0x0 0x10000>;
0362 #iommu-cells = <2>;
0363 #global-interrupts = <7>;
0364 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
0365 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
0366 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
0367 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
0368 /* Performance counter interrupts */
0369 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
0370 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
0371 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
0372 /* Per context non-secure context interrupts, 0-3 interrupts */
0373 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
0374 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
0375 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
0376 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
0377 };
0378
0379 smmu_isp: iommu@12100000 {
0380 compatible = "arm,mmu-500";
0381 reg = <0x0 0x12100000 0x0 0x10000>;
0382 #iommu-cells = <2>;
0383 #global-interrupts = <11>;
0384 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
0385 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
0386 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
0387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
0388 /* Performance counter interrupts */
0389 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
0390 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
0391 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
0392 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
0393 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
0394 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
0395 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
0396 /* Per context non-secure context interrupts, 0-7 interrupts */
0397 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
0398 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
0399 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
0400 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
0401 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
0402 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
0403 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
0404 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
0405 };
0406
0407 smmu_peric: iommu@14900000 {
0408 compatible = "arm,mmu-500";
0409 reg = <0x0 0x14900000 0x0 0x10000>;
0410 #iommu-cells = <2>;
0411 #global-interrupts = <5>;
0412 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
0413 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
0414 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
0415 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
0416 /* Performance counter interrupts */
0417 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
0418 /* Per context non-secure context interrupts, 0-1 interrupts */
0419 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
0420 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
0421 };
0422
0423 smmu_fsys0: iommu@15450000 {
0424 compatible = "arm,mmu-500";
0425 reg = <0x0 0x15450000 0x0 0x10000>;
0426 #iommu-cells = <2>;
0427 #global-interrupts = <5>;
0428 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
0429 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
0430 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
0431 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
0432 /* Performance counter interrupts */
0433 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
0434 /* Per context non-secure context interrupts, 0-1 interrupts */
0435 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
0436 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
0437 };
0438
0439 clock_imem: clock-controller@10010000 {
0440 compatible = "tesla,fsd-clock-imem";
0441 reg = <0x0 0x10010000 0x0 0x3000>;
0442 #clock-cells = <1>;
0443 clocks = <&fin_pll>,
0444 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
0445 <&clock_cmu DOUT_CMU_IMEM_ACLK>,
0446 <&clock_cmu DOUT_CMU_IMEM_DMACLK>;
0447 clock-names = "fin_pll",
0448 "dout_cmu_imem_tcuclk",
0449 "dout_cmu_imem_aclk",
0450 "dout_cmu_imem_dmaclk";
0451 };
0452
0453 clock_cmu: clock-controller@11c10000 {
0454 compatible = "tesla,fsd-clock-cmu";
0455 reg = <0x0 0x11c10000 0x0 0x3000>;
0456 #clock-cells = <1>;
0457 clocks = <&fin_pll>;
0458 clock-names = "fin_pll";
0459 };
0460
0461 clock_csi: clock-controller@12610000 {
0462 compatible = "tesla,fsd-clock-cam_csi";
0463 reg = <0x0 0x12610000 0x0 0x3000>;
0464 #clock-cells = <1>;
0465 clocks = <&fin_pll>;
0466 clock-names = "fin_pll";
0467 };
0468
0469 clock_mfc: clock-controller@12810000 {
0470 compatible = "tesla,fsd-clock-mfc";
0471 reg = <0x0 0x12810000 0x0 0x3000>;
0472 #clock-cells = <1>;
0473 clocks = <&fin_pll>;
0474 clock-names = "fin_pll";
0475 };
0476
0477 clock_peric: clock-controller@14010000 {
0478 compatible = "tesla,fsd-clock-peric";
0479 reg = <0x0 0x14010000 0x0 0x3000>;
0480 #clock-cells = <1>;
0481 clocks = <&fin_pll>,
0482 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
0483 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
0484 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
0485 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
0486 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
0487 clock-names = "fin_pll",
0488 "dout_cmu_pll_shared0_div4",
0489 "dout_cmu_peric_shared1div36",
0490 "dout_cmu_peric_shared0div3_tbuclk",
0491 "dout_cmu_peric_shared0div20",
0492 "dout_cmu_peric_shared1div4_dmaclk";
0493 };
0494
0495 clock_fsys0: clock-controller@15010000 {
0496 compatible = "tesla,fsd-clock-fsys0";
0497 reg = <0x0 0x15010000 0x0 0x3000>;
0498 #clock-cells = <1>;
0499 clocks = <&fin_pll>,
0500 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
0501 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
0502 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
0503 clock-names = "fin_pll",
0504 "dout_cmu_pll_shared0_div6",
0505 "dout_cmu_fsys0_shared1div4",
0506 "dout_cmu_fsys0_shared0div4";
0507 };
0508
0509 clock_fsys1: clock-controller@16810000 {
0510 compatible = "tesla,fsd-clock-fsys1";
0511 reg = <0x0 0x16810000 0x0 0x3000>;
0512 #clock-cells = <1>;
0513 clocks = <&fin_pll>,
0514 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
0515 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
0516 clock-names = "fin_pll",
0517 "dout_cmu_fsys1_shared0div8",
0518 "dout_cmu_fsys1_shared0div4";
0519 };
0520
0521 mdma0: dma-controller@10100000 {
0522 compatible = "arm,pl330", "arm,primecell";
0523 reg = <0x0 0x10100000 0x0 0x1000>;
0524 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
0525 #dma-cells = <1>;
0526 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
0527 clock-names = "apb_pclk";
0528 iommus = <&smmu_imem 0x800 0x0>;
0529 };
0530
0531 mdma1: dma-controller@10110000 {
0532 compatible = "arm,pl330", "arm,primecell";
0533 reg = <0x0 0x10110000 0x0 0x1000>;
0534 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
0535 #dma-cells = <1>;
0536 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
0537 clock-names = "apb_pclk";
0538 iommus = <&smmu_imem 0x801 0x0>;
0539 };
0540
0541 pdma0: dma-controller@14280000 {
0542 compatible = "arm,pl330", "arm,primecell";
0543 reg = <0x0 0x14280000 0x0 0x1000>;
0544 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0545 #dma-cells = <1>;
0546 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
0547 clock-names = "apb_pclk";
0548 iommus = <&smmu_peric 0x2 0x0>;
0549 };
0550
0551 pdma1: dma-controller@14290000 {
0552 compatible = "arm,pl330", "arm,primecell";
0553 reg = <0x0 0x14290000 0x0 0x1000>;
0554 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
0555 #dma-cells = <1>;
0556 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
0557 clock-names = "apb_pclk";
0558 iommus = <&smmu_peric 0x1 0x0>;
0559 };
0560
0561 serial_0: serial@14180000 {
0562 compatible = "samsung,exynos4210-uart";
0563 reg = <0x0 0x14180000 0x0 0x100>;
0564 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
0565 dmas = <&pdma1 1>, <&pdma1 0>;
0566 dma-names = "rx", "tx";
0567 clocks = <&clock_peric PERIC_PCLK_UART0>,
0568 <&clock_peric PERIC_SCLK_UART0>;
0569 clock-names = "uart", "clk_uart_baud0";
0570 status = "disabled";
0571 };
0572
0573 serial_1: serial@14190000 {
0574 compatible = "samsung,exynos4210-uart";
0575 reg = <0x0 0x14190000 0x0 0x100>;
0576 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0577 dmas = <&pdma1 3>, <&pdma1 2>;
0578 dma-names = "rx", "tx";
0579 clocks = <&clock_peric PERIC_PCLK_UART1>,
0580 <&clock_peric PERIC_SCLK_UART1>;
0581 clock-names = "uart", "clk_uart_baud0";
0582 status = "disabled";
0583 };
0584
0585 pmu_system_controller: system-controller@11400000 {
0586 compatible = "samsung,exynos7-pmu", "syscon";
0587 reg = <0x0 0x11400000 0x0 0x5000>;
0588 };
0589
0590 watchdog_0: watchdog@100a0000 {
0591 compatible = "samsung,exynos7-wdt";
0592 reg = <0x0 0x100a0000 0x0 0x100>;
0593 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
0594 samsung,syscon-phandle = <&pmu_system_controller>;
0595 clocks = <&fin_pll>;
0596 clock-names = "watchdog";
0597 };
0598
0599 watchdog_1: watchdog@100b0000 {
0600 compatible = "samsung,exynos7-wdt";
0601 reg = <0x0 0x100b0000 0x0 0x100>;
0602 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
0603 samsung,syscon-phandle = <&pmu_system_controller>;
0604 clocks = <&fin_pll>;
0605 clock-names = "watchdog";
0606 };
0607
0608 watchdog_2: watchdog@100c0000 {
0609 compatible = "samsung,exynos7-wdt";
0610 reg = <0x0 0x100c0000 0x0 0x100>;
0611 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
0612 samsung,syscon-phandle = <&pmu_system_controller>;
0613 clocks = <&fin_pll>;
0614 clock-names = "watchdog";
0615 };
0616
0617 pwm_0: pwm@14100000 {
0618 compatible = "samsung,exynos4210-pwm";
0619 reg = <0x0 0x14100000 0x0 0x100>;
0620 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
0621 #pwm-cells = <3>;
0622 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
0623 clock-names = "timers";
0624 status = "disabled";
0625 };
0626
0627 pwm_1: pwm@14110000 {
0628 compatible = "samsung,exynos4210-pwm";
0629 reg = <0x0 0x14110000 0x0 0x100>;
0630 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
0631 #pwm-cells = <3>;
0632 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
0633 clock-names = "timers";
0634 status = "disabled";
0635 };
0636
0637 hsi2c_0: i2c@14200000 {
0638 compatible = "samsung,exynos7-hsi2c";
0639 reg = <0x0 0x14200000 0x0 0x1000>;
0640 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0641 #address-cells = <1>;
0642 #size-cells = <0>;
0643 pinctrl-names = "default";
0644 pinctrl-0 = <&hs_i2c0_bus>;
0645 clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
0646 clock-names = "hsi2c";
0647 status = "disabled";
0648 };
0649
0650 hsi2c_1: i2c@14210000 {
0651 compatible = "samsung,exynos7-hsi2c";
0652 reg = <0x0 0x14210000 0x0 0x1000>;
0653 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0654 #address-cells = <1>;
0655 #size-cells = <0>;
0656 pinctrl-names = "default";
0657 pinctrl-0 = <&hs_i2c1_bus>;
0658 clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
0659 clock-names = "hsi2c";
0660 status = "disabled";
0661 };
0662
0663 hsi2c_2: i2c@14220000 {
0664 compatible = "samsung,exynos7-hsi2c";
0665 reg = <0x0 0x14220000 0x0 0x1000>;
0666 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
0667 #address-cells = <1>;
0668 #size-cells = <0>;
0669 pinctrl-names = "default";
0670 pinctrl-0 = <&hs_i2c2_bus>;
0671 clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
0672 clock-names = "hsi2c";
0673 status = "disabled";
0674 };
0675
0676 hsi2c_3: i2c@14230000 {
0677 compatible = "samsung,exynos7-hsi2c";
0678 reg = <0x0 0x14230000 0x0 0x1000>;
0679 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0680 #address-cells = <1>;
0681 #size-cells = <0>;
0682 pinctrl-names = "default";
0683 pinctrl-0 = <&hs_i2c3_bus>;
0684 clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
0685 clock-names = "hsi2c";
0686 status = "disabled";
0687 };
0688
0689 hsi2c_4: i2c@14240000 {
0690 compatible = "samsung,exynos7-hsi2c";
0691 reg = <0x0 0x14240000 0x0 0x1000>;
0692 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0693 #address-cells = <1>;
0694 #size-cells = <0>;
0695 pinctrl-names = "default";
0696 pinctrl-0 = <&hs_i2c4_bus>;
0697 clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
0698 clock-names = "hsi2c";
0699 status = "disabled";
0700 };
0701
0702 hsi2c_5: i2c@14250000 {
0703 compatible = "samsung,exynos7-hsi2c";
0704 reg = <0x0 0x14250000 0x0 0x1000>;
0705 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0706 #address-cells = <1>;
0707 #size-cells = <0>;
0708 pinctrl-names = "default";
0709 pinctrl-0 = <&hs_i2c5_bus>;
0710 clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
0711 clock-names = "hsi2c";
0712 status = "disabled";
0713 };
0714
0715 hsi2c_6: i2c@14260000 {
0716 compatible = "samsung,exynos7-hsi2c";
0717 reg = <0x0 0x14260000 0x0 0x1000>;
0718 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0719 #address-cells = <1>;
0720 #size-cells = <0>;
0721 pinctrl-names = "default";
0722 pinctrl-0 = <&hs_i2c6_bus>;
0723 clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
0724 clock-names = "hsi2c";
0725 status = "disabled";
0726 };
0727
0728 hsi2c_7: i2c@14270000 {
0729 compatible = "samsung,exynos7-hsi2c";
0730 reg = <0x0 0x14270000 0x0 0x1000>;
0731 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0732 #address-cells = <1>;
0733 #size-cells = <0>;
0734 pinctrl-names = "default";
0735 pinctrl-0 = <&hs_i2c7_bus>;
0736 clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
0737 clock-names = "hsi2c";
0738 status = "disabled";
0739 };
0740
0741 pinctrl_pmu: pinctrl@114f0000 {
0742 compatible = "tesla,fsd-pinctrl";
0743 reg = <0x0 0x114f0000 0x0 0x1000>;
0744 };
0745
0746 pinctrl_peric: pinctrl@141f0000 {
0747 compatible = "tesla,fsd-pinctrl";
0748 reg = <0x0 0x141f0000 0x0 0x1000>;
0749 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0750 };
0751
0752 pinctrl_fsys0: pinctrl@15020000 {
0753 compatible = "tesla,fsd-pinctrl";
0754 reg = <0x0 0x15020000 0x0 0x1000>;
0755 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0756 };
0757
0758 spi_0: spi@14140000 {
0759 compatible = "tesla,fsd-spi";
0760 reg = <0x0 0x14140000 0x0 0x100>;
0761 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0762 dmas = <&pdma1 4>, <&pdma1 5>;
0763 dma-names = "tx", "rx";
0764 #address-cells = <1>;
0765 #size-cells = <0>;
0766 clocks = <&clock_peric PERIC_PCLK_SPI0>,
0767 <&clock_peric PERIC_SCLK_SPI0>;
0768 clock-names = "spi", "spi_busclk0";
0769 samsung,spi-src-clk = <0>;
0770 pinctrl-names = "default";
0771 pinctrl-0 = <&spi0_bus>;
0772 num-cs = <1>;
0773 status = "disabled";
0774 };
0775
0776 spi_1: spi@14150000 {
0777 compatible = "tesla,fsd-spi";
0778 reg = <0x0 0x14150000 0x0 0x100>;
0779 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0780 dmas = <&pdma1 6>, <&pdma1 7>;
0781 dma-names = "tx", "rx";
0782 #address-cells = <1>;
0783 #size-cells = <0>;
0784 clocks = <&clock_peric PERIC_PCLK_SPI1>,
0785 <&clock_peric PERIC_SCLK_SPI1>;
0786 clock-names = "spi", "spi_busclk0";
0787 samsung,spi-src-clk = <0>;
0788 pinctrl-names = "default";
0789 pinctrl-0 = <&spi1_bus>;
0790 num-cs = <1>;
0791 status = "disabled";
0792 };
0793
0794 spi_2: spi@14160000 {
0795 compatible = "tesla,fsd-spi";
0796 reg = <0x0 0x14160000 0x0 0x100>;
0797 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0798 dmas = <&pdma1 8>, <&pdma1 9>;
0799 dma-names = "tx", "rx";
0800 #address-cells = <1>;
0801 #size-cells = <0>;
0802 clocks = <&clock_peric PERIC_PCLK_SPI2>,
0803 <&clock_peric PERIC_SCLK_SPI2>;
0804 clock-names = "spi", "spi_busclk0";
0805 samsung,spi-src-clk = <0>;
0806 pinctrl-names = "default";
0807 pinctrl-0 = <&spi2_bus>;
0808 num-cs = <1>;
0809 status = "disabled";
0810 };
0811
0812 timer@10040000 {
0813 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
0814 reg = <0x0 0x10040000 0x0 0x800>;
0815 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
0816 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
0817 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
0818 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
0819 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
0820 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
0821 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
0822 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
0823 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
0824 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
0825 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
0826 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
0827 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
0828 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
0829 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
0830 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
0831 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
0832 clock-names = "fin_pll", "mct";
0833 };
0834
0835 ufs: ufs@15120000 {
0836 compatible = "tesla,fsd-ufs";
0837 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
0838 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
0839 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
0840 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
0841 reg-names = "hci", "vs_hci", "unipro", "ufsp";
0842 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0843 clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
0844 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
0845 clock-names = "core_clk", "sclk_unipro_main";
0846 freq-table-hz = <0 0>, <0 0>;
0847 pinctrl-names = "default";
0848 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
0849 phys = <&ufs_phy>;
0850 phy-names = "ufs-phy";
0851 status = "disabled";
0852 };
0853
0854 ufs_phy: ufs-phy@15124000 {
0855 compatible = "tesla,fsd-ufs-phy";
0856 reg = <0x0 0x15124000 0x0 0x800>;
0857 reg-names = "phy-pma";
0858 samsung,pmu-syscon = <&pmu_system_controller>;
0859 #phy-cells = <0>;
0860 clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
0861 clock-names = "ref_clk";
0862 };
0863 };
0864 };
0865
0866 #include "fsd-pinctrl.dtsi"
