0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Unisoc Sharkl3 platform DTS file
0004 *
0005 * Copyright (C) 2019, Unisoc Inc.
0006 */
0007
0008 / {
0009 interrupt-parent = <&gic>;
0010 #address-cells = <2>;
0011 #size-cells = <2>;
0012
0013 soc: soc {
0014 compatible = "simple-bus";
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017 ranges;
0018
0019 ap_ahb_regs: syscon@20e00000 {
0020 compatible = "sprd,sc9863a-glbregs", "syscon",
0021 "simple-mfd";
0022 reg = <0 0x20e00000 0 0x4000>;
0023 #address-cells = <1>;
0024 #size-cells = <1>;
0025 ranges = <0 0 0x20e00000 0x4000>;
0026
0027 apahb_gate: apahb-gate {
0028 compatible = "sprd,sc9863a-apahb-gate";
0029 reg = <0x0 0x1020>;
0030 #clock-cells = <1>;
0031 };
0032 };
0033
0034 pmu_regs: syscon@402b0000 {
0035 compatible = "sprd,sc9863a-glbregs", "syscon",
0036 "simple-mfd";
0037 reg = <0 0x402b0000 0 0x4000>;
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040 ranges = <0 0 0x402b0000 0x4000>;
0041
0042 pmu_gate: pmu-gate {
0043 compatible = "sprd,sc9863a-pmu-gate";
0044 reg = <0 0x1200>;
0045 clocks = <&ext_26m>;
0046 clock-names = "ext-26m";
0047 #clock-cells = <1>;
0048 };
0049 };
0050
0051 aon_apb_regs: syscon@402e0000 {
0052 compatible = "sprd,sc9863a-glbregs", "syscon",
0053 "simple-mfd";
0054 reg = <0 0x402e0000 0 0x4000>;
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 ranges = <0 0 0x402e0000 0x4000>;
0058
0059 aonapb_gate: aonapb-gate {
0060 compatible = "sprd,sc9863a-aonapb-gate";
0061 reg = <0 0x1100>;
0062 #clock-cells = <1>;
0063 };
0064 };
0065
0066 anlg_phy_g2_regs: syscon@40353000 {
0067 compatible = "sprd,sc9863a-glbregs", "syscon",
0068 "simple-mfd";
0069 reg = <0 0x40353000 0 0x3000>;
0070 #address-cells = <1>;
0071 #size-cells = <1>;
0072 ranges = <0 0 0x40353000 0x3000>;
0073
0074 pll: pll {
0075 compatible = "sprd,sc9863a-pll";
0076 reg = <0 0x100>;
0077 clocks = <&ext_26m>;
0078 clock-names = "ext-26m";
0079 #clock-cells = <1>;
0080 };
0081 };
0082
0083 anlg_phy_g4_regs: syscon@40359000 {
0084 compatible = "sprd,sc9863a-glbregs", "syscon",
0085 "simple-mfd";
0086 reg = <0 0x40359000 0 0x3000>;
0087 #address-cells = <1>;
0088 #size-cells = <1>;
0089 ranges = <0 0 0x40359000 0x3000>;
0090
0091 mpll: mpll {
0092 compatible = "sprd,sc9863a-mpll";
0093 reg = <0 0x100>;
0094 #clock-cells = <1>;
0095 };
0096 };
0097
0098 anlg_phy_g5_regs: syscon@4035c000 {
0099 compatible = "sprd,sc9863a-glbregs", "syscon",
0100 "simple-mfd";
0101 reg = <0 0x4035c000 0 0x3000>;
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 ranges = <0 0 0x4035c000 0x3000>;
0105
0106 rpll: rpll {
0107 compatible = "sprd,sc9863a-rpll";
0108 reg = <0 0x100>;
0109 clocks = <&ext_26m>;
0110 clock-names = "ext-26m";
0111 #clock-cells = <1>;
0112 };
0113 };
0114
0115 anlg_phy_g7_regs: syscon@40363000 {
0116 compatible = "sprd,sc9863a-glbregs", "syscon",
0117 "simple-mfd";
0118 reg = <0 0x40363000 0 0x3000>;
0119 #address-cells = <1>;
0120 #size-cells = <1>;
0121 ranges = <0 0 0x40363000 0x3000>;
0122
0123 dpll: dpll {
0124 compatible = "sprd,sc9863a-dpll";
0125 reg = <0 0x100>;
0126 #clock-cells = <1>;
0127 };
0128 };
0129
0130 mm_ahb_regs: syscon@60800000 {
0131 compatible = "sprd,sc9863a-glbregs", "syscon",
0132 "simple-mfd";
0133 reg = <0 0x60800000 0 0x1000>;
0134 #address-cells = <1>;
0135 #size-cells = <1>;
0136 ranges = <0 0 0x60800000 0x3000>;
0137
0138 mm_gate: mm-gate {
0139 compatible = "sprd,sc9863a-mm-gate";
0140 reg = <0 0x1100>;
0141 #clock-cells = <1>;
0142 };
0143 };
0144
0145 ap_apb_regs: syscon@71300000 {
0146 compatible = "sprd,sc9863a-glbregs", "syscon",
0147 "simple-mfd";
0148 reg = <0 0x71300000 0 0x4000>;
0149 #address-cells = <1>;
0150 #size-cells = <1>;
0151 ranges = <0 0 0x71300000 0x4000>;
0152
0153 apapb_gate: apapb-gate {
0154 compatible = "sprd,sc9863a-apapb-gate";
0155 reg = <0 0x1000>;
0156 clocks = <&ext_26m>;
0157 clock-names = "ext-26m";
0158 #clock-cells = <1>;
0159 };
0160 };
0161
0162 apb@70000000 {
0163 compatible = "simple-bus";
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166 ranges = <0 0x0 0x70000000 0x10000000>;
0167
0168 uart0: serial@0 {
0169 compatible = "sprd,sc9863a-uart",
0170 "sprd,sc9836-uart";
0171 reg = <0x0 0x100>;
0172 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0173 clocks = <&ext_26m>;
0174 status = "disabled";
0175 };
0176
0177 uart1: serial@100000 {
0178 compatible = "sprd,sc9863a-uart",
0179 "sprd,sc9836-uart";
0180 reg = <0x100000 0x100>;
0181 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0182 clocks = <&ext_26m>;
0183 status = "disabled";
0184 };
0185
0186 uart2: serial@200000 {
0187 compatible = "sprd,sc9863a-uart",
0188 "sprd,sc9836-uart";
0189 reg = <0x200000 0x100>;
0190 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0191 clocks = <&ext_26m>;
0192 status = "disabled";
0193 };
0194
0195 uart3: serial@300000 {
0196 compatible = "sprd,sc9863a-uart",
0197 "sprd,sc9836-uart";
0198 reg = <0x300000 0x100>;
0199 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0200 clocks = <&ext_26m>;
0201 status = "disabled";
0202 };
0203
0204 uart4: serial@400000 {
0205 compatible = "sprd,sc9863a-uart",
0206 "sprd,sc9836-uart";
0207 reg = <0x400000 0x100>;
0208 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0209 clocks = <&ext_26m>;
0210 status = "disabled";
0211 };
0212 };
0213 };
0214
0215 ext_26m: ext-26m {
0216 compatible = "fixed-clock";
0217 #clock-cells = <0>;
0218 clock-frequency = <26000000>;
0219 clock-output-names = "ext-26m";
0220 };
0221
0222 ext_32k: ext-32k {
0223 compatible = "fixed-clock";
0224 #clock-cells = <0>;
0225 clock-frequency = <32768>;
0226 clock-output-names = "ext-32k";
0227 };
0228
0229 ext_4m: ext-4m {
0230 compatible = "fixed-clock";
0231 #clock-cells = <0>;
0232 clock-frequency = <4000000>;
0233 clock-output-names = "ext-4m";
0234 };
0235
0236 rco_100m: rco-100m {
0237 compatible = "fixed-clock";
0238 #clock-cells = <0>;
0239 clock-frequency = <100000000>;
0240 clock-output-names = "rco-100m";
0241 };
0242 };
