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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Unisoc SC9863A SoC DTS file
0004 *
0005 * Copyright (C) 2019, Unisoc Inc.
0006 */
0007
0008 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include "sharkl3.dtsi"
0011
0012 / {
0013 cpus {
0014 #address-cells = <2>;
0015 #size-cells = <0>;
0016
0017 cpu-map {
0018 cluster0 {
0019 core0 {
0020 cpu = <&CPU0>;
0021 };
0022 core1 {
0023 cpu = <&CPU1>;
0024 };
0025 core2 {
0026 cpu = <&CPU2>;
0027 };
0028 core3 {
0029 cpu = <&CPU3>;
0030 };
0031 core4 {
0032 cpu = <&CPU4>;
0033 };
0034 core5 {
0035 cpu = <&CPU5>;
0036 };
0037 core6 {
0038 cpu = <&CPU6>;
0039 };
0040 core7 {
0041 cpu = <&CPU7>;
0042 };
0043 };
0044 };
0045
0046 CPU0: cpu@0 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a55";
0049 reg = <0x0 0x0>;
0050 enable-method = "psci";
0051 cpu-idle-states = <&CORE_PD>;
0052 };
0053
0054 CPU1: cpu@100 {
0055 device_type = "cpu";
0056 compatible = "arm,cortex-a55";
0057 reg = <0x0 0x100>;
0058 enable-method = "psci";
0059 cpu-idle-states = <&CORE_PD>;
0060 };
0061
0062 CPU2: cpu@200 {
0063 device_type = "cpu";
0064 compatible = "arm,cortex-a55";
0065 reg = <0x0 0x200>;
0066 enable-method = "psci";
0067 cpu-idle-states = <&CORE_PD>;
0068 };
0069
0070 CPU3: cpu@300 {
0071 device_type = "cpu";
0072 compatible = "arm,cortex-a55";
0073 reg = <0x0 0x300>;
0074 enable-method = "psci";
0075 cpu-idle-states = <&CORE_PD>;
0076 };
0077
0078 CPU4: cpu@400 {
0079 device_type = "cpu";
0080 compatible = "arm,cortex-a55";
0081 reg = <0x0 0x400>;
0082 enable-method = "psci";
0083 cpu-idle-states = <&CORE_PD>;
0084 };
0085
0086 CPU5: cpu@500 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a55";
0089 reg = <0x0 0x500>;
0090 enable-method = "psci";
0091 cpu-idle-states = <&CORE_PD>;
0092 };
0093
0094 CPU6: cpu@600 {
0095 device_type = "cpu";
0096 compatible = "arm,cortex-a55";
0097 reg = <0x0 0x600>;
0098 enable-method = "psci";
0099 cpu-idle-states = <&CORE_PD>;
0100 };
0101
0102 CPU7: cpu@700 {
0103 device_type = "cpu";
0104 compatible = "arm,cortex-a55";
0105 reg = <0x0 0x700>;
0106 enable-method = "psci";
0107 cpu-idle-states = <&CORE_PD>;
0108 };
0109 };
0110
0111 idle-states {
0112 entry-method = "psci";
0113 CORE_PD: core-pd {
0114 compatible = "arm,idle-state";
0115 entry-latency-us = <4000>;
0116 exit-latency-us = <4000>;
0117 min-residency-us = <10000>;
0118 local-timer-stop;
0119 arm,psci-suspend-param = <0x00010000>;
0120 };
0121 };
0122
0123 psci {
0124 compatible = "arm,psci-0.2";
0125 method = "smc";
0126 };
0127
0128 timer {
0129 compatible = "arm,armv8-timer";
0130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
0131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
0132 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
0133 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
0134 };
0135
0136 pmu {
0137 compatible = "arm,armv8-pmuv3";
0138 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0141 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0142 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0146 };
0147
0148 soc {
0149 gic: interrupt-controller@14000000 {
0150 compatible = "arm,gic-v3";
0151 #interrupt-cells = <3>;
0152 #address-cells = <2>;
0153 #size-cells = <2>;
0154 ranges;
0155 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
0156 #redistributor-regions = <1>;
0157 interrupt-controller;
0158 reg = <0x0 0x14000000 0 0x20000>, /* GICD */
0159 <0x0 0x14040000 0 0x100000>; /* GICR */
0160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0161 };
0162
0163 ap_clk: clock-controller@21500000 {
0164 compatible = "sprd,sc9863a-ap-clk";
0165 reg = <0 0x21500000 0 0x1000>;
0166 clocks = <&ext_32k>, <&ext_26m>;
0167 clock-names = "ext-32k", "ext-26m";
0168 #clock-cells = <1>;
0169 };
0170
0171 aon_clk: clock-controller@402d0000 {
0172 compatible = "sprd,sc9863a-aon-clk";
0173 reg = <0 0x402d0000 0 0x1000>;
0174 clocks = <&ext_26m>, <&rco_100m>,
0175 <&ext_32k>, <&ext_4m>;
0176 clock-names = "ext-26m", "rco-100m",
0177 "ext-32k", "ext-4m";
0178 #clock-cells = <1>;
0179 };
0180
0181 mm_clk: clock-controller@60900000 {
0182 compatible = "sprd,sc9863a-mm-clk";
0183 reg = <0 0x60900000 0 0x1000>;
0184 #clock-cells = <1>;
0185 };
0186
0187 funnel@10001000 {
0188 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0189 reg = <0 0x10001000 0 0x1000>;
0190 clocks = <&ext_26m>;
0191 clock-names = "apb_pclk";
0192
0193 out-ports {
0194 port {
0195 funnel_soc_out_port: endpoint {
0196 remote-endpoint = <&etb_in>;
0197 };
0198 };
0199 };
0200
0201 in-ports {
0202 port {
0203 funnel_soc_in_port: endpoint {
0204 remote-endpoint =
0205 <&funnel_ca55_out_port>;
0206 };
0207 };
0208 };
0209 };
0210
0211 etb@10003000 {
0212 compatible = "arm,coresight-tmc", "arm,primecell";
0213 reg = <0 0x10003000 0 0x1000>;
0214 clocks = <&ext_26m>;
0215 clock-names = "apb_pclk";
0216
0217 in-ports {
0218 port {
0219 etb_in: endpoint {
0220 remote-endpoint =
0221 <&funnel_soc_out_port>;
0222 };
0223 };
0224 };
0225 };
0226
0227 funnel@12001000 {
0228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0229 reg = <0 0x12001000 0 0x1000>;
0230 clocks = <&ext_26m>;
0231 clock-names = "apb_pclk";
0232
0233 out-ports {
0234 port {
0235 funnel_little_out_port: endpoint {
0236 remote-endpoint =
0237 <&etf_little_in>;
0238 };
0239 };
0240 };
0241
0242 in-ports {
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245
0246 port@0 {
0247 reg = <0>;
0248 funnel_little_in_port0: endpoint {
0249 remote-endpoint = <&etm0_out>;
0250 };
0251 };
0252
0253 port@1 {
0254 reg = <1>;
0255 funnel_little_in_port1: endpoint {
0256 remote-endpoint = <&etm1_out>;
0257 };
0258 };
0259
0260 port@2 {
0261 reg = <2>;
0262 funnel_little_in_port2: endpoint {
0263 remote-endpoint = <&etm2_out>;
0264 };
0265 };
0266
0267 port@3 {
0268 reg = <3>;
0269 funnel_little_in_port3: endpoint {
0270 remote-endpoint = <&etm3_out>;
0271 };
0272 };
0273 };
0274 };
0275
0276 etf@12002000 {
0277 compatible = "arm,coresight-tmc", "arm,primecell";
0278 reg = <0 0x12002000 0 0x1000>;
0279 clocks = <&ext_26m>;
0280 clock-names = "apb_pclk";
0281
0282 out-ports {
0283 port {
0284 etf_little_out: endpoint {
0285 remote-endpoint =
0286 <&funnel_ca55_in_port0>;
0287 };
0288 };
0289 };
0290
0291 in-port {
0292 port {
0293 etf_little_in: endpoint {
0294 remote-endpoint =
0295 <&funnel_little_out_port>;
0296 };
0297 };
0298 };
0299 };
0300
0301 etf@12003000 {
0302 compatible = "arm,coresight-tmc", "arm,primecell";
0303 reg = <0 0x12003000 0 0x1000>;
0304 clocks = <&ext_26m>;
0305 clock-names = "apb_pclk";
0306
0307 out-ports {
0308 port {
0309 etf_big_out: endpoint {
0310 remote-endpoint =
0311 <&funnel_ca55_in_port1>;
0312 };
0313 };
0314 };
0315
0316 in-ports {
0317 port {
0318 etf_big_in: endpoint {
0319 remote-endpoint =
0320 <&funnel_big_out_port>;
0321 };
0322 };
0323 };
0324 };
0325
0326 funnel@12004000 {
0327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0328 reg = <0 0x12004000 0 0x1000>;
0329 clocks = <&ext_26m>;
0330 clock-names = "apb_pclk";
0331
0332 out-ports {
0333 port {
0334 funnel_ca55_out_port: endpoint {
0335 remote-endpoint =
0336 <&funnel_soc_in_port>;
0337 };
0338 };
0339 };
0340
0341 in-ports {
0342 #address-cells = <1>;
0343 #size-cells = <0>;
0344
0345 port@0 {
0346 reg = <0>;
0347 funnel_ca55_in_port0: endpoint {
0348 remote-endpoint =
0349 <&etf_little_out>;
0350 };
0351 };
0352
0353 port@1 {
0354 reg = <1>;
0355 funnel_ca55_in_port1: endpoint {
0356 remote-endpoint =
0357 <&etf_big_out>;
0358 };
0359 };
0360 };
0361 };
0362
0363 funnel@12005000 {
0364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0365 reg = <0 0x12005000 0 0x1000>;
0366 clocks = <&ext_26m>;
0367 clock-names = "apb_pclk";
0368
0369 out-ports {
0370 port {
0371 funnel_big_out_port: endpoint {
0372 remote-endpoint =
0373 <&etf_big_in>;
0374 };
0375 };
0376 };
0377
0378 in-ports {
0379 #address-cells = <1>;
0380 #size-cells = <0>;
0381
0382 port@0 {
0383 reg = <0>;
0384 funnel_big_in_port0: endpoint {
0385 remote-endpoint = <&etm4_out>;
0386 };
0387 };
0388
0389 port@1 {
0390 reg = <1>;
0391 funnel_big_in_port1: endpoint {
0392 remote-endpoint = <&etm5_out>;
0393 };
0394 };
0395
0396 port@2 {
0397 reg = <2>;
0398 funnel_big_in_port2: endpoint {
0399 remote-endpoint = <&etm6_out>;
0400 };
0401 };
0402
0403 port@3 {
0404 reg = <3>;
0405 funnel_big_in_port3: endpoint {
0406 remote-endpoint = <&etm7_out>;
0407 };
0408 };
0409 };
0410 };
0411
0412 etm@13040000 {
0413 compatible = "arm,coresight-etm4x", "arm,primecell";
0414 reg = <0 0x13040000 0 0x1000>;
0415 cpu = <&CPU0>;
0416 clocks = <&ext_26m>;
0417 clock-names = "apb_pclk";
0418
0419 out-ports {
0420 port {
0421 etm0_out: endpoint {
0422 remote-endpoint =
0423 <&funnel_little_in_port0>;
0424 };
0425 };
0426 };
0427 };
0428
0429 etm@13140000 {
0430 compatible = "arm,coresight-etm4x", "arm,primecell";
0431 reg = <0 0x13140000 0 0x1000>;
0432 cpu = <&CPU1>;
0433 clocks = <&ext_26m>;
0434 clock-names = "apb_pclk";
0435
0436 out-ports {
0437 port {
0438 etm1_out: endpoint {
0439 remote-endpoint =
0440 <&funnel_little_in_port1>;
0441 };
0442 };
0443 };
0444 };
0445
0446 etm@13240000 {
0447 compatible = "arm,coresight-etm4x", "arm,primecell";
0448 reg = <0 0x13240000 0 0x1000>;
0449 cpu = <&CPU2>;
0450 clocks = <&ext_26m>;
0451 clock-names = "apb_pclk";
0452
0453 out-ports {
0454 port {
0455 etm2_out: endpoint {
0456 remote-endpoint =
0457 <&funnel_little_in_port2>;
0458 };
0459 };
0460 };
0461 };
0462
0463 etm@13340000 {
0464 compatible = "arm,coresight-etm4x", "arm,primecell";
0465 reg = <0 0x13340000 0 0x1000>;
0466 cpu = <&CPU3>;
0467 clocks = <&ext_26m>;
0468 clock-names = "apb_pclk";
0469
0470 out-ports {
0471 port {
0472 etm3_out: endpoint {
0473 remote-endpoint =
0474 <&funnel_little_in_port3>;
0475 };
0476 };
0477 };
0478 };
0479
0480 etm@13440000 {
0481 compatible = "arm,coresight-etm4x", "arm,primecell";
0482 reg = <0 0x13440000 0 0x1000>;
0483 cpu = <&CPU4>;
0484 clocks = <&ext_26m>;
0485 clock-names = "apb_pclk";
0486
0487 out-ports {
0488 port {
0489 etm4_out: endpoint {
0490 remote-endpoint =
0491 <&funnel_big_in_port0>;
0492 };
0493 };
0494 };
0495 };
0496
0497 etm@13540000 {
0498 compatible = "arm,coresight-etm4x", "arm,primecell";
0499 reg = <0 0x13540000 0 0x1000>;
0500 cpu = <&CPU5>;
0501 clocks = <&ext_26m>;
0502 clock-names = "apb_pclk";
0503
0504 out-ports {
0505 port {
0506 etm5_out: endpoint {
0507 remote-endpoint =
0508 <&funnel_big_in_port1>;
0509 };
0510 };
0511 };
0512 };
0513
0514 etm@13640000 {
0515 compatible = "arm,coresight-etm4x", "arm,primecell";
0516 reg = <0 0x13640000 0 0x1000>;
0517 cpu = <&CPU6>;
0518 clocks = <&ext_26m>;
0519 clock-names = "apb_pclk";
0520
0521 out-ports {
0522 port {
0523 etm6_out: endpoint {
0524 remote-endpoint =
0525 <&funnel_big_in_port2>;
0526 };
0527 };
0528 };
0529 };
0530
0531 etm@13740000 {
0532 compatible = "arm,coresight-etm4x", "arm,primecell";
0533 reg = <0 0x13740000 0 0x1000>;
0534 cpu = <&CPU7>;
0535 clocks = <&ext_26m>;
0536 clock-names = "apb_pclk";
0537
0538 out-ports {
0539 port {
0540 etm7_out: endpoint {
0541 remote-endpoint =
0542 <&funnel_big_in_port3>;
0543 };
0544 };
0545 };
0546 };
0547
0548 ap-ahb {
0549 compatible = "simple-bus";
0550 #address-cells = <2>;
0551 #size-cells = <2>;
0552 ranges;
0553
0554 sdio0: sdio@20300000 {
0555 compatible = "sprd,sdhci-r11";
0556 reg = <0 0x20300000 0 0x1000>;
0557 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0558
0559 clock-names = "sdio", "enable";
0560 clocks = <&aon_clk CLK_SDIO0_2X>,
0561 <&apahb_gate CLK_SDIO0_EB>;
0562 assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
0563 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
0564
0565 bus-width = <4>;
0566 no-sdio;
0567 no-mmc;
0568 };
0569
0570 sdio3: sdio@20600000 {
0571 compatible = "sprd,sdhci-r11";
0572 reg = <0 0x20600000 0 0x1000>;
0573 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0574
0575 clock-names = "sdio", "enable";
0576 clocks = <&aon_clk CLK_EMMC_2X>,
0577 <&apahb_gate CLK_EMMC_EB>;
0578 assigned-clocks = <&aon_clk CLK_EMMC_2X>;
0579 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
0580
0581 bus-width = <8>;
0582 non-removable;
0583 no-sdio;
0584 no-sd;
0585 cap-mmc-hw-reset;
0586 };
0587 };
0588 };
0589 };
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