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0001 /*
0002 * Spreadtrum SC9860 SoC
0003 *
0004 * Copyright (C) 2016, Spreadtrum Communications Inc.
0005 *
0006 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0007 */
0008
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include "whale2.dtsi"
0013
0014 / {
0015 cpus {
0016 #address-cells = <2>;
0017 #size-cells = <0>;
0018
0019 cpu-map {
0020 cluster0 {
0021 core0 {
0022 cpu = <&CPU0>;
0023 };
0024 core1 {
0025 cpu = <&CPU1>;
0026 };
0027 core2 {
0028 cpu = <&CPU2>;
0029 };
0030 core3 {
0031 cpu = <&CPU3>;
0032 };
0033 };
0034
0035 cluster1 {
0036 core0 {
0037 cpu = <&CPU4>;
0038 };
0039 core1 {
0040 cpu = <&CPU5>;
0041 };
0042 core2 {
0043 cpu = <&CPU6>;
0044 };
0045 core3 {
0046 cpu = <&CPU7>;
0047 };
0048 };
0049 };
0050
0051 CPU0: cpu@530000 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a53";
0054 reg = <0x0 0x530000>;
0055 enable-method = "psci";
0056 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0057 };
0058
0059 CPU1: cpu@530001 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a53";
0062 reg = <0x0 0x530001>;
0063 enable-method = "psci";
0064 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0065 };
0066
0067 CPU2: cpu@530002 {
0068 device_type = "cpu";
0069 compatible = "arm,cortex-a53";
0070 reg = <0x0 0x530002>;
0071 enable-method = "psci";
0072 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0073 };
0074
0075 CPU3: cpu@530003 {
0076 device_type = "cpu";
0077 compatible = "arm,cortex-a53";
0078 reg = <0x0 0x530003>;
0079 enable-method = "psci";
0080 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0081 };
0082
0083 CPU4: cpu@530100 {
0084 device_type = "cpu";
0085 compatible = "arm,cortex-a53";
0086 reg = <0x0 0x530100>;
0087 enable-method = "psci";
0088 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0089 };
0090
0091 CPU5: cpu@530101 {
0092 device_type = "cpu";
0093 compatible = "arm,cortex-a53";
0094 reg = <0x0 0x530101>;
0095 enable-method = "psci";
0096 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0097 };
0098
0099 CPU6: cpu@530102 {
0100 device_type = "cpu";
0101 compatible = "arm,cortex-a53";
0102 reg = <0x0 0x530102>;
0103 enable-method = "psci";
0104 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0105 };
0106
0107 CPU7: cpu@530103 {
0108 device_type = "cpu";
0109 compatible = "arm,cortex-a53";
0110 reg = <0x0 0x530103>;
0111 enable-method = "psci";
0112 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
0113 };
0114 };
0115
0116 idle-states{
0117 entry-method = "psci";
0118
0119 CORE_PD: core_pd {
0120 compatible = "arm,idle-state";
0121 entry-latency-us = <1000>;
0122 exit-latency-us = <700>;
0123 min-residency-us = <2500>;
0124 local-timer-stop;
0125 arm,psci-suspend-param = <0x00010002>;
0126 };
0127
0128 CLUSTER_PD: cluster_pd {
0129 compatible = "arm,idle-state";
0130 entry-latency-us = <1000>;
0131 exit-latency-us = <1000>;
0132 min-residency-us = <3000>;
0133 local-timer-stop;
0134 arm,psci-suspend-param = <0x01010003>;
0135 };
0136 };
0137
0138 gic: interrupt-controller@12001000 {
0139 compatible = "arm,gic-400";
0140 reg = <0 0x12001000 0 0x1000>,
0141 <0 0x12002000 0 0x2000>,
0142 <0 0x12004000 0 0x2000>,
0143 <0 0x12006000 0 0x2000>;
0144 #interrupt-cells = <3>;
0145 interrupt-controller;
0146 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
0147 | IRQ_TYPE_LEVEL_HIGH)>;
0148 };
0149
0150 psci {
0151 compatible = "arm,psci-0.2";
0152 method = "smc";
0153 };
0154
0155 timer {
0156 compatible = "arm,armv8-timer";
0157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
0158 | IRQ_TYPE_LEVEL_LOW)>,
0159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
0160 | IRQ_TYPE_LEVEL_LOW)>,
0161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
0162 | IRQ_TYPE_LEVEL_LOW)>,
0163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
0164 | IRQ_TYPE_LEVEL_LOW)>;
0165 };
0166
0167 pmu {
0168 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
0169 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0177 interrupt-affinity = <&CPU0>,
0178 <&CPU1>,
0179 <&CPU2>,
0180 <&CPU3>,
0181 <&CPU4>,
0182 <&CPU5>,
0183 <&CPU6>,
0184 <&CPU7>;
0185 };
0186
0187 soc {
0188 pmu_gate: pmu-gate {
0189 compatible = "sprd,sc9860-pmu-gate";
0190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
0191 clocks = <&ext_26m>;
0192 #clock-cells = <1>;
0193 };
0194
0195 pll: pll {
0196 compatible = "sprd,sc9860-pll";
0197 sprd,syscon = <&ana_regs>; /* 0x40400000 */
0198 clocks = <&pmu_gate 0>;
0199 #clock-cells = <1>;
0200 };
0201
0202 ap_clk: clock-controller@20000000 {
0203 compatible = "sprd,sc9860-ap-clk";
0204 reg = <0 0x20000000 0 0x400>;
0205 clocks = <&ext_26m>, <&pll 0>,
0206 <&pmu_gate 0>;
0207 #clock-cells = <1>;
0208 };
0209
0210 aon_prediv: aon-prediv {
0211 compatible = "sprd,sc9860-aon-prediv";
0212 reg = <0 0x402d0000 0 0x400>;
0213 clocks = <&ext_26m>, <&pll 0>,
0214 <&pmu_gate 0>;
0215 #clock-cells = <1>;
0216 };
0217
0218 apahb_gate: apahb-gate {
0219 compatible = "sprd,sc9860-apahb-gate";
0220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
0221 clocks = <&aon_prediv 0>;
0222 #clock-cells = <1>;
0223 };
0224
0225 aon_gate: aon-gate {
0226 compatible = "sprd,sc9860-aon-gate";
0227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
0228 clocks = <&aon_prediv 0>;
0229 #clock-cells = <1>;
0230 };
0231
0232 aonsecure_clk: clock-controller@40880000 {
0233 compatible = "sprd,sc9860-aonsecure-clk";
0234 reg = <0 0x40880000 0 0x400>;
0235 clocks = <&ext_26m>, <&pll 0>;
0236 #clock-cells = <1>;
0237 };
0238
0239 agcp_gate: agcp-gate {
0240 compatible = "sprd,sc9860-agcp-gate";
0241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
0242 clocks = <&aon_prediv 0>;
0243 #clock-cells = <1>;
0244 };
0245
0246 gpu_clk: clock-controller@60200000 {
0247 compatible = "sprd,sc9860-gpu-clk";
0248 reg = <0 0x60200000 0 0x400>;
0249 clocks = <&pll 0>;
0250 #clock-cells = <1>;
0251 };
0252
0253 vsp_clk: clock-controller@61000000 {
0254 compatible = "sprd,sc9860-vsp-clk";
0255 reg = <0 0x61000000 0 0x400>;
0256 clocks = <&ext_26m>, <&pll 0>;
0257 #clock-cells = <1>;
0258 };
0259
0260 vsp_gate: vsp-gate {
0261 compatible = "sprd,sc9860-vsp-gate";
0262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
0263 clocks = <&vsp_clk 0>;
0264 #clock-cells = <1>;
0265 };
0266
0267 cam_clk: clock-controller@62000000 {
0268 compatible = "sprd,sc9860-cam-clk";
0269 reg = <0 0x62000000 0 0x4000>;
0270 clocks = <&ext_26m>, <&pll 0>;
0271 #clock-cells = <1>;
0272 };
0273
0274 cam_gate: cam-gate {
0275 compatible = "sprd,sc9860-cam-gate";
0276 sprd,syscon = <&cam_regs>; /* 0x62100000 */
0277 clocks = <&cam_clk 0>;
0278 #clock-cells = <1>;
0279 };
0280
0281 disp_clk: clock-controller@63000000 {
0282 compatible = "sprd,sc9860-disp-clk";
0283 reg = <0 0x63000000 0 0x400>;
0284 clocks = <&ext_26m>, <&pll 0>;
0285 #clock-cells = <1>;
0286 };
0287
0288 disp_gate: disp-gate {
0289 compatible = "sprd,sc9860-disp-gate";
0290 sprd,syscon = <&disp_regs>; /* 0x63100000 */
0291 clocks = <&disp_clk 0>;
0292 #clock-cells = <1>;
0293 };
0294
0295 apapb_gate: apapb-gate {
0296 compatible = "sprd,sc9860-apapb-gate";
0297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
0298 clocks = <&ap_clk 0>;
0299 #clock-cells = <1>;
0300 };
0301
0302 funnel@10001000 { /* SoC Funnel */
0303 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0304 reg = <0 0x10001000 0 0x1000>;
0305 clocks = <&ext_26m>;
0306 clock-names = "apb_pclk";
0307 out-ports {
0308 port {
0309 soc_funnel_out_port: endpoint {
0310 remote-endpoint = <&etb_in>;
0311 };
0312 };
0313 };
0314
0315 in-ports {
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318
0319 port@0 {
0320 reg = <0>;
0321 soc_funnel_in_port0: endpoint {
0322 remote-endpoint =
0323 <&main_funnel_out_port>;
0324 };
0325 };
0326
0327 port@4 {
0328 reg = <4>;
0329 soc_funnel_in_port1: endpoint {
0330 remote-endpoint =
0331 <&stm_out_port>;
0332 };
0333 };
0334 };
0335 };
0336
0337 etb@10003000 {
0338 compatible = "arm,coresight-tmc", "arm,primecell";
0339 reg = <0 0x10003000 0 0x1000>;
0340 clocks = <&ext_26m>;
0341 clock-names = "apb_pclk";
0342 out-ports {
0343 port {
0344 etb_in: endpoint {
0345 remote-endpoint =
0346 <&soc_funnel_out_port>;
0347 };
0348 };
0349 };
0350 };
0351
0352 stm@10006000 {
0353 compatible = "arm,coresight-stm", "arm,primecell";
0354 reg = <0 0x10006000 0 0x1000>,
0355 <0 0x01000000 0 0x180000>;
0356 reg-names = "stm-base", "stm-stimulus-base";
0357 clocks = <&ext_26m>;
0358 clock-names = "apb_pclk";
0359 out-ports {
0360 port {
0361 stm_out_port: endpoint {
0362 remote-endpoint =
0363 <&soc_funnel_in_port1>;
0364 };
0365 };
0366 };
0367 };
0368
0369 funnel@11001000 { /* Cluster0 Funnel */
0370 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0371 reg = <0 0x11001000 0 0x1000>;
0372 clocks = <&ext_26m>;
0373 clock-names = "apb_pclk";
0374 out-ports {
0375 port {
0376 cluster0_funnel_out_port: endpoint {
0377 remote-endpoint =
0378 <&cluster0_etf_in>;
0379 };
0380 };
0381 };
0382
0383 in-ports {
0384 #address-cells = <1>;
0385 #size-cells = <0>;
0386
0387 port@0 {
0388 reg = <0>;
0389 cluster0_funnel_in_port0: endpoint {
0390 remote-endpoint = <&etm0_out>;
0391 };
0392 };
0393
0394 port@1 {
0395 reg = <1>;
0396 cluster0_funnel_in_port1: endpoint {
0397 remote-endpoint = <&etm1_out>;
0398 };
0399 };
0400
0401 port@2 {
0402 reg = <2>;
0403 cluster0_funnel_in_port2: endpoint {
0404 remote-endpoint = <&etm2_out>;
0405 };
0406 };
0407
0408 port@4 {
0409 reg = <4>;
0410 cluster0_funnel_in_port3: endpoint {
0411 remote-endpoint = <&etm3_out>;
0412 };
0413 };
0414 };
0415 };
0416
0417 funnel@11002000 { /* Cluster1 Funnel */
0418 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0419 reg = <0 0x11002000 0 0x1000>;
0420 clocks = <&ext_26m>;
0421 clock-names = "apb_pclk";
0422 out-ports {
0423 port {
0424 cluster1_funnel_out_port: endpoint {
0425 remote-endpoint =
0426 <&cluster1_etf_in>;
0427 };
0428 };
0429 };
0430
0431 in-ports {
0432 #address-cells = <1>;
0433 #size-cells = <0>;
0434
0435 port@0 {
0436 reg = <0>;
0437 cluster1_funnel_in_port0: endpoint {
0438 remote-endpoint = <&etm4_out>;
0439 };
0440 };
0441
0442 port@1 {
0443 reg = <1>;
0444 cluster1_funnel_in_port1: endpoint {
0445 remote-endpoint = <&etm5_out>;
0446 };
0447 };
0448
0449 port@2 {
0450 reg = <2>;
0451 cluster1_funnel_in_port2: endpoint {
0452 remote-endpoint = <&etm6_out>;
0453 };
0454 };
0455
0456 port@3 {
0457 reg = <3>;
0458 cluster1_funnel_in_port3: endpoint {
0459 remote-endpoint = <&etm7_out>;
0460 };
0461 };
0462 };
0463 };
0464
0465 etf@11003000 { /* ETF on Cluster0 */
0466 compatible = "arm,coresight-tmc", "arm,primecell";
0467 reg = <0 0x11003000 0 0x1000>;
0468 clocks = <&ext_26m>;
0469 clock-names = "apb_pclk";
0470
0471 out-ports {
0472 port {
0473 cluster0_etf_out: endpoint {
0474 remote-endpoint =
0475 <&main_funnel_in_port0>;
0476 };
0477 };
0478 };
0479
0480 in-ports {
0481 port {
0482 cluster0_etf_in: endpoint {
0483 remote-endpoint =
0484 <&cluster0_funnel_out_port>;
0485 };
0486 };
0487 };
0488 };
0489
0490 etf@11004000 { /* ETF on Cluster1 */
0491 compatible = "arm,coresight-tmc", "arm,primecell";
0492 reg = <0 0x11004000 0 0x1000>;
0493 clocks = <&ext_26m>;
0494 clock-names = "apb_pclk";
0495
0496 out-ports {
0497 port {
0498 cluster1_etf_out: endpoint {
0499 remote-endpoint =
0500 <&main_funnel_in_port1>;
0501 };
0502 };
0503 };
0504
0505 in-ports {
0506 port {
0507 cluster1_etf_in: endpoint {
0508 remote-endpoint =
0509 <&cluster1_funnel_out_port>;
0510 };
0511 };
0512 };
0513 };
0514
0515 funnel@11005000 { /* Main Funnel */
0516 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0517 reg = <0 0x11005000 0 0x1000>;
0518 clocks = <&ext_26m>;
0519 clock-names = "apb_pclk";
0520
0521 out-ports {
0522 port {
0523 main_funnel_out_port: endpoint {
0524 remote-endpoint =
0525 <&soc_funnel_in_port0>;
0526 };
0527 };
0528 };
0529
0530 in-ports {
0531 #address-cells = <1>;
0532 #size-cells = <0>;
0533
0534 port@0 {
0535 reg = <0>;
0536 main_funnel_in_port0: endpoint {
0537 remote-endpoint =
0538 <&cluster0_etf_out>;
0539 };
0540 };
0541
0542 port@1 {
0543 reg = <1>;
0544 main_funnel_in_port1: endpoint {
0545 remote-endpoint =
0546 <&cluster1_etf_out>;
0547 };
0548 };
0549 };
0550 };
0551
0552 etm@11440000 {
0553 compatible = "arm,coresight-etm4x", "arm,primecell";
0554 reg = <0 0x11440000 0 0x1000>;
0555 cpu = <&CPU0>;
0556 clocks = <&ext_26m>;
0557 clock-names = "apb_pclk";
0558
0559 out-ports {
0560 port {
0561 etm0_out: endpoint {
0562 remote-endpoint =
0563 <&cluster0_funnel_in_port0>;
0564 };
0565 };
0566 };
0567 };
0568
0569 etm@11540000 {
0570 compatible = "arm,coresight-etm4x", "arm,primecell";
0571 reg = <0 0x11540000 0 0x1000>;
0572 cpu = <&CPU1>;
0573 clocks = <&ext_26m>;
0574 clock-names = "apb_pclk";
0575
0576 out-ports {
0577 port {
0578 etm1_out: endpoint {
0579 remote-endpoint =
0580 <&cluster0_funnel_in_port1>;
0581 };
0582 };
0583 };
0584 };
0585
0586 etm@11640000 {
0587 compatible = "arm,coresight-etm4x", "arm,primecell";
0588 reg = <0 0x11640000 0 0x1000>;
0589 cpu = <&CPU2>;
0590 clocks = <&ext_26m>;
0591 clock-names = "apb_pclk";
0592
0593 out-ports {
0594 port {
0595 etm2_out: endpoint {
0596 remote-endpoint =
0597 <&cluster0_funnel_in_port2>;
0598 };
0599 };
0600 };
0601 };
0602
0603 etm@11740000 {
0604 compatible = "arm,coresight-etm4x", "arm,primecell";
0605 reg = <0 0x11740000 0 0x1000>;
0606 cpu = <&CPU3>;
0607 clocks = <&ext_26m>;
0608 clock-names = "apb_pclk";
0609
0610 out-ports {
0611 port {
0612 etm3_out: endpoint {
0613 remote-endpoint =
0614 <&cluster0_funnel_in_port3>;
0615 };
0616 };
0617 };
0618 };
0619
0620 etm@11840000 {
0621 compatible = "arm,coresight-etm4x", "arm,primecell";
0622 reg = <0 0x11840000 0 0x1000>;
0623 cpu = <&CPU4>;
0624 clocks = <&ext_26m>;
0625 clock-names = "apb_pclk";
0626
0627 out-ports {
0628 port {
0629 etm4_out: endpoint {
0630 remote-endpoint =
0631 <&cluster1_funnel_in_port0>;
0632 };
0633 };
0634 };
0635 };
0636
0637 etm@11940000 {
0638 compatible = "arm,coresight-etm4x", "arm,primecell";
0639 reg = <0 0x11940000 0 0x1000>;
0640 cpu = <&CPU5>;
0641 clocks = <&ext_26m>;
0642 clock-names = "apb_pclk";
0643
0644 out-ports {
0645 port {
0646 etm5_out: endpoint {
0647 remote-endpoint =
0648 <&cluster1_funnel_in_port1>;
0649 };
0650 };
0651 };
0652 };
0653
0654 etm@11a40000 {
0655 compatible = "arm,coresight-etm4x", "arm,primecell";
0656 reg = <0 0x11a40000 0 0x1000>;
0657 cpu = <&CPU6>;
0658 clocks = <&ext_26m>;
0659 clock-names = "apb_pclk";
0660
0661 out-ports {
0662 port {
0663 etm6_out: endpoint {
0664 remote-endpoint =
0665 <&cluster1_funnel_in_port2>;
0666 };
0667 };
0668 };
0669 };
0670
0671 etm@11b40000 {
0672 compatible = "arm,coresight-etm4x", "arm,primecell";
0673 reg = <0 0x11b40000 0 0x1000>;
0674 cpu = <&CPU7>;
0675 clocks = <&ext_26m>;
0676 clock-names = "apb_pclk";
0677
0678 out-ports {
0679 port {
0680 etm7_out: endpoint {
0681 remote-endpoint =
0682 <&cluster1_funnel_in_port3>;
0683 };
0684 };
0685 };
0686 };
0687
0688 gpio-keys {
0689 compatible = "gpio-keys";
0690
0691 key-volumedown {
0692 label = "Volume Down Key";
0693 linux,code = <KEY_VOLUMEDOWN>;
0694 gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
0695 debounce-interval = <2>;
0696 wakeup-source;
0697 };
0698
0699 key-volumeup {
0700 label = "Volume Up Key";
0701 linux,code = <KEY_VOLUMEUP>;
0702 gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
0703 debounce-interval = <2>;
0704 wakeup-source;
0705 };
0706
0707 key-power {
0708 label = "Power Key";
0709 linux,code = <KEY_POWER>;
0710 gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
0711 debounce-interval = <2>;
0712 wakeup-source;
0713 };
0714 };
0715 };
0716 };
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