0001 /*
0002 * Spreadtrum SC9836 SoC DTS file
0003 *
0004 * Copyright (C) 2014, Spreadtrum Communications Inc.
0005 *
0006 * This file is licensed under a dual GPLv2 or X11 license.
0007 */
0008
0009 #include "sharkl64.dtsi"
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 / {
0013 compatible = "sprd,sc9836";
0014
0015 cpus {
0016 #address-cells = <2>;
0017 #size-cells = <0>;
0018
0019 cpu0: cpu@0 {
0020 device_type = "cpu";
0021 compatible = "arm,cortex-a53";
0022 reg = <0x0 0x0>;
0023 enable-method = "psci";
0024 };
0025
0026 cpu1: cpu@1 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a53";
0029 reg = <0x0 0x1>;
0030 enable-method = "psci";
0031 };
0032
0033 cpu2: cpu@2 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a53";
0036 reg = <0x0 0x2>;
0037 enable-method = "psci";
0038 };
0039
0040 cpu3: cpu@3 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a53";
0043 reg = <0x0 0x3>;
0044 enable-method = "psci";
0045 };
0046 };
0047
0048 etf@10003000 {
0049 compatible = "arm,coresight-tmc", "arm,primecell";
0050 reg = <0 0x10003000 0 0x1000>;
0051 clocks = <&clk26mhz>;
0052 clock-names = "apb_pclk";
0053 in-ports {
0054 port {
0055 etf_in: endpoint {
0056 remote-endpoint = <&funnel_out_port0>;
0057 };
0058 };
0059 };
0060 };
0061
0062 funnel@10001000 {
0063 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0064 reg = <0 0x10001000 0 0x1000>;
0065 clocks = <&clk26mhz>;
0066 clock-names = "apb_pclk";
0067
0068 out-ports {
0069 port {
0070 funnel_out_port0: endpoint {
0071 remote-endpoint = <&etf_in>;
0072 };
0073 };
0074 };
0075
0076 in-ports {
0077 #address-cells = <1>;
0078 #size-cells = <0>;
0079
0080 port@0 {
0081 reg = <0>;
0082 funnel_in_port0: endpoint {
0083 remote-endpoint = <&etm0_out>;
0084 };
0085 };
0086
0087 port@1 {
0088 reg = <1>;
0089 funnel_in_port1: endpoint {
0090 remote-endpoint = <&etm1_out>;
0091 };
0092 };
0093
0094 port@2 {
0095 reg = <2>;
0096 funnel_in_port2: endpoint {
0097 remote-endpoint = <&etm2_out>;
0098 };
0099 };
0100
0101 port@3 {
0102 reg = <3>;
0103 funnel_in_port3: endpoint {
0104 remote-endpoint = <&etm3_out>;
0105 };
0106 };
0107
0108 port@4 {
0109 reg = <4>;
0110 funnel_in_port4: endpoint {
0111 remote-endpoint = <&stm_out>;
0112 };
0113 };
0114 /* Other input ports aren't connected to anyone */
0115 };
0116 };
0117
0118 etm@10440000 {
0119 compatible = "arm,coresight-etm4x", "arm,primecell";
0120 reg = <0 0x10440000 0 0x1000>;
0121
0122 cpu = <&cpu0>;
0123 clocks = <&clk26mhz>;
0124 clock-names = "apb_pclk";
0125 out-ports {
0126 port {
0127 etm0_out: endpoint {
0128 remote-endpoint = <&funnel_in_port0>;
0129 };
0130 };
0131 };
0132 };
0133
0134 etm@10540000 {
0135 compatible = "arm,coresight-etm4x", "arm,primecell";
0136 reg = <0 0x10540000 0 0x1000>;
0137
0138 cpu = <&cpu1>;
0139 clocks = <&clk26mhz>;
0140 clock-names = "apb_pclk";
0141 out-ports {
0142 port {
0143 etm1_out: endpoint {
0144 remote-endpoint = <&funnel_in_port1>;
0145 };
0146 };
0147 };
0148 };
0149
0150 etm@10640000 {
0151 compatible = "arm,coresight-etm4x", "arm,primecell";
0152 reg = <0 0x10640000 0 0x1000>;
0153
0154 cpu = <&cpu2>;
0155 clocks = <&clk26mhz>;
0156 clock-names = "apb_pclk";
0157 out-ports {
0158 port {
0159 etm2_out: endpoint {
0160 remote-endpoint = <&funnel_in_port2>;
0161 };
0162 };
0163 };
0164 };
0165
0166 etm@10740000 {
0167 compatible = "arm,coresight-etm4x", "arm,primecell";
0168 reg = <0 0x10740000 0 0x1000>;
0169
0170 cpu = <&cpu3>;
0171 clocks = <&clk26mhz>;
0172 clock-names = "apb_pclk";
0173 out-ports {
0174 port {
0175 etm3_out: endpoint {
0176 remote-endpoint = <&funnel_in_port3>;
0177 };
0178 };
0179 };
0180 };
0181
0182 stm@10006000 {
0183 compatible = "arm,coresight-stm", "arm,primecell";
0184 reg = <0 0x10006000 0 0x1000>,
0185 <0 0x01000000 0 0x180000>;
0186 reg-names = "stm-base", "stm-stimulus-base";
0187 clocks = <&clk26mhz>;
0188 clock-names = "apb_pclk";
0189 out-ports {
0190 port {
0191 stm_out: endpoint {
0192 remote-endpoint = <&funnel_in_port4>;
0193 };
0194 };
0195 };
0196 };
0197
0198 gic: interrupt-controller@12001000 {
0199 compatible = "arm,gic-400";
0200 reg = <0 0x12001000 0 0x1000>,
0201 <0 0x12002000 0 0x2000>,
0202 <0 0x12004000 0 0x2000>,
0203 <0 0x12006000 0 0x2000>;
0204 #interrupt-cells = <3>;
0205 interrupt-controller;
0206 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0207 };
0208
0209 psci {
0210 compatible = "arm,psci";
0211 method = "smc";
0212 cpu_on = <0xc4000003>;
0213 cpu_off = <0x84000002>;
0214 cpu_suspend = <0xc4000001>;
0215 };
0216
0217 timer {
0218 compatible = "arm,armv8-timer";
0219 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0220 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0221 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0222 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0223 };
0224 };
