0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier LD20 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/gpio/uniphier-gpio.h>
0010 #include <dt-bindings/thermal/thermal.h>
0011
0012 / {
0013 compatible = "socionext,uniphier-ld20";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016 interrupt-parent = <&gic>;
0017
0018 cpus {
0019 #address-cells = <2>;
0020 #size-cells = <0>;
0021
0022 cpu-map {
0023 cluster0 {
0024 core0 {
0025 cpu = <&cpu0>;
0026 };
0027 core1 {
0028 cpu = <&cpu1>;
0029 };
0030 };
0031
0032 cluster1 {
0033 core0 {
0034 cpu = <&cpu2>;
0035 };
0036 core1 {
0037 cpu = <&cpu3>;
0038 };
0039 };
0040 };
0041
0042 cpu0: cpu@0 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a72";
0045 reg = <0 0x000>;
0046 clocks = <&sys_clk 32>;
0047 enable-method = "psci";
0048 operating-points-v2 = <&cluster0_opp>;
0049 #cooling-cells = <2>;
0050 };
0051
0052 cpu1: cpu@1 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a72";
0055 reg = <0 0x001>;
0056 clocks = <&sys_clk 32>;
0057 enable-method = "psci";
0058 operating-points-v2 = <&cluster0_opp>;
0059 #cooling-cells = <2>;
0060 };
0061
0062 cpu2: cpu@100 {
0063 device_type = "cpu";
0064 compatible = "arm,cortex-a53";
0065 reg = <0 0x100>;
0066 clocks = <&sys_clk 33>;
0067 enable-method = "psci";
0068 operating-points-v2 = <&cluster1_opp>;
0069 #cooling-cells = <2>;
0070 };
0071
0072 cpu3: cpu@101 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a53";
0075 reg = <0 0x101>;
0076 clocks = <&sys_clk 33>;
0077 enable-method = "psci";
0078 operating-points-v2 = <&cluster1_opp>;
0079 #cooling-cells = <2>;
0080 };
0081 };
0082
0083 cluster0_opp: opp-table0 {
0084 compatible = "operating-points-v2";
0085 opp-shared;
0086
0087 opp-250000000 {
0088 opp-hz = /bits/ 64 <250000000>;
0089 clock-latency-ns = <300>;
0090 };
0091 opp-275000000 {
0092 opp-hz = /bits/ 64 <275000000>;
0093 clock-latency-ns = <300>;
0094 };
0095 opp-500000000 {
0096 opp-hz = /bits/ 64 <500000000>;
0097 clock-latency-ns = <300>;
0098 };
0099 opp-550000000 {
0100 opp-hz = /bits/ 64 <550000000>;
0101 clock-latency-ns = <300>;
0102 };
0103 opp-666667000 {
0104 opp-hz = /bits/ 64 <666667000>;
0105 clock-latency-ns = <300>;
0106 };
0107 opp-733334000 {
0108 opp-hz = /bits/ 64 <733334000>;
0109 clock-latency-ns = <300>;
0110 };
0111 opp-1000000000 {
0112 opp-hz = /bits/ 64 <1000000000>;
0113 clock-latency-ns = <300>;
0114 };
0115 opp-1100000000 {
0116 opp-hz = /bits/ 64 <1100000000>;
0117 clock-latency-ns = <300>;
0118 };
0119 };
0120
0121 cluster1_opp: opp-table1 {
0122 compatible = "operating-points-v2";
0123 opp-shared;
0124
0125 opp-250000000 {
0126 opp-hz = /bits/ 64 <250000000>;
0127 clock-latency-ns = <300>;
0128 };
0129 opp-275000000 {
0130 opp-hz = /bits/ 64 <275000000>;
0131 clock-latency-ns = <300>;
0132 };
0133 opp-500000000 {
0134 opp-hz = /bits/ 64 <500000000>;
0135 clock-latency-ns = <300>;
0136 };
0137 opp-550000000 {
0138 opp-hz = /bits/ 64 <550000000>;
0139 clock-latency-ns = <300>;
0140 };
0141 opp-666667000 {
0142 opp-hz = /bits/ 64 <666667000>;
0143 clock-latency-ns = <300>;
0144 };
0145 opp-733334000 {
0146 opp-hz = /bits/ 64 <733334000>;
0147 clock-latency-ns = <300>;
0148 };
0149 opp-1000000000 {
0150 opp-hz = /bits/ 64 <1000000000>;
0151 clock-latency-ns = <300>;
0152 };
0153 opp-1100000000 {
0154 opp-hz = /bits/ 64 <1100000000>;
0155 clock-latency-ns = <300>;
0156 };
0157 };
0158
0159 psci {
0160 compatible = "arm,psci-1.0";
0161 method = "smc";
0162 };
0163
0164 clocks {
0165 refclk: ref {
0166 compatible = "fixed-clock";
0167 #clock-cells = <0>;
0168 clock-frequency = <25000000>;
0169 };
0170 };
0171
0172 emmc_pwrseq: emmc-pwrseq {
0173 compatible = "mmc-pwrseq-emmc";
0174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
0175 };
0176
0177 timer {
0178 compatible = "arm,armv8-timer";
0179 interrupts = <1 13 4>,
0180 <1 14 4>,
0181 <1 11 4>,
0182 <1 10 4>;
0183 };
0184
0185 thermal-zones {
0186 cpu-thermal {
0187 polling-delay-passive = <250>; /* 250ms */
0188 polling-delay = <1000>; /* 1000ms */
0189 thermal-sensors = <&pvtctl>;
0190
0191 trips {
0192 cpu_crit: cpu-crit {
0193 temperature = <110000>; /* 110C */
0194 hysteresis = <2000>;
0195 type = "critical";
0196 };
0197 cpu_alert: cpu-alert {
0198 temperature = <100000>; /* 100C */
0199 hysteresis = <2000>;
0200 type = "passive";
0201 };
0202 };
0203
0204 cooling-maps {
0205 map0 {
0206 trip = <&cpu_alert>;
0207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0211 };
0212 };
0213 };
0214 };
0215
0216 reserved-memory {
0217 #address-cells = <2>;
0218 #size-cells = <2>;
0219 ranges;
0220
0221 secure-memory@81000000 {
0222 reg = <0x0 0x81000000 0x0 0x01000000>;
0223 no-map;
0224 };
0225 };
0226
0227 soc@0 {
0228 compatible = "simple-bus";
0229 #address-cells = <1>;
0230 #size-cells = <1>;
0231 ranges = <0 0 0 0xffffffff>;
0232
0233 spi0: spi@54006000 {
0234 compatible = "socionext,uniphier-scssi";
0235 status = "disabled";
0236 reg = <0x54006000 0x100>;
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 interrupts = <0 39 4>;
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_spi0>;
0242 clocks = <&peri_clk 11>;
0243 resets = <&peri_rst 11>;
0244 };
0245
0246 spi1: spi@54006100 {
0247 compatible = "socionext,uniphier-scssi";
0248 status = "disabled";
0249 reg = <0x54006100 0x100>;
0250 #address-cells = <1>;
0251 #size-cells = <0>;
0252 interrupts = <0 216 4>;
0253 pinctrl-names = "default";
0254 pinctrl-0 = <&pinctrl_spi1>;
0255 clocks = <&peri_clk 12>;
0256 resets = <&peri_rst 12>;
0257 };
0258
0259 spi2: spi@54006200 {
0260 compatible = "socionext,uniphier-scssi";
0261 status = "disabled";
0262 reg = <0x54006200 0x100>;
0263 #address-cells = <1>;
0264 #size-cells = <0>;
0265 interrupts = <0 229 4>;
0266 pinctrl-names = "default";
0267 pinctrl-0 = <&pinctrl_spi2>;
0268 clocks = <&peri_clk 13>;
0269 resets = <&peri_rst 13>;
0270 };
0271
0272 spi3: spi@54006300 {
0273 compatible = "socionext,uniphier-scssi";
0274 status = "disabled";
0275 reg = <0x54006300 0x100>;
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 interrupts = <0 230 4>;
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&pinctrl_spi3>;
0281 clocks = <&peri_clk 14>;
0282 resets = <&peri_rst 14>;
0283 };
0284
0285 serial0: serial@54006800 {
0286 compatible = "socionext,uniphier-uart";
0287 status = "disabled";
0288 reg = <0x54006800 0x40>;
0289 interrupts = <0 33 4>;
0290 pinctrl-names = "default";
0291 pinctrl-0 = <&pinctrl_uart0>;
0292 clocks = <&peri_clk 0>;
0293 resets = <&peri_rst 0>;
0294 };
0295
0296 serial1: serial@54006900 {
0297 compatible = "socionext,uniphier-uart";
0298 status = "disabled";
0299 reg = <0x54006900 0x40>;
0300 interrupts = <0 35 4>;
0301 pinctrl-names = "default";
0302 pinctrl-0 = <&pinctrl_uart1>;
0303 clocks = <&peri_clk 1>;
0304 resets = <&peri_rst 1>;
0305 };
0306
0307 serial2: serial@54006a00 {
0308 compatible = "socionext,uniphier-uart";
0309 status = "disabled";
0310 reg = <0x54006a00 0x40>;
0311 interrupts = <0 37 4>;
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&pinctrl_uart2>;
0314 clocks = <&peri_clk 2>;
0315 resets = <&peri_rst 2>;
0316 };
0317
0318 serial3: serial@54006b00 {
0319 compatible = "socionext,uniphier-uart";
0320 status = "disabled";
0321 reg = <0x54006b00 0x40>;
0322 interrupts = <0 177 4>;
0323 pinctrl-names = "default";
0324 pinctrl-0 = <&pinctrl_uart3>;
0325 clocks = <&peri_clk 3>;
0326 resets = <&peri_rst 3>;
0327 };
0328
0329 gpio: gpio@55000000 {
0330 compatible = "socionext,uniphier-gpio";
0331 reg = <0x55000000 0x200>;
0332 interrupt-parent = <&aidet>;
0333 interrupt-controller;
0334 #interrupt-cells = <2>;
0335 gpio-controller;
0336 #gpio-cells = <2>;
0337 gpio-ranges = <&pinctrl 0 0 0>,
0338 <&pinctrl 96 0 0>,
0339 <&pinctrl 160 0 0>;
0340 gpio-ranges-group-names = "gpio_range0",
0341 "gpio_range1",
0342 "gpio_range2";
0343 ngpios = <205>;
0344 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
0345 <21 217 3>;
0346 };
0347
0348 audio@56000000 {
0349 compatible = "socionext,uniphier-ld20-aio";
0350 reg = <0x56000000 0x80000>;
0351 interrupts = <0 144 4>;
0352 pinctrl-names = "default";
0353 pinctrl-0 = <&pinctrl_aout1>,
0354 <&pinctrl_aoutiec1>;
0355 clock-names = "aio";
0356 clocks = <&sys_clk 40>;
0357 reset-names = "aio";
0358 resets = <&sys_rst 40>;
0359 #sound-dai-cells = <1>;
0360 socionext,syscon = <&soc_glue>;
0361
0362 i2s_port0: port@0 {
0363 i2s_hdmi: endpoint {
0364 };
0365 };
0366
0367 i2s_port1: port@1 {
0368 i2s_pcmin2: endpoint {
0369 };
0370 };
0371
0372 i2s_port2: port@2 {
0373 i2s_line: endpoint {
0374 dai-format = "i2s";
0375 remote-endpoint = <&evea_line>;
0376 };
0377 };
0378
0379 i2s_port3: port@3 {
0380 i2s_hpcmout1: endpoint {
0381 };
0382 };
0383
0384 i2s_port4: port@4 {
0385 i2s_hp: endpoint {
0386 dai-format = "i2s";
0387 remote-endpoint = <&evea_hp>;
0388 };
0389 };
0390
0391 spdif_port0: port@5 {
0392 spdif_hiecout1: endpoint {
0393 };
0394 };
0395
0396 src_port0: port@6 {
0397 i2s_epcmout2: endpoint {
0398 };
0399 };
0400
0401 src_port1: port@7 {
0402 i2s_epcmout3: endpoint {
0403 };
0404 };
0405
0406 comp_spdif_port0: port@8 {
0407 comp_spdif_hiecout1: endpoint {
0408 };
0409 };
0410 };
0411
0412 codec@57900000 {
0413 compatible = "socionext,uniphier-evea";
0414 reg = <0x57900000 0x1000>;
0415 clock-names = "evea", "exiv";
0416 clocks = <&sys_clk 41>, <&sys_clk 42>;
0417 reset-names = "evea", "exiv", "adamv";
0418 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
0419 #sound-dai-cells = <1>;
0420
0421 port@0 {
0422 evea_line: endpoint {
0423 remote-endpoint = <&i2s_line>;
0424 };
0425 };
0426
0427 port@1 {
0428 evea_hp: endpoint {
0429 remote-endpoint = <&i2s_hp>;
0430 };
0431 };
0432 };
0433
0434 adamv@57920000 {
0435 compatible = "socionext,uniphier-ld20-adamv",
0436 "simple-mfd", "syscon";
0437 reg = <0x57920000 0x1000>;
0438
0439 adamv_rst: reset {
0440 compatible = "socionext,uniphier-ld20-adamv-reset";
0441 #reset-cells = <1>;
0442 };
0443 };
0444
0445 i2c0: i2c@58780000 {
0446 compatible = "socionext,uniphier-fi2c";
0447 status = "disabled";
0448 reg = <0x58780000 0x80>;
0449 #address-cells = <1>;
0450 #size-cells = <0>;
0451 interrupts = <0 41 4>;
0452 pinctrl-names = "default";
0453 pinctrl-0 = <&pinctrl_i2c0>;
0454 clocks = <&peri_clk 4>;
0455 resets = <&peri_rst 4>;
0456 clock-frequency = <100000>;
0457 };
0458
0459 i2c1: i2c@58781000 {
0460 compatible = "socionext,uniphier-fi2c";
0461 status = "disabled";
0462 reg = <0x58781000 0x80>;
0463 #address-cells = <1>;
0464 #size-cells = <0>;
0465 interrupts = <0 42 4>;
0466 pinctrl-names = "default";
0467 pinctrl-0 = <&pinctrl_i2c1>;
0468 clocks = <&peri_clk 5>;
0469 resets = <&peri_rst 5>;
0470 clock-frequency = <100000>;
0471 };
0472
0473 i2c2: i2c@58782000 {
0474 compatible = "socionext,uniphier-fi2c";
0475 reg = <0x58782000 0x80>;
0476 #address-cells = <1>;
0477 #size-cells = <0>;
0478 interrupts = <0 43 4>;
0479 clocks = <&peri_clk 6>;
0480 resets = <&peri_rst 6>;
0481 clock-frequency = <400000>;
0482 };
0483
0484 i2c3: i2c@58783000 {
0485 compatible = "socionext,uniphier-fi2c";
0486 status = "disabled";
0487 reg = <0x58783000 0x80>;
0488 #address-cells = <1>;
0489 #size-cells = <0>;
0490 interrupts = <0 44 4>;
0491 pinctrl-names = "default";
0492 pinctrl-0 = <&pinctrl_i2c3>;
0493 clocks = <&peri_clk 7>;
0494 resets = <&peri_rst 7>;
0495 clock-frequency = <100000>;
0496 };
0497
0498 i2c4: i2c@58784000 {
0499 compatible = "socionext,uniphier-fi2c";
0500 status = "disabled";
0501 reg = <0x58784000 0x80>;
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 interrupts = <0 45 4>;
0505 pinctrl-names = "default";
0506 pinctrl-0 = <&pinctrl_i2c4>;
0507 clocks = <&peri_clk 8>;
0508 resets = <&peri_rst 8>;
0509 clock-frequency = <100000>;
0510 };
0511
0512 i2c5: i2c@58785000 {
0513 compatible = "socionext,uniphier-fi2c";
0514 reg = <0x58785000 0x80>;
0515 #address-cells = <1>;
0516 #size-cells = <0>;
0517 interrupts = <0 25 4>;
0518 clocks = <&peri_clk 9>;
0519 resets = <&peri_rst 9>;
0520 clock-frequency = <400000>;
0521 };
0522
0523 system_bus: system-bus@58c00000 {
0524 compatible = "socionext,uniphier-system-bus";
0525 status = "disabled";
0526 reg = <0x58c00000 0x400>;
0527 #address-cells = <2>;
0528 #size-cells = <1>;
0529 pinctrl-names = "default";
0530 pinctrl-0 = <&pinctrl_system_bus>;
0531 };
0532
0533 smpctrl@59801000 {
0534 compatible = "socionext,uniphier-smpctrl";
0535 reg = <0x59801000 0x400>;
0536 };
0537
0538 sdctrl@59810000 {
0539 compatible = "socionext,uniphier-ld20-sdctrl",
0540 "simple-mfd", "syscon";
0541 reg = <0x59810000 0x400>;
0542
0543 sd_clk: clock {
0544 compatible = "socionext,uniphier-ld20-sd-clock";
0545 #clock-cells = <1>;
0546 };
0547
0548 sd_rst: reset {
0549 compatible = "socionext,uniphier-ld20-sd-reset";
0550 #reset-cells = <1>;
0551 };
0552 };
0553
0554 perictrl@59820000 {
0555 compatible = "socionext,uniphier-ld20-perictrl",
0556 "simple-mfd", "syscon";
0557 reg = <0x59820000 0x200>;
0558
0559 peri_clk: clock {
0560 compatible = "socionext,uniphier-ld20-peri-clock";
0561 #clock-cells = <1>;
0562 };
0563
0564 peri_rst: reset {
0565 compatible = "socionext,uniphier-ld20-peri-reset";
0566 #reset-cells = <1>;
0567 };
0568 };
0569
0570 emmc: mmc@5a000000 {
0571 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
0572 reg = <0x5a000000 0x400>;
0573 interrupts = <0 78 4>;
0574 pinctrl-names = "default";
0575 pinctrl-0 = <&pinctrl_emmc>;
0576 clocks = <&sys_clk 4>;
0577 resets = <&sys_rst 4>;
0578 bus-width = <8>;
0579 mmc-ddr-1_8v;
0580 mmc-hs200-1_8v;
0581 mmc-pwrseq = <&emmc_pwrseq>;
0582 cdns,phy-input-delay-legacy = <9>;
0583 cdns,phy-input-delay-mmc-highspeed = <2>;
0584 cdns,phy-input-delay-mmc-ddr = <3>;
0585 cdns,phy-dll-delay-sdclk = <21>;
0586 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
0587 };
0588
0589 sd: mmc@5a400000 {
0590 compatible = "socionext,uniphier-sd-v3.1.1";
0591 status = "disabled";
0592 reg = <0x5a400000 0x800>;
0593 interrupts = <0 76 4>;
0594 pinctrl-names = "default";
0595 pinctrl-0 = <&pinctrl_sd>;
0596 clocks = <&sd_clk 0>;
0597 reset-names = "host";
0598 resets = <&sd_rst 0>;
0599 bus-width = <4>;
0600 cap-sd-highspeed;
0601 };
0602
0603 soc_glue: soc-glue@5f800000 {
0604 compatible = "socionext,uniphier-ld20-soc-glue",
0605 "simple-mfd", "syscon";
0606 reg = <0x5f800000 0x2000>;
0607
0608 pinctrl: pinctrl {
0609 compatible = "socionext,uniphier-ld20-pinctrl";
0610 };
0611 };
0612
0613 soc-glue@5f900000 {
0614 compatible = "socionext,uniphier-ld20-soc-glue-debug",
0615 "simple-mfd";
0616 #address-cells = <1>;
0617 #size-cells = <1>;
0618 ranges = <0 0x5f900000 0x2000>;
0619
0620 efuse@100 {
0621 compatible = "socionext,uniphier-efuse";
0622 reg = <0x100 0x28>;
0623 };
0624
0625 efuse@200 {
0626 compatible = "socionext,uniphier-efuse";
0627 reg = <0x200 0x68>;
0628 #address-cells = <1>;
0629 #size-cells = <1>;
0630
0631 /* USB cells */
0632 usb_rterm0: trim@54,4 {
0633 reg = <0x54 1>;
0634 bits = <4 2>;
0635 };
0636 usb_rterm1: trim@55,4 {
0637 reg = <0x55 1>;
0638 bits = <4 2>;
0639 };
0640 usb_rterm2: trim@58,4 {
0641 reg = <0x58 1>;
0642 bits = <4 2>;
0643 };
0644 usb_rterm3: trim@59,4 {
0645 reg = <0x59 1>;
0646 bits = <4 2>;
0647 };
0648 usb_sel_t0: trim@54,0 {
0649 reg = <0x54 1>;
0650 bits = <0 4>;
0651 };
0652 usb_sel_t1: trim@55,0 {
0653 reg = <0x55 1>;
0654 bits = <0 4>;
0655 };
0656 usb_sel_t2: trim@58,0 {
0657 reg = <0x58 1>;
0658 bits = <0 4>;
0659 };
0660 usb_sel_t3: trim@59,0 {
0661 reg = <0x59 1>;
0662 bits = <0 4>;
0663 };
0664 usb_hs_i0: trim@56,0 {
0665 reg = <0x56 1>;
0666 bits = <0 4>;
0667 };
0668 usb_hs_i2: trim@5a,0 {
0669 reg = <0x5a 1>;
0670 bits = <0 4>;
0671 };
0672 };
0673 };
0674
0675 xdmac: dma-controller@5fc10000 {
0676 compatible = "socionext,uniphier-xdmac";
0677 reg = <0x5fc10000 0x5300>;
0678 interrupts = <0 188 4>;
0679 dma-channels = <16>;
0680 #dma-cells = <2>;
0681 };
0682
0683 aidet: interrupt-controller@5fc20000 {
0684 compatible = "socionext,uniphier-ld20-aidet";
0685 reg = <0x5fc20000 0x200>;
0686 interrupt-controller;
0687 #interrupt-cells = <2>;
0688 };
0689
0690 gic: interrupt-controller@5fe00000 {
0691 compatible = "arm,gic-v3";
0692 reg = <0x5fe00000 0x10000>, /* GICD */
0693 <0x5fe80000 0x80000>; /* GICR */
0694 interrupt-controller;
0695 #interrupt-cells = <3>;
0696 interrupts = <1 9 4>;
0697 };
0698
0699 sysctrl@61840000 {
0700 compatible = "socionext,uniphier-ld20-sysctrl",
0701 "simple-mfd", "syscon";
0702 reg = <0x61840000 0x10000>;
0703
0704 sys_clk: clock {
0705 compatible = "socionext,uniphier-ld20-clock";
0706 #clock-cells = <1>;
0707 };
0708
0709 sys_rst: reset {
0710 compatible = "socionext,uniphier-ld20-reset";
0711 #reset-cells = <1>;
0712 };
0713
0714 watchdog {
0715 compatible = "socionext,uniphier-wdt";
0716 };
0717
0718 pvtctl: pvtctl {
0719 compatible = "socionext,uniphier-ld20-thermal";
0720 interrupts = <0 3 4>;
0721 #thermal-sensor-cells = <0>;
0722 socionext,tmod-calibration = <0x0f22 0x68ee>;
0723 };
0724 };
0725
0726 eth: ethernet@65000000 {
0727 compatible = "socionext,uniphier-ld20-ave4";
0728 status = "disabled";
0729 reg = <0x65000000 0x8500>;
0730 interrupts = <0 66 4>;
0731 pinctrl-names = "default";
0732 pinctrl-0 = <&pinctrl_ether_rgmii>;
0733 clock-names = "ether";
0734 clocks = <&sys_clk 6>;
0735 reset-names = "ether";
0736 resets = <&sys_rst 6>;
0737 phy-mode = "rgmii-id";
0738 local-mac-address = [00 00 00 00 00 00];
0739 socionext,syscon-phy-mode = <&soc_glue 0>;
0740
0741 mdio: mdio {
0742 #address-cells = <1>;
0743 #size-cells = <0>;
0744 };
0745 };
0746
0747 usb: usb@65a00000 {
0748 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0749 status = "disabled";
0750 reg = <0x65a00000 0xcd00>;
0751 interrupt-names = "host";
0752 interrupts = <0 134 4>;
0753 pinctrl-names = "default";
0754 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
0755 <&pinctrl_usb2>, <&pinctrl_usb3>;
0756 clock-names = "ref", "bus_early", "suspend";
0757 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
0758 resets = <&usb_rst 15>;
0759 phys = <&usb_hsphy0>, <&usb_hsphy1>,
0760 <&usb_hsphy2>, <&usb_hsphy3>,
0761 <&usb_ssphy0>, <&usb_ssphy1>;
0762 dr_mode = "host";
0763 };
0764
0765 usb-glue@65b00000 {
0766 compatible = "socionext,uniphier-ld20-dwc3-glue",
0767 "simple-mfd";
0768 #address-cells = <1>;
0769 #size-cells = <1>;
0770 ranges = <0 0x65b00000 0x400>;
0771
0772 usb_rst: reset@0 {
0773 compatible = "socionext,uniphier-ld20-usb3-reset";
0774 reg = <0x0 0x4>;
0775 #reset-cells = <1>;
0776 clock-names = "link";
0777 clocks = <&sys_clk 14>;
0778 reset-names = "link";
0779 resets = <&sys_rst 14>;
0780 };
0781
0782 usb_vbus0: regulator@100 {
0783 compatible = "socionext,uniphier-ld20-usb3-regulator";
0784 reg = <0x100 0x10>;
0785 clock-names = "link";
0786 clocks = <&sys_clk 14>;
0787 reset-names = "link";
0788 resets = <&sys_rst 14>;
0789 };
0790
0791 usb_vbus1: regulator@110 {
0792 compatible = "socionext,uniphier-ld20-usb3-regulator";
0793 reg = <0x110 0x10>;
0794 clock-names = "link";
0795 clocks = <&sys_clk 14>;
0796 reset-names = "link";
0797 resets = <&sys_rst 14>;
0798 };
0799
0800 usb_vbus2: regulator@120 {
0801 compatible = "socionext,uniphier-ld20-usb3-regulator";
0802 reg = <0x120 0x10>;
0803 clock-names = "link";
0804 clocks = <&sys_clk 14>;
0805 reset-names = "link";
0806 resets = <&sys_rst 14>;
0807 };
0808
0809 usb_vbus3: regulator@130 {
0810 compatible = "socionext,uniphier-ld20-usb3-regulator";
0811 reg = <0x130 0x10>;
0812 clock-names = "link";
0813 clocks = <&sys_clk 14>;
0814 reset-names = "link";
0815 resets = <&sys_rst 14>;
0816 };
0817
0818 usb_hsphy0: hs-phy@200 {
0819 compatible = "socionext,uniphier-ld20-usb3-hsphy";
0820 reg = <0x200 0x10>;
0821 #phy-cells = <0>;
0822 clock-names = "link", "phy";
0823 clocks = <&sys_clk 14>, <&sys_clk 16>;
0824 reset-names = "link", "phy";
0825 resets = <&sys_rst 14>, <&sys_rst 16>;
0826 vbus-supply = <&usb_vbus0>;
0827 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0828 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
0829 <&usb_hs_i0>;
0830 };
0831
0832 usb_hsphy1: hs-phy@210 {
0833 compatible = "socionext,uniphier-ld20-usb3-hsphy";
0834 reg = <0x210 0x10>;
0835 #phy-cells = <0>;
0836 clock-names = "link", "phy";
0837 clocks = <&sys_clk 14>, <&sys_clk 16>;
0838 reset-names = "link", "phy";
0839 resets = <&sys_rst 14>, <&sys_rst 16>;
0840 vbus-supply = <&usb_vbus1>;
0841 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0842 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
0843 <&usb_hs_i0>;
0844 };
0845
0846 usb_hsphy2: hs-phy@220 {
0847 compatible = "socionext,uniphier-ld20-usb3-hsphy";
0848 reg = <0x220 0x10>;
0849 #phy-cells = <0>;
0850 clock-names = "link", "phy";
0851 clocks = <&sys_clk 14>, <&sys_clk 17>;
0852 reset-names = "link", "phy";
0853 resets = <&sys_rst 14>, <&sys_rst 17>;
0854 vbus-supply = <&usb_vbus2>;
0855 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0856 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
0857 <&usb_hs_i2>;
0858 };
0859
0860 usb_hsphy3: hs-phy@230 {
0861 compatible = "socionext,uniphier-ld20-usb3-hsphy";
0862 reg = <0x230 0x10>;
0863 #phy-cells = <0>;
0864 clock-names = "link", "phy";
0865 clocks = <&sys_clk 14>, <&sys_clk 17>;
0866 reset-names = "link", "phy";
0867 resets = <&sys_rst 14>, <&sys_rst 17>;
0868 vbus-supply = <&usb_vbus3>;
0869 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0870 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
0871 <&usb_hs_i2>;
0872 };
0873
0874 usb_ssphy0: ss-phy@300 {
0875 compatible = "socionext,uniphier-ld20-usb3-ssphy";
0876 reg = <0x300 0x10>;
0877 #phy-cells = <0>;
0878 clock-names = "link", "phy";
0879 clocks = <&sys_clk 14>, <&sys_clk 18>;
0880 reset-names = "link", "phy";
0881 resets = <&sys_rst 14>, <&sys_rst 18>;
0882 vbus-supply = <&usb_vbus0>;
0883 };
0884
0885 usb_ssphy1: ss-phy@310 {
0886 compatible = "socionext,uniphier-ld20-usb3-ssphy";
0887 reg = <0x310 0x10>;
0888 #phy-cells = <0>;
0889 clock-names = "link", "phy";
0890 clocks = <&sys_clk 14>, <&sys_clk 19>;
0891 reset-names = "link", "phy";
0892 resets = <&sys_rst 14>, <&sys_rst 19>;
0893 vbus-supply = <&usb_vbus1>;
0894 };
0895 };
0896
0897 pcie: pcie@66000000 {
0898 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
0899 status = "disabled";
0900 reg-names = "dbi", "link", "config";
0901 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
0902 <0x2fff0000 0x10000>;
0903 #address-cells = <3>;
0904 #size-cells = <2>;
0905 clocks = <&sys_clk 24>;
0906 resets = <&sys_rst 24>;
0907 num-lanes = <1>;
0908 num-viewport = <1>;
0909 bus-range = <0x0 0xff>;
0910 device_type = "pci";
0911 ranges =
0912 /* downstream I/O */
0913 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
0914 /* non-prefetchable memory */
0915 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
0916 #interrupt-cells = <1>;
0917 interrupt-names = "dma", "msi";
0918 interrupts = <0 224 4>, <0 225 4>;
0919 interrupt-map-mask = <0 0 0 7>;
0920 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
0921 <0 0 0 2 &pcie_intc 1>, /* INTB */
0922 <0 0 0 3 &pcie_intc 2>, /* INTC */
0923 <0 0 0 4 &pcie_intc 3>; /* INTD */
0924 phy-names = "pcie-phy";
0925 phys = <&pcie_phy>;
0926
0927 pcie_intc: legacy-interrupt-controller {
0928 interrupt-controller;
0929 #interrupt-cells = <1>;
0930 interrupt-parent = <&gic>;
0931 interrupts = <0 226 4>;
0932 };
0933 };
0934
0935 pcie_phy: phy@66038000 {
0936 compatible = "socionext,uniphier-ld20-pcie-phy";
0937 reg = <0x66038000 0x4000>;
0938 #phy-cells = <0>;
0939 clock-names = "link";
0940 clocks = <&sys_clk 24>;
0941 reset-names = "link";
0942 resets = <&sys_rst 24>;
0943 socionext,syscon = <&soc_glue>;
0944 };
0945
0946 nand: nand-controller@68000000 {
0947 compatible = "socionext,uniphier-denali-nand-v5b";
0948 status = "disabled";
0949 reg-names = "nand_data", "denali_reg";
0950 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0951 #address-cells = <1>;
0952 #size-cells = <0>;
0953 interrupts = <0 65 4>;
0954 pinctrl-names = "default";
0955 pinctrl-0 = <&pinctrl_nand>;
0956 clock-names = "nand", "nand_x", "ecc";
0957 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0958 reset-names = "nand", "reg";
0959 resets = <&sys_rst 2>, <&sys_rst 2>;
0960 };
0961 };
0962 };
0963
0964 #include "uniphier-pinctrl.dtsi"
0965
0966 &pinctrl_aout1 {
0967 drive-strength = <4>; /* default: 3.5mA */
0968
0969 ao1dacck {
0970 pins = "AO1DACCK";
0971 drive-strength = <5>; /* 5mA */
0972 };
0973 };
0974
0975 &pinctrl_aoutiec1 {
0976 drive-strength = <4>; /* default: 3.5mA */
0977
0978 ao1arc {
0979 pins = "AO1ARC";
0980 drive-strength = <11>; /* 11mA */
0981 };
0982 };
