0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier LD11 SoC
0004 //
0005 // Copyright (C) 2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/gpio/uniphier-gpio.h>
0010
0011 / {
0012 compatible = "socionext,uniphier-ld11";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015 interrupt-parent = <&gic>;
0016
0017 cpus {
0018 #address-cells = <2>;
0019 #size-cells = <0>;
0020
0021 cpu-map {
0022 cluster0 {
0023 core0 {
0024 cpu = <&cpu0>;
0025 };
0026 core1 {
0027 cpu = <&cpu1>;
0028 };
0029 };
0030 };
0031
0032 cpu0: cpu@0 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a53";
0035 reg = <0 0x000>;
0036 clocks = <&sys_clk 33>;
0037 enable-method = "psci";
0038 operating-points-v2 = <&cluster0_opp>;
0039 };
0040
0041 cpu1: cpu@1 {
0042 device_type = "cpu";
0043 compatible = "arm,cortex-a53";
0044 reg = <0 0x001>;
0045 clocks = <&sys_clk 33>;
0046 enable-method = "psci";
0047 operating-points-v2 = <&cluster0_opp>;
0048 };
0049 };
0050
0051 cluster0_opp: opp-table {
0052 compatible = "operating-points-v2";
0053 opp-shared;
0054
0055 opp-245000000 {
0056 opp-hz = /bits/ 64 <245000000>;
0057 clock-latency-ns = <300>;
0058 };
0059 opp-250000000 {
0060 opp-hz = /bits/ 64 <250000000>;
0061 clock-latency-ns = <300>;
0062 };
0063 opp-490000000 {
0064 opp-hz = /bits/ 64 <490000000>;
0065 clock-latency-ns = <300>;
0066 };
0067 opp-500000000 {
0068 opp-hz = /bits/ 64 <500000000>;
0069 clock-latency-ns = <300>;
0070 };
0071 opp-653334000 {
0072 opp-hz = /bits/ 64 <653334000>;
0073 clock-latency-ns = <300>;
0074 };
0075 opp-666667000 {
0076 opp-hz = /bits/ 64 <666667000>;
0077 clock-latency-ns = <300>;
0078 };
0079 opp-980000000 {
0080 opp-hz = /bits/ 64 <980000000>;
0081 clock-latency-ns = <300>;
0082 };
0083 };
0084
0085 psci {
0086 compatible = "arm,psci-1.0";
0087 method = "smc";
0088 };
0089
0090 clocks {
0091 refclk: ref {
0092 compatible = "fixed-clock";
0093 #clock-cells = <0>;
0094 clock-frequency = <25000000>;
0095 };
0096 };
0097
0098 emmc_pwrseq: emmc-pwrseq {
0099 compatible = "mmc-pwrseq-emmc";
0100 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
0101 };
0102
0103 timer {
0104 compatible = "arm,armv8-timer";
0105 interrupts = <1 13 4>,
0106 <1 14 4>,
0107 <1 11 4>,
0108 <1 10 4>;
0109 };
0110
0111 reserved-memory {
0112 #address-cells = <2>;
0113 #size-cells = <2>;
0114 ranges;
0115
0116 secure-memory@81000000 {
0117 reg = <0x0 0x81000000 0x0 0x01000000>;
0118 no-map;
0119 };
0120 };
0121
0122 soc@0 {
0123 compatible = "simple-bus";
0124 #address-cells = <1>;
0125 #size-cells = <1>;
0126 ranges = <0 0 0 0xffffffff>;
0127
0128 spi0: spi@54006000 {
0129 compatible = "socionext,uniphier-scssi";
0130 status = "disabled";
0131 reg = <0x54006000 0x100>;
0132 #address-cells = <1>;
0133 #size-cells = <0>;
0134 interrupts = <0 39 4>;
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&pinctrl_spi0>;
0137 clocks = <&peri_clk 11>;
0138 resets = <&peri_rst 11>;
0139 };
0140
0141 spi1: spi@54006100 {
0142 compatible = "socionext,uniphier-scssi";
0143 status = "disabled";
0144 reg = <0x54006100 0x100>;
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 interrupts = <0 216 4>;
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_spi1>;
0150 clocks = <&peri_clk 12>;
0151 resets = <&peri_rst 12>;
0152 };
0153
0154 serial0: serial@54006800 {
0155 compatible = "socionext,uniphier-uart";
0156 status = "disabled";
0157 reg = <0x54006800 0x40>;
0158 interrupts = <0 33 4>;
0159 pinctrl-names = "default";
0160 pinctrl-0 = <&pinctrl_uart0>;
0161 clocks = <&peri_clk 0>;
0162 resets = <&peri_rst 0>;
0163 };
0164
0165 serial1: serial@54006900 {
0166 compatible = "socionext,uniphier-uart";
0167 status = "disabled";
0168 reg = <0x54006900 0x40>;
0169 interrupts = <0 35 4>;
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&pinctrl_uart1>;
0172 clocks = <&peri_clk 1>;
0173 resets = <&peri_rst 1>;
0174 };
0175
0176 serial2: serial@54006a00 {
0177 compatible = "socionext,uniphier-uart";
0178 status = "disabled";
0179 reg = <0x54006a00 0x40>;
0180 interrupts = <0 37 4>;
0181 pinctrl-names = "default";
0182 pinctrl-0 = <&pinctrl_uart2>;
0183 clocks = <&peri_clk 2>;
0184 resets = <&peri_rst 2>;
0185 };
0186
0187 serial3: serial@54006b00 {
0188 compatible = "socionext,uniphier-uart";
0189 status = "disabled";
0190 reg = <0x54006b00 0x40>;
0191 interrupts = <0 177 4>;
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_uart3>;
0194 clocks = <&peri_clk 3>;
0195 resets = <&peri_rst 3>;
0196 };
0197
0198 gpio: gpio@55000000 {
0199 compatible = "socionext,uniphier-gpio";
0200 reg = <0x55000000 0x200>;
0201 interrupt-parent = <&aidet>;
0202 interrupt-controller;
0203 #interrupt-cells = <2>;
0204 gpio-controller;
0205 #gpio-cells = <2>;
0206 gpio-ranges = <&pinctrl 0 0 0>,
0207 <&pinctrl 43 0 0>,
0208 <&pinctrl 51 0 0>,
0209 <&pinctrl 96 0 0>,
0210 <&pinctrl 160 0 0>,
0211 <&pinctrl 184 0 0>;
0212 gpio-ranges-group-names = "gpio_range0",
0213 "gpio_range1",
0214 "gpio_range2",
0215 "gpio_range3",
0216 "gpio_range4",
0217 "gpio_range5";
0218 ngpios = <200>;
0219 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
0220 <21 217 3>;
0221 };
0222
0223 audio@56000000 {
0224 compatible = "socionext,uniphier-ld11-aio";
0225 reg = <0x56000000 0x80000>;
0226 interrupts = <0 144 4>;
0227 pinctrl-names = "default";
0228 pinctrl-0 = <&pinctrl_aout1>,
0229 <&pinctrl_aoutiec1>;
0230 clock-names = "aio";
0231 clocks = <&sys_clk 40>;
0232 reset-names = "aio";
0233 resets = <&sys_rst 40>;
0234 #sound-dai-cells = <1>;
0235 socionext,syscon = <&soc_glue>;
0236
0237 i2s_port0: port@0 {
0238 i2s_hdmi: endpoint {
0239 };
0240 };
0241
0242 i2s_port1: port@1 {
0243 i2s_pcmin2: endpoint {
0244 };
0245 };
0246
0247 i2s_port2: port@2 {
0248 i2s_line: endpoint {
0249 dai-format = "i2s";
0250 remote-endpoint = <&evea_line>;
0251 };
0252 };
0253
0254 i2s_port3: port@3 {
0255 i2s_hpcmout1: endpoint {
0256 };
0257 };
0258
0259 i2s_port4: port@4 {
0260 i2s_hp: endpoint {
0261 dai-format = "i2s";
0262 remote-endpoint = <&evea_hp>;
0263 };
0264 };
0265
0266 spdif_port0: port@5 {
0267 spdif_hiecout1: endpoint {
0268 };
0269 };
0270
0271 src_port0: port@6 {
0272 i2s_epcmout2: endpoint {
0273 };
0274 };
0275
0276 src_port1: port@7 {
0277 i2s_epcmout3: endpoint {
0278 };
0279 };
0280
0281 comp_spdif_port0: port@8 {
0282 comp_spdif_hiecout1: endpoint {
0283 };
0284 };
0285 };
0286
0287 codec@57900000 {
0288 compatible = "socionext,uniphier-evea";
0289 reg = <0x57900000 0x1000>;
0290 clock-names = "evea", "exiv";
0291 clocks = <&sys_clk 41>, <&sys_clk 42>;
0292 reset-names = "evea", "exiv", "adamv";
0293 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
0294 #sound-dai-cells = <1>;
0295
0296 port@0 {
0297 evea_line: endpoint {
0298 remote-endpoint = <&i2s_line>;
0299 };
0300 };
0301
0302 port@1 {
0303 evea_hp: endpoint {
0304 remote-endpoint = <&i2s_hp>;
0305 };
0306 };
0307 };
0308
0309 adamv@57920000 {
0310 compatible = "socionext,uniphier-ld11-adamv",
0311 "simple-mfd", "syscon";
0312 reg = <0x57920000 0x1000>;
0313
0314 adamv_rst: reset {
0315 compatible = "socionext,uniphier-ld11-adamv-reset";
0316 #reset-cells = <1>;
0317 };
0318 };
0319
0320 i2c0: i2c@58780000 {
0321 compatible = "socionext,uniphier-fi2c";
0322 status = "disabled";
0323 reg = <0x58780000 0x80>;
0324 #address-cells = <1>;
0325 #size-cells = <0>;
0326 interrupts = <0 41 4>;
0327 pinctrl-names = "default";
0328 pinctrl-0 = <&pinctrl_i2c0>;
0329 clocks = <&peri_clk 4>;
0330 resets = <&peri_rst 4>;
0331 clock-frequency = <100000>;
0332 };
0333
0334 i2c1: i2c@58781000 {
0335 compatible = "socionext,uniphier-fi2c";
0336 status = "disabled";
0337 reg = <0x58781000 0x80>;
0338 #address-cells = <1>;
0339 #size-cells = <0>;
0340 interrupts = <0 42 4>;
0341 pinctrl-names = "default";
0342 pinctrl-0 = <&pinctrl_i2c1>;
0343 clocks = <&peri_clk 5>;
0344 resets = <&peri_rst 5>;
0345 clock-frequency = <100000>;
0346 };
0347
0348 i2c2: i2c@58782000 {
0349 compatible = "socionext,uniphier-fi2c";
0350 reg = <0x58782000 0x80>;
0351 #address-cells = <1>;
0352 #size-cells = <0>;
0353 interrupts = <0 43 4>;
0354 clocks = <&peri_clk 6>;
0355 resets = <&peri_rst 6>;
0356 clock-frequency = <400000>;
0357 };
0358
0359 i2c3: i2c@58783000 {
0360 compatible = "socionext,uniphier-fi2c";
0361 status = "disabled";
0362 reg = <0x58783000 0x80>;
0363 #address-cells = <1>;
0364 #size-cells = <0>;
0365 interrupts = <0 44 4>;
0366 pinctrl-names = "default";
0367 pinctrl-0 = <&pinctrl_i2c3>;
0368 clocks = <&peri_clk 7>;
0369 resets = <&peri_rst 7>;
0370 clock-frequency = <100000>;
0371 };
0372
0373 i2c4: i2c@58784000 {
0374 compatible = "socionext,uniphier-fi2c";
0375 status = "disabled";
0376 reg = <0x58784000 0x80>;
0377 #address-cells = <1>;
0378 #size-cells = <0>;
0379 interrupts = <0 45 4>;
0380 pinctrl-names = "default";
0381 pinctrl-0 = <&pinctrl_i2c4>;
0382 clocks = <&peri_clk 8>;
0383 resets = <&peri_rst 8>;
0384 clock-frequency = <100000>;
0385 };
0386
0387 i2c5: i2c@58785000 {
0388 compatible = "socionext,uniphier-fi2c";
0389 reg = <0x58785000 0x80>;
0390 #address-cells = <1>;
0391 #size-cells = <0>;
0392 interrupts = <0 25 4>;
0393 clocks = <&peri_clk 9>;
0394 resets = <&peri_rst 9>;
0395 clock-frequency = <400000>;
0396 };
0397
0398 system_bus: system-bus@58c00000 {
0399 compatible = "socionext,uniphier-system-bus";
0400 status = "disabled";
0401 reg = <0x58c00000 0x400>;
0402 #address-cells = <2>;
0403 #size-cells = <1>;
0404 pinctrl-names = "default";
0405 pinctrl-0 = <&pinctrl_system_bus>;
0406 };
0407
0408 smpctrl@59801000 {
0409 compatible = "socionext,uniphier-smpctrl";
0410 reg = <0x59801000 0x400>;
0411 };
0412
0413 sdctrl@59810000 {
0414 compatible = "socionext,uniphier-ld11-sdctrl",
0415 "simple-mfd", "syscon";
0416 reg = <0x59810000 0x400>;
0417
0418 sd_rst: reset {
0419 compatible = "socionext,uniphier-ld11-sd-reset";
0420 #reset-cells = <1>;
0421 };
0422 };
0423
0424 perictrl@59820000 {
0425 compatible = "socionext,uniphier-ld11-perictrl",
0426 "simple-mfd", "syscon";
0427 reg = <0x59820000 0x200>;
0428
0429 peri_clk: clock {
0430 compatible = "socionext,uniphier-ld11-peri-clock";
0431 #clock-cells = <1>;
0432 };
0433
0434 peri_rst: reset {
0435 compatible = "socionext,uniphier-ld11-peri-reset";
0436 #reset-cells = <1>;
0437 };
0438 };
0439
0440 emmc: mmc@5a000000 {
0441 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
0442 reg = <0x5a000000 0x400>;
0443 interrupts = <0 78 4>;
0444 pinctrl-names = "default";
0445 pinctrl-0 = <&pinctrl_emmc>;
0446 clocks = <&sys_clk 4>;
0447 resets = <&sys_rst 4>;
0448 bus-width = <8>;
0449 mmc-ddr-1_8v;
0450 mmc-hs200-1_8v;
0451 mmc-pwrseq = <&emmc_pwrseq>;
0452 cdns,phy-input-delay-legacy = <9>;
0453 cdns,phy-input-delay-mmc-highspeed = <2>;
0454 cdns,phy-input-delay-mmc-ddr = <3>;
0455 cdns,phy-dll-delay-sdclk = <21>;
0456 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
0457 };
0458
0459 usb0: usb@5a800100 {
0460 compatible = "socionext,uniphier-ehci", "generic-ehci";
0461 status = "disabled";
0462 reg = <0x5a800100 0x100>;
0463 interrupts = <0 243 4>;
0464 pinctrl-names = "default";
0465 pinctrl-0 = <&pinctrl_usb0>;
0466 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
0467 <&mio_clk 12>;
0468 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
0469 <&mio_rst 12>;
0470 phy-names = "usb";
0471 phys = <&usb_phy0>;
0472 has-transaction-translator;
0473 };
0474
0475 usb1: usb@5a810100 {
0476 compatible = "socionext,uniphier-ehci", "generic-ehci";
0477 status = "disabled";
0478 reg = <0x5a810100 0x100>;
0479 interrupts = <0 244 4>;
0480 pinctrl-names = "default";
0481 pinctrl-0 = <&pinctrl_usb1>;
0482 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
0483 <&mio_clk 13>;
0484 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
0485 <&mio_rst 13>;
0486 phy-names = "usb";
0487 phys = <&usb_phy1>;
0488 has-transaction-translator;
0489 };
0490
0491 usb2: usb@5a820100 {
0492 compatible = "socionext,uniphier-ehci", "generic-ehci";
0493 status = "disabled";
0494 reg = <0x5a820100 0x100>;
0495 interrupts = <0 245 4>;
0496 pinctrl-names = "default";
0497 pinctrl-0 = <&pinctrl_usb2>;
0498 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
0499 <&mio_clk 14>;
0500 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
0501 <&mio_rst 14>;
0502 phy-names = "usb";
0503 phys = <&usb_phy2>;
0504 has-transaction-translator;
0505 };
0506
0507 mioctrl@5b3e0000 {
0508 compatible = "socionext,uniphier-ld11-mioctrl",
0509 "simple-mfd", "syscon";
0510 reg = <0x5b3e0000 0x800>;
0511
0512 mio_clk: clock {
0513 compatible = "socionext,uniphier-ld11-mio-clock";
0514 #clock-cells = <1>;
0515 };
0516
0517 mio_rst: reset {
0518 compatible = "socionext,uniphier-ld11-mio-reset";
0519 #reset-cells = <1>;
0520 resets = <&sys_rst 7>;
0521 };
0522 };
0523
0524 soc_glue: soc-glue@5f800000 {
0525 compatible = "socionext,uniphier-ld11-soc-glue",
0526 "simple-mfd", "syscon";
0527 reg = <0x5f800000 0x2000>;
0528
0529 pinctrl: pinctrl {
0530 compatible = "socionext,uniphier-ld11-pinctrl";
0531 };
0532
0533 usb-phy {
0534 compatible = "socionext,uniphier-ld11-usb2-phy";
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537
0538 usb_phy0: phy@0 {
0539 reg = <0>;
0540 #phy-cells = <0>;
0541 };
0542
0543 usb_phy1: phy@1 {
0544 reg = <1>;
0545 #phy-cells = <0>;
0546 };
0547
0548 usb_phy2: phy@2 {
0549 reg = <2>;
0550 #phy-cells = <0>;
0551 };
0552 };
0553 };
0554
0555 soc-glue@5f900000 {
0556 compatible = "socionext,uniphier-ld11-soc-glue-debug",
0557 "simple-mfd";
0558 #address-cells = <1>;
0559 #size-cells = <1>;
0560 ranges = <0 0x5f900000 0x2000>;
0561
0562 efuse@100 {
0563 compatible = "socionext,uniphier-efuse";
0564 reg = <0x100 0x28>;
0565 };
0566
0567 efuse@200 {
0568 compatible = "socionext,uniphier-efuse";
0569 reg = <0x200 0x68>;
0570 };
0571 };
0572
0573 xdmac: dma-controller@5fc10000 {
0574 compatible = "socionext,uniphier-xdmac";
0575 reg = <0x5fc10000 0x5300>;
0576 interrupts = <0 188 4>;
0577 dma-channels = <16>;
0578 #dma-cells = <2>;
0579 };
0580
0581 aidet: interrupt-controller@5fc20000 {
0582 compatible = "socionext,uniphier-ld11-aidet";
0583 reg = <0x5fc20000 0x200>;
0584 interrupt-controller;
0585 #interrupt-cells = <2>;
0586 };
0587
0588 gic: interrupt-controller@5fe00000 {
0589 compatible = "arm,gic-v3";
0590 reg = <0x5fe00000 0x10000>, /* GICD */
0591 <0x5fe40000 0x80000>; /* GICR */
0592 interrupt-controller;
0593 #interrupt-cells = <3>;
0594 interrupts = <1 9 4>;
0595 };
0596
0597 sysctrl@61840000 {
0598 compatible = "socionext,uniphier-ld11-sysctrl",
0599 "simple-mfd", "syscon";
0600 reg = <0x61840000 0x10000>;
0601
0602 sys_clk: clock {
0603 compatible = "socionext,uniphier-ld11-clock";
0604 #clock-cells = <1>;
0605 };
0606
0607 sys_rst: reset {
0608 compatible = "socionext,uniphier-ld11-reset";
0609 #reset-cells = <1>;
0610 };
0611
0612 watchdog {
0613 compatible = "socionext,uniphier-wdt";
0614 };
0615 };
0616
0617 eth: ethernet@65000000 {
0618 compatible = "socionext,uniphier-ld11-ave4";
0619 status = "disabled";
0620 reg = <0x65000000 0x8500>;
0621 interrupts = <0 66 4>;
0622 clock-names = "ether";
0623 clocks = <&sys_clk 6>;
0624 reset-names = "ether";
0625 resets = <&sys_rst 6>;
0626 phy-mode = "internal";
0627 local-mac-address = [00 00 00 00 00 00];
0628 socionext,syscon-phy-mode = <&soc_glue 0>;
0629
0630 mdio: mdio {
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633 };
0634 };
0635
0636 nand: nand-controller@68000000 {
0637 compatible = "socionext,uniphier-denali-nand-v5b";
0638 status = "disabled";
0639 reg-names = "nand_data", "denali_reg";
0640 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0641 #address-cells = <1>;
0642 #size-cells = <0>;
0643 interrupts = <0 65 4>;
0644 pinctrl-names = "default";
0645 pinctrl-0 = <&pinctrl_nand>;
0646 clock-names = "nand", "nand_x", "ecc";
0647 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0648 reset-names = "nand", "reg";
0649 resets = <&sys_rst 2>, <&sys_rst 2>;
0650 };
0651 };
0652 };
0653
0654 #include "uniphier-pinctrl.dtsi"
0655
0656 &pinctrl_aoutiec1 {
0657 drive-strength = <4>; /* default: 4mA */
0658
0659 ao1arc {
0660 pins = "AO1ARC";
0661 drive-strength = <8>; /* 8mA */
0662 };
0663 };
