0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
0004 */
0005
0006 #include "rk356x.dtsi"
0007
0008 / {
0009 compatible = "rockchip,rk3568";
0010
0011 sata0: sata@fc000000 {
0012 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
0013 reg = <0 0xfc000000 0 0x1000>;
0014 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
0015 <&cru CLK_SATA0_RXOOB>;
0016 clock-names = "sata", "pmalive", "rxoob";
0017 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0018 phys = <&combphy0 PHY_TYPE_SATA>;
0019 phy-names = "sata-phy";
0020 ports-implemented = <0x1>;
0021 power-domains = <&power RK3568_PD_PIPE>;
0022 status = "disabled";
0023 };
0024
0025 pipe_phy_grf0: syscon@fdc70000 {
0026 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
0027 reg = <0x0 0xfdc70000 0x0 0x1000>;
0028 };
0029
0030 qos_pcie3x1: qos@fe190080 {
0031 compatible = "rockchip,rk3568-qos", "syscon";
0032 reg = <0x0 0xfe190080 0x0 0x20>;
0033 };
0034
0035 qos_pcie3x2: qos@fe190100 {
0036 compatible = "rockchip,rk3568-qos", "syscon";
0037 reg = <0x0 0xfe190100 0x0 0x20>;
0038 };
0039
0040 qos_sata0: qos@fe190200 {
0041 compatible = "rockchip,rk3568-qos", "syscon";
0042 reg = <0x0 0xfe190200 0x0 0x20>;
0043 };
0044
0045 gmac0: ethernet@fe2a0000 {
0046 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
0047 reg = <0x0 0xfe2a0000 0x0 0x10000>;
0048 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0049 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0050 interrupt-names = "macirq", "eth_wake_irq";
0051 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
0052 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
0053 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
0054 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
0055 clock-names = "stmmaceth", "mac_clk_rx",
0056 "mac_clk_tx", "clk_mac_refout",
0057 "aclk_mac", "pclk_mac",
0058 "clk_mac_speed", "ptp_ref";
0059 resets = <&cru SRST_A_GMAC0>;
0060 reset-names = "stmmaceth";
0061 rockchip,grf = <&grf>;
0062 snps,axi-config = <&gmac0_stmmac_axi_setup>;
0063 snps,mixed-burst;
0064 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
0065 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
0066 snps,tso;
0067 status = "disabled";
0068
0069 mdio0: mdio {
0070 compatible = "snps,dwmac-mdio";
0071 #address-cells = <0x1>;
0072 #size-cells = <0x0>;
0073 };
0074
0075 gmac0_stmmac_axi_setup: stmmac-axi-config {
0076 snps,blen = <0 0 0 0 16 8 4>;
0077 snps,rd_osr_lmt = <8>;
0078 snps,wr_osr_lmt = <4>;
0079 };
0080
0081 gmac0_mtl_rx_setup: rx-queues-config {
0082 snps,rx-queues-to-use = <1>;
0083 queue0 {};
0084 };
0085
0086 gmac0_mtl_tx_setup: tx-queues-config {
0087 snps,tx-queues-to-use = <1>;
0088 queue0 {};
0089 };
0090 };
0091
0092 combphy0: phy@fe820000 {
0093 compatible = "rockchip,rk3568-naneng-combphy";
0094 reg = <0x0 0xfe820000 0x0 0x100>;
0095 clocks = <&pmucru CLK_PCIEPHY0_REF>,
0096 <&cru PCLK_PIPEPHY0>,
0097 <&cru PCLK_PIPE>;
0098 clock-names = "ref", "apb", "pipe";
0099 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
0100 assigned-clock-rates = <100000000>;
0101 resets = <&cru SRST_PIPEPHY0>;
0102 rockchip,pipe-grf = <&pipegrf>;
0103 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
0104 #phy-cells = <1>;
0105 status = "disabled";
0106 };
0107 };
0108
0109 &cpu0_opp_table {
0110 opp-1992000000 {
0111 opp-hz = /bits/ 64 <1992000000>;
0112 opp-microvolt = <1150000 1150000 1150000>;
0113 };
0114 };
0115
0116 &pipegrf {
0117 compatible = "rockchip,rk3568-pipe-grf", "syscon";
0118 };
0119
0120 &power {
0121 power-domain@RK3568_PD_PIPE {
0122 reg = <RK3568_PD_PIPE>;
0123 clocks = <&cru PCLK_PIPE>;
0124 pm_qos = <&qos_pcie2x1>,
0125 <&qos_pcie3x1>,
0126 <&qos_pcie3x2>,
0127 <&qos_sata0>,
0128 <&qos_sata1>,
0129 <&qos_sata2>,
0130 <&qos_usb3_0>,
0131 <&qos_usb3_1>;
0132 #power-domain-cells = <0>;
0133 };
0134 };
0135
0136 &usb_host0_xhci {
0137 phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
0138 phy-names = "usb2-phy", "usb3-phy";
0139 };
0140
0141 &vop {
0142 compatible = "rockchip,rk3568-vop";
0143 };
