0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
0004 */
0005
0006 / {
0007 cluster0_opp: opp-table-0 {
0008 compatible = "operating-points-v2";
0009 opp-shared;
0010
0011 opp00 {
0012 opp-hz = /bits/ 64 <408000000>;
0013 opp-microvolt = <825000 825000 1250000>;
0014 clock-latency-ns = <40000>;
0015 };
0016 opp01 {
0017 opp-hz = /bits/ 64 <600000000>;
0018 opp-microvolt = <825000 825000 1250000>;
0019 };
0020 opp02 {
0021 opp-hz = /bits/ 64 <816000000>;
0022 opp-microvolt = <850000 850000 1250000>;
0023 };
0024 opp03 {
0025 opp-hz = /bits/ 64 <1008000000>;
0026 opp-microvolt = <925000 925000 1250000>;
0027 };
0028 opp04 {
0029 opp-hz = /bits/ 64 <1200000000>;
0030 opp-microvolt = <1000000 1000000 1250000>;
0031 };
0032 opp05 {
0033 opp-hz = /bits/ 64 <1416000000>;
0034 opp-microvolt = <1125000 1125000 1250000>;
0035 };
0036 };
0037
0038 cluster1_opp: opp-table-1 {
0039 compatible = "operating-points-v2";
0040 opp-shared;
0041
0042 opp00 {
0043 opp-hz = /bits/ 64 <408000000>;
0044 opp-microvolt = <825000 825000 1250000>;
0045 clock-latency-ns = <40000>;
0046 };
0047 opp01 {
0048 opp-hz = /bits/ 64 <600000000>;
0049 opp-microvolt = <825000 825000 1250000>;
0050 };
0051 opp02 {
0052 opp-hz = /bits/ 64 <816000000>;
0053 opp-microvolt = <825000 825000 1250000>;
0054 };
0055 opp03 {
0056 opp-hz = /bits/ 64 <1008000000>;
0057 opp-microvolt = <875000 875000 1250000>;
0058 };
0059 opp04 {
0060 opp-hz = /bits/ 64 <1200000000>;
0061 opp-microvolt = <950000 950000 1250000>;
0062 };
0063 opp05 {
0064 opp-hz = /bits/ 64 <1416000000>;
0065 opp-microvolt = <1025000 1025000 1250000>;
0066 };
0067 opp06 {
0068 opp-hz = /bits/ 64 <1608000000>;
0069 opp-microvolt = <1100000 1100000 1250000>;
0070 };
0071 opp07 {
0072 opp-hz = /bits/ 64 <1800000000>;
0073 opp-microvolt = <1200000 1200000 1250000>;
0074 };
0075 };
0076
0077 gpu_opp_table: opp-table-2 {
0078 compatible = "operating-points-v2";
0079
0080 opp00 {
0081 opp-hz = /bits/ 64 <200000000>;
0082 opp-microvolt = <825000 825000 1150000>;
0083 };
0084 opp01 {
0085 opp-hz = /bits/ 64 <297000000>;
0086 opp-microvolt = <825000 825000 1150000>;
0087 };
0088 opp02 {
0089 opp-hz = /bits/ 64 <400000000>;
0090 opp-microvolt = <825000 825000 1150000>;
0091 };
0092 opp03 {
0093 opp-hz = /bits/ 64 <500000000>;
0094 opp-microvolt = <875000 875000 1150000>;
0095 };
0096 opp04 {
0097 opp-hz = /bits/ 64 <600000000>;
0098 opp-microvolt = <925000 925000 1150000>;
0099 };
0100 opp05 {
0101 opp-hz = /bits/ 64 <800000000>;
0102 opp-microvolt = <1100000 1100000 1150000>;
0103 };
0104 };
0105 };
0106
0107 &cpu_l0 {
0108 operating-points-v2 = <&cluster0_opp>;
0109 };
0110
0111 &cpu_l1 {
0112 operating-points-v2 = <&cluster0_opp>;
0113 };
0114
0115 &cpu_l2 {
0116 operating-points-v2 = <&cluster0_opp>;
0117 };
0118
0119 &cpu_l3 {
0120 operating-points-v2 = <&cluster0_opp>;
0121 };
0122
0123 &cpu_b0 {
0124 operating-points-v2 = <&cluster1_opp>;
0125 };
0126
0127 &cpu_b1 {
0128 operating-points-v2 = <&cluster1_opp>;
0129 };
0130
0131 &gpu {
0132 operating-points-v2 = <&gpu_opp_table>;
0133 };
