0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Gru (and derivatives) board device tree source
0004 *
0005 * Copyright 2016-2017 Google, Inc
0006 */
0007
0008 #include <dt-bindings/input/input.h>
0009 #include "rk3399.dtsi"
0010 #include "rk3399-op1-opp.dtsi"
0011
0012 / {
0013 aliases {
0014 mmc0 = &sdmmc;
0015 mmc1 = &sdhci;
0016 };
0017
0018 chosen {
0019 stdout-path = "serial2:115200n8";
0020 };
0021
0022 /*
0023 * Power Tree
0024 *
0025 * In general an attempt is made to include all rails called out by
0026 * the schematic as long as those rails interact in some way with
0027 * the AP. AKA:
0028 * - Rails that only connect to the EC (or devices that the EC talks to)
0029 * are not included.
0030 * - Rails _are_ included if the rails go to the AP even if the AP
0031 * doesn't currently care about them / they are always on. The idea
0032 * here is that it makes it easier to map to the schematic or extend
0033 * later.
0034 *
0035 * If two rails are substantially the same from the AP's point of
0036 * view, though, we won't create a full fixed regulator. We'll just
0037 * put the child rail as an alias of the parent rail. Sometimes rails
0038 * look the same to the AP because one of these is true:
0039 * - The EC controls the enable and the EC always enables a rail as
0040 * long as the AP is running.
0041 * - The rails are actually connected to each other by a jumper and
0042 * the distinction is just there to add clarity/flexibility to the
0043 * schematic.
0044 */
0045
0046 ppvar_sys: ppvar-sys {
0047 compatible = "regulator-fixed";
0048 regulator-name = "ppvar_sys";
0049 regulator-always-on;
0050 regulator-boot-on;
0051 };
0052
0053 pp1200_lpddr: pp1200-lpddr {
0054 compatible = "regulator-fixed";
0055 regulator-name = "pp1200_lpddr";
0056
0057 /* EC turns on w/ lpddr_pwr_en; always on for AP */
0058 regulator-always-on;
0059 regulator-boot-on;
0060 regulator-min-microvolt = <1200000>;
0061 regulator-max-microvolt = <1200000>;
0062
0063 vin-supply = <&ppvar_sys>;
0064 };
0065
0066 pp1800: pp1800 {
0067 compatible = "regulator-fixed";
0068 regulator-name = "pp1800";
0069
0070 /* Always on when ppvar_sys shows power good */
0071 regulator-always-on;
0072 regulator-boot-on;
0073 regulator-min-microvolt = <1800000>;
0074 regulator-max-microvolt = <1800000>;
0075
0076 vin-supply = <&ppvar_sys>;
0077 };
0078
0079 pp3300: pp3300 {
0080 compatible = "regulator-fixed";
0081 regulator-name = "pp3300";
0082
0083 /* Always on; plain and simple */
0084 regulator-always-on;
0085 regulator-boot-on;
0086 regulator-min-microvolt = <3300000>;
0087 regulator-max-microvolt = <3300000>;
0088
0089 vin-supply = <&ppvar_sys>;
0090 };
0091
0092 pp5000: pp5000 {
0093 compatible = "regulator-fixed";
0094 regulator-name = "pp5000";
0095
0096 /* EC turns on w/ pp5000_en; always on for AP */
0097 regulator-always-on;
0098 regulator-boot-on;
0099 regulator-min-microvolt = <5000000>;
0100 regulator-max-microvolt = <5000000>;
0101
0102 vin-supply = <&ppvar_sys>;
0103 };
0104
0105 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
0106 compatible = "pwm-regulator";
0107 regulator-name = "ppvar_bigcpu_pwm";
0108
0109 pwms = <&pwm1 0 3337 0>;
0110 pwm-supply = <&ppvar_sys>;
0111 pwm-dutycycle-range = <100 0>;
0112 pwm-dutycycle-unit = <100>;
0113
0114 /* EC turns on w/ ap_core_en; always on for AP */
0115 regulator-always-on;
0116 regulator-boot-on;
0117 regulator-min-microvolt = <800107>;
0118 regulator-max-microvolt = <1302232>;
0119 };
0120
0121 ppvar_bigcpu: ppvar-bigcpu {
0122 compatible = "vctrl-regulator";
0123 regulator-name = "ppvar_bigcpu";
0124
0125 regulator-min-microvolt = <800107>;
0126 regulator-max-microvolt = <1302232>;
0127
0128 ctrl-supply = <&ppvar_bigcpu_pwm>;
0129 ctrl-voltage-range = <800107 1302232>;
0130
0131 regulator-settling-time-up-us = <322>;
0132 };
0133
0134 ppvar_litcpu_pwm: ppvar-litcpu-pwm {
0135 compatible = "pwm-regulator";
0136 regulator-name = "ppvar_litcpu_pwm";
0137
0138 pwms = <&pwm2 0 3337 0>;
0139 pwm-supply = <&ppvar_sys>;
0140 pwm-dutycycle-range = <100 0>;
0141 pwm-dutycycle-unit = <100>;
0142
0143 /* EC turns on w/ ap_core_en; always on for AP */
0144 regulator-always-on;
0145 regulator-boot-on;
0146 regulator-min-microvolt = <797743>;
0147 regulator-max-microvolt = <1307837>;
0148 };
0149
0150 ppvar_litcpu: ppvar-litcpu {
0151 compatible = "vctrl-regulator";
0152 regulator-name = "ppvar_litcpu";
0153
0154 regulator-min-microvolt = <797743>;
0155 regulator-max-microvolt = <1307837>;
0156
0157 ctrl-supply = <&ppvar_litcpu_pwm>;
0158 ctrl-voltage-range = <797743 1307837>;
0159
0160 regulator-settling-time-up-us = <384>;
0161 };
0162
0163 ppvar_gpu_pwm: ppvar-gpu-pwm {
0164 compatible = "pwm-regulator";
0165 regulator-name = "ppvar_gpu_pwm";
0166
0167 pwms = <&pwm0 0 3337 0>;
0168 pwm-supply = <&ppvar_sys>;
0169 pwm-dutycycle-range = <100 0>;
0170 pwm-dutycycle-unit = <100>;
0171
0172 /* EC turns on w/ ap_core_en; always on for AP */
0173 regulator-always-on;
0174 regulator-boot-on;
0175 regulator-min-microvolt = <786384>;
0176 regulator-max-microvolt = <1217747>;
0177 };
0178
0179 ppvar_gpu: ppvar-gpu {
0180 compatible = "vctrl-regulator";
0181 regulator-name = "ppvar_gpu";
0182
0183 regulator-min-microvolt = <786384>;
0184 regulator-max-microvolt = <1217747>;
0185
0186 ctrl-supply = <&ppvar_gpu_pwm>;
0187 ctrl-voltage-range = <786384 1217747>;
0188
0189 regulator-settling-time-up-us = <390>;
0190 };
0191
0192 /* EC turns on w/ pp900_ddrpll_en */
0193 pp900_ddrpll: pp900-ap {
0194 };
0195
0196 /* EC turns on w/ pp900_pll_en */
0197 pp900_pll: pp900-ap {
0198 };
0199
0200 /* EC turns on w/ pp900_pmu_en */
0201 pp900_pmu: pp900-ap {
0202 };
0203
0204 /* EC turns on w/ pp1800_s0_en_l */
0205 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
0206 };
0207
0208 /* EC turns on w/ pp1800_avdd_en_l */
0209 pp1800_avdd: pp1800 {
0210 };
0211
0212 /* EC turns on w/ pp1800_lid_en_l */
0213 pp1800_lid: pp1800_mic: pp1800 {
0214 };
0215
0216 /* EC turns on w/ lpddr_pwr_en */
0217 pp1800_lpddr: pp1800 {
0218 };
0219
0220 /* EC turns on w/ pp1800_pmu_en_l */
0221 pp1800_pmu: pp1800 {
0222 };
0223
0224 /* EC turns on w/ pp1800_usb_en_l */
0225 pp1800_usb: pp1800 {
0226 };
0227
0228 pp3000_sd_slot: pp3000-sd-slot {
0229 compatible = "regulator-fixed";
0230 regulator-name = "pp3000_sd_slot";
0231 pinctrl-names = "default";
0232 pinctrl-0 = <&sd_slot_pwr_en>;
0233
0234 enable-active-high;
0235 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
0236
0237 vin-supply = <&pp3000>;
0238 };
0239
0240 /*
0241 * Technically, this is a small abuse of 'regulator-gpio'; this
0242 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
0243 * always on though, so it is sufficient to simply control the mux
0244 * here.
0245 */
0246 ppvar_sd_card_io: ppvar-sd-card-io {
0247 compatible = "regulator-gpio";
0248 regulator-name = "ppvar_sd_card_io";
0249 pinctrl-names = "default";
0250 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
0251
0252 enable-active-high;
0253 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
0254 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
0255 states = <1800000 0x1>,
0256 <3000000 0x0>;
0257
0258 regulator-min-microvolt = <1800000>;
0259 regulator-max-microvolt = <3000000>;
0260 };
0261
0262 /* EC turns on w/ pp3300_trackpad_en_l */
0263 pp3300_trackpad: pp3300-trackpad {
0264 };
0265
0266 /* EC turns on w/ usb_a_en */
0267 pp5000_usb_a_vbus: pp5000 {
0268 };
0269
0270 ap_rtc_clk: ap-rtc-clk {
0271 compatible = "fixed-clock";
0272 clock-frequency = <32768>;
0273 clock-output-names = "xin32k";
0274 #clock-cells = <0>;
0275 };
0276
0277 max98357a: max98357a {
0278 compatible = "maxim,max98357a";
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&sdmode_en>;
0281 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
0282 sdmode-delay = <2>;
0283 #sound-dai-cells = <0>;
0284 status = "okay";
0285 };
0286
0287 sound: sound {
0288 compatible = "rockchip,rk3399-gru-sound";
0289 rockchip,cpu = <&i2s0 &spdif>;
0290 };
0291 };
0292
0293 &cdn_dp {
0294 status = "okay";
0295 };
0296
0297 /*
0298 * Set some suspend operating points to avoid OVP in suspend
0299 *
0300 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
0301 * from wherever they're at back to the "default" operating point (whatever
0302 * voltage we get when we set the PWM pins to "input").
0303 *
0304 * This quick transition under light load has the possibility to trigger the
0305 * regulator "over voltage protection" (OVP).
0306 *
0307 * To make extra certain that we don't hit this OVP at suspend time, we'll
0308 * transition to a voltage that's much closer to the default (~1.0 V) so that
0309 * there will not be a big jump. Technically we only need to get within 200 mV
0310 * of the default voltage, but the speed here should be fast enough and we need
0311 * suspend/resume to be rock solid.
0312 */
0313
0314 &cluster0_opp {
0315 opp05 {
0316 opp-suspend;
0317 };
0318 };
0319
0320 &cluster1_opp {
0321 opp06 {
0322 opp-suspend;
0323 };
0324 };
0325
0326 &cpu_l0 {
0327 cpu-supply = <&ppvar_litcpu>;
0328 };
0329
0330 &cpu_l1 {
0331 cpu-supply = <&ppvar_litcpu>;
0332 };
0333
0334 &cpu_l2 {
0335 cpu-supply = <&ppvar_litcpu>;
0336 };
0337
0338 &cpu_l3 {
0339 cpu-supply = <&ppvar_litcpu>;
0340 };
0341
0342 &cpu_b0 {
0343 cpu-supply = <&ppvar_bigcpu>;
0344 };
0345
0346 &cpu_b1 {
0347 cpu-supply = <&ppvar_bigcpu>;
0348 };
0349
0350
0351 &cru {
0352 assigned-clocks =
0353 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
0354 <&cru PLL_NPLL>,
0355 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
0356 <&cru PCLK_PERIHP>,
0357 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
0358 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
0359 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
0360 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
0361 <&cru ACLK_GIC_PRE>,
0362 <&cru PCLK_DDR>;
0363 assigned-clock-rates =
0364 <600000000>, <800000000>,
0365 <1000000000>,
0366 <150000000>, <75000000>,
0367 <37500000>,
0368 <100000000>, <100000000>,
0369 <50000000>, <800000000>,
0370 <100000000>, <50000000>,
0371 <400000000>, <400000000>,
0372 <200000000>,
0373 <200000000>;
0374 };
0375
0376 &dfi {
0377 status = "okay";
0378 };
0379
0380 &dmc {
0381 status = "okay";
0382
0383 rockchip,pd-idle-ns = <160>;
0384 rockchip,sr-idle-ns = <10240>;
0385 rockchip,sr-mc-gate-idle-ns = <40960>;
0386 rockchip,srpd-lite-idle-ns = <61440>;
0387 rockchip,standby-idle-ns = <81920>;
0388
0389 rockchip,ddr3_odt_dis_freq = <666000000>;
0390 rockchip,lpddr3_odt_dis_freq = <666000000>;
0391 rockchip,lpddr4_odt_dis_freq = <666000000>;
0392
0393 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
0394 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
0395 rockchip,standby-idle-dis-freq-hz = <928000000>;
0396 };
0397
0398 &dmc_opp_table {
0399 opp03 {
0400 opp-suspend;
0401 };
0402 };
0403
0404 &emmc_phy {
0405 status = "okay";
0406 };
0407
0408 &gpu {
0409 mali-supply = <&ppvar_gpu>;
0410 status = "okay";
0411 };
0412
0413 ap_i2c_ts: &i2c3 {
0414 status = "okay";
0415
0416 clock-frequency = <400000>;
0417
0418 /* These are relatively safe rise/fall times */
0419 i2c-scl-falling-time-ns = <50>;
0420 i2c-scl-rising-time-ns = <300>;
0421 };
0422
0423 ap_i2c_audio: &i2c8 {
0424 status = "okay";
0425
0426 clock-frequency = <400000>;
0427
0428 /* These are relatively safe rise/fall times */
0429 i2c-scl-falling-time-ns = <50>;
0430 i2c-scl-rising-time-ns = <300>;
0431
0432 codec: da7219@1a {
0433 compatible = "dlg,da7219";
0434 reg = <0x1a>;
0435 interrupt-parent = <&gpio1>;
0436 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
0437 clocks = <&cru SCLK_I2S_8CH_OUT>;
0438 clock-names = "mclk";
0439 dlg,micbias-lvl = <2600>;
0440 dlg,mic-amp-in-sel = "diff";
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&headset_int_l>;
0443 VDD-supply = <&pp1800>;
0444 VDDMIC-supply = <&pp3300>;
0445 VDDIO-supply = <&pp1800>;
0446
0447 da7219_aad {
0448 dlg,adc-1bit-rpt = <1>;
0449 dlg,btn-avg = <4>;
0450 dlg,btn-cfg = <50>;
0451 dlg,mic-det-thr = <500>;
0452 dlg,jack-ins-deb = <20>;
0453 dlg,jack-det-rate = "32ms_64ms";
0454 dlg,jack-rem-deb = <1>;
0455
0456 dlg,a-d-btn-thr = <0xa>;
0457 dlg,d-b-btn-thr = <0x16>;
0458 dlg,b-c-btn-thr = <0x21>;
0459 dlg,c-mic-btn-thr = <0x3E>;
0460 };
0461 };
0462 };
0463
0464 &i2s0 {
0465 status = "okay";
0466 };
0467
0468 &io_domains {
0469 status = "okay";
0470
0471 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
0472 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
0473 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
0474 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
0475 };
0476
0477 &pcie0 {
0478 status = "okay";
0479
0480 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
0481 pinctrl-names = "default";
0482 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
0483 vpcie3v3-supply = <&pp3300_wifi_bt>;
0484 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
0485 vpcie0v9-supply = <&pp900_pcie>;
0486
0487 pci_rootport: pcie@0,0 {
0488 reg = <0x0000 0 0 0 0>;
0489 #address-cells = <3>;
0490 #size-cells = <2>;
0491 ranges;
0492 };
0493 };
0494
0495 &pcie_phy {
0496 status = "okay";
0497 };
0498
0499 &pmu_io_domains {
0500 status = "okay";
0501
0502 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
0503 };
0504
0505 &pwm0 {
0506 status = "okay";
0507 };
0508
0509 &pwm1 {
0510 status = "okay";
0511 };
0512
0513 &pwm2 {
0514 status = "okay";
0515 };
0516
0517 &pwm3 {
0518 status = "okay";
0519 };
0520
0521 &sdhci {
0522 /*
0523 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
0524 * same (or nearly the same) performance for all eMMC that are intended
0525 * to be used.
0526 */
0527 assigned-clock-rates = <150000000>;
0528
0529 bus-width = <8>;
0530 mmc-hs400-1_8v;
0531 mmc-hs400-enhanced-strobe;
0532 non-removable;
0533 status = "okay";
0534 };
0535
0536 &sdmmc {
0537 status = "okay";
0538
0539 /*
0540 * Note: configure "sdmmc_cd" as card detect even though it's actually
0541 * hooked to ground. Because we specified "cd-gpios" below dw_mmc
0542 * should be ignoring card detect anyway. Specifying the pin as
0543 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
0544 * turned on that the system will still make sure the port is
0545 * configured as SDMMC and not JTAG.
0546 */
0547 pinctrl-names = "default";
0548 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
0549 &sdmmc_bus4>;
0550
0551 bus-width = <4>;
0552 cap-mmc-highspeed;
0553 cap-sd-highspeed;
0554 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0555 disable-wp;
0556 sd-uhs-sdr12;
0557 sd-uhs-sdr25;
0558 sd-uhs-sdr50;
0559 sd-uhs-sdr104;
0560 vmmc-supply = <&pp3000_sd_slot>;
0561 vqmmc-supply = <&ppvar_sd_card_io>;
0562 };
0563
0564 &spdif {
0565 status = "okay";
0566
0567 /*
0568 * SPDIF is routed internally to DP; we either don't use these pins, or
0569 * mux them to something else.
0570 */
0571 /delete-property/ pinctrl-0;
0572 /delete-property/ pinctrl-names;
0573 };
0574
0575 &spi1 {
0576 status = "okay";
0577
0578 pinctrl-names = "default", "sleep";
0579 pinctrl-1 = <&spi1_sleep>;
0580
0581 flash@0 {
0582 compatible = "jedec,spi-nor";
0583 reg = <0>;
0584
0585 /* May run faster once verified. */
0586 spi-max-frequency = <10000000>;
0587 };
0588 };
0589
0590 &spi2 {
0591 status = "okay";
0592 };
0593
0594 &spi5 {
0595 status = "okay";
0596
0597 cros_ec: ec@0 {
0598 compatible = "google,cros-ec-spi";
0599 reg = <0>;
0600 interrupt-parent = <&gpio0>;
0601 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
0602 pinctrl-names = "default";
0603 pinctrl-0 = <&ec_ap_int_l>;
0604 spi-max-frequency = <3000000>;
0605
0606 i2c_tunnel: i2c-tunnel {
0607 compatible = "google,cros-ec-i2c-tunnel";
0608 google,remote-bus = <4>;
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 };
0612
0613 usbc_extcon0: extcon0 {
0614 compatible = "google,extcon-usbc-cros-ec";
0615 google,usb-port-id = <0>;
0616 };
0617 };
0618 };
0619
0620 &tsadc {
0621 status = "okay";
0622
0623 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
0624 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
0625 };
0626
0627 &tcphy0 {
0628 status = "okay";
0629 extcon = <&usbc_extcon0>;
0630 };
0631
0632 &u2phy0 {
0633 status = "okay";
0634 };
0635
0636 &u2phy0_host {
0637 status = "okay";
0638 };
0639
0640 &u2phy1_host {
0641 status = "okay";
0642 };
0643
0644 &u2phy0_otg {
0645 status = "okay";
0646 };
0647
0648 &u2phy1_otg {
0649 status = "okay";
0650 };
0651
0652 &uart2 {
0653 status = "okay";
0654 };
0655
0656 &usb_host0_ohci {
0657 status = "okay";
0658 };
0659
0660 &usbdrd3_0 {
0661 status = "okay";
0662 extcon = <&usbc_extcon0>;
0663 };
0664
0665 &usbdrd_dwc3_0 {
0666 status = "okay";
0667 dr_mode = "host";
0668 };
0669
0670 &vopb {
0671 status = "okay";
0672 };
0673
0674 &vopb_mmu {
0675 status = "okay";
0676 };
0677
0678 &vopl {
0679 status = "okay";
0680 };
0681
0682 &vopl_mmu {
0683 status = "okay";
0684 };
0685
0686 #include <arm/cros-ec-keyboard.dtsi>
0687 #include <arm/cros-ec-sbs.dtsi>
0688
0689 &pinctrl {
0690 /*
0691 * pinctrl settings for pins that have no real owners.
0692 *
0693 * At the moment settings are identical for S0 and S3, but if we later
0694 * need to configure things differently for S3 we'll adjust here.
0695 */
0696 pinctrl-names = "default";
0697 pinctrl-0 = <
0698 &ap_pwroff /* AP will auto-assert this when in S3 */
0699 &clk_32k /* This pin is always 32k on gru boards */
0700 >;
0701
0702 pcfg_output_low: pcfg-output-low {
0703 output-low;
0704 };
0705
0706 pcfg_output_high: pcfg-output-high {
0707 output-high;
0708 };
0709
0710 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
0711 bias-disable;
0712 drive-strength = <8>;
0713 };
0714
0715 backlight-enable {
0716 bl_en: bl-en {
0717 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
0718 };
0719 };
0720
0721 cros-ec {
0722 ec_ap_int_l: ec-ap-int-l {
0723 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
0724 };
0725 };
0726
0727 discrete-regulators {
0728 sd_io_pwr_en: sd-io-pwr-en {
0729 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
0730 &pcfg_pull_none>;
0731 };
0732
0733 sd_pwr_1800_sel: sd-pwr-1800-sel {
0734 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
0735 &pcfg_pull_none>;
0736 };
0737
0738 sd_slot_pwr_en: sd-slot-pwr-en {
0739 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
0740 &pcfg_pull_none>;
0741 };
0742 };
0743
0744 codec {
0745 /* Has external pullup */
0746 headset_int_l: headset-int-l {
0747 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
0748 };
0749
0750 mic_int: mic-int {
0751 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
0752 };
0753 };
0754
0755 max98357a {
0756 sdmode_en: sdmode-en {
0757 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
0758 };
0759 };
0760
0761 pcie {
0762 pcie_clkreqn_cpm: pci-clkreqn-cpm {
0763 /*
0764 * Since our pcie doesn't support ClockPM(CPM), we want
0765 * to hack this as gpio, so the EP could be able to
0766 * de-assert it along and make ClockPM(CPM) work.
0767 */
0768 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
0769 };
0770 };
0771
0772 sdmmc {
0773 /*
0774 * We run sdmmc at max speed; bump up drive strength.
0775 * We also have external pulls, so disable the internal ones.
0776 */
0777 sdmmc_bus4: sdmmc-bus4 {
0778 rockchip,pins =
0779 <4 RK_PB0 1 &pcfg_pull_none_8ma>,
0780 <4 RK_PB1 1 &pcfg_pull_none_8ma>,
0781 <4 RK_PB2 1 &pcfg_pull_none_8ma>,
0782 <4 RK_PB3 1 &pcfg_pull_none_8ma>;
0783 };
0784
0785 sdmmc_clk: sdmmc-clk {
0786 rockchip,pins =
0787 <4 RK_PB4 1 &pcfg_pull_none_8ma>;
0788 };
0789
0790 sdmmc_cmd: sdmmc-cmd {
0791 rockchip,pins =
0792 <4 RK_PB5 1 &pcfg_pull_none_8ma>;
0793 };
0794
0795 /*
0796 * In our case the official card detect is hooked to ground
0797 * to avoid getting access to JTAG just by sticking something
0798 * in the SD card slot (see the force_jtag bit in the TRM).
0799 *
0800 * We still configure it as card detect because it doesn't
0801 * hurt and dw_mmc will ignore it. We make sure to disable
0802 * the pull though so we don't burn needless power.
0803 */
0804 sdmmc_cd: sdmmc-cd {
0805 rockchip,pins =
0806 <0 RK_PA7 1 &pcfg_pull_none>;
0807 };
0808
0809 /* This is where we actually hook up CD; has external pull */
0810 sdmmc_cd_pin: sdmmc-cd-pin {
0811 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
0812 };
0813 };
0814
0815 spi1 {
0816 spi1_sleep: spi1-sleep {
0817 /*
0818 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
0819 * prevent leakage.
0820 */
0821 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
0822 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
0823 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
0824 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
0825 };
0826 };
0827
0828 touchscreen {
0829 touch_int_l: touch-int-l {
0830 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
0831 };
0832
0833 touch_reset_l: touch-reset-l {
0834 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
0835 };
0836 };
0837
0838 trackpad {
0839 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
0840 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
0841 };
0842
0843 trackpad_int_l: trackpad-int-l {
0844 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
0845 };
0846 };
0847
0848 wifi: wifi {
0849 wlan_module_reset_l: wlan-module-reset-l {
0850 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
0851 };
0852
0853 bt_host_wake_l: bt-host-wake-l {
0854 /* Kevin has an external pull up, but Gru does not */
0855 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
0856 };
0857 };
0858
0859 write-protect {
0860 ap_fw_wp: ap-fw-wp {
0861 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
0862 };
0863 };
0864 };
