0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Gru-scarlet board device tree source
0004 *
0005 * Copyright 2018 Google, Inc
0006 */
0007
0008 #include "rk3399-gru.dtsi"
0009
0010 /{
0011 chassis-type = "tablet";
0012
0013 /* Power tree */
0014
0015 /* ppvar_sys children, sorted by name */
0016 pp1250_s3: pp1250-s3 {
0017 compatible = "regulator-fixed";
0018 regulator-name = "pp1250_s3";
0019
0020 /* EC turns on w/ pp1250_s3_en; always on for AP */
0021 regulator-always-on;
0022 regulator-boot-on;
0023 regulator-min-microvolt = <1250000>;
0024 regulator-max-microvolt = <1250000>;
0025
0026 vin-supply = <&ppvar_sys>;
0027 };
0028
0029 pp1250_cam: pp1250-dvdd {
0030 compatible = "regulator-fixed";
0031 regulator-name = "pp1250_dvdd";
0032 pinctrl-names = "default";
0033 pinctrl-0 = <&pp1250_cam_en>;
0034
0035 enable-active-high;
0036 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
0037
0038 /* 740us delay from gpio output high to pp1250 stable,
0039 * rounding up to 1ms for safety.
0040 */
0041 startup-delay-us = <1000>;
0042 vin-supply = <&pp1250_s3>;
0043 };
0044
0045 pp900_s0: pp900-s0 {
0046 compatible = "regulator-fixed";
0047 regulator-name = "pp900_s0";
0048
0049 /* EC turns on w/ pp900_s0_en; always on for AP */
0050 regulator-always-on;
0051 regulator-boot-on;
0052 regulator-min-microvolt = <900000>;
0053 regulator-max-microvolt = <900000>;
0054
0055 vin-supply = <&ppvar_sys>;
0056 };
0057
0058 ppvarn_lcd: ppvarn-lcd {
0059 compatible = "regulator-fixed";
0060 regulator-name = "ppvarn_lcd";
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&ppvarn_lcd_en>;
0063
0064 enable-active-high;
0065 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0066 vin-supply = <&ppvar_sys>;
0067 };
0068
0069 ppvarp_lcd: ppvarp-lcd {
0070 compatible = "regulator-fixed";
0071 regulator-name = "ppvarp_lcd";
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&ppvarp_lcd_en>;
0074
0075 enable-active-high;
0076 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
0077 vin-supply = <&ppvar_sys>;
0078 };
0079
0080 /* pp1800 children, sorted by name */
0081 pp900_s3: pp900-s3 {
0082 compatible = "regulator-fixed";
0083 regulator-name = "pp900_s3";
0084
0085 /* EC turns on w/ pp900_s3_en; always on for AP */
0086 regulator-always-on;
0087 regulator-boot-on;
0088 regulator-min-microvolt = <900000>;
0089 regulator-max-microvolt = <900000>;
0090
0091 vin-supply = <&pp1800>;
0092 };
0093
0094 /* EC turns on pp1800_s3_en */
0095 pp1800_s3: pp1800 {
0096 };
0097
0098 /* pp3300 children, sorted by name */
0099 pp2800_cam: pp2800-avdd {
0100 compatible = "regulator-fixed";
0101 regulator-name = "pp2800_avdd";
0102 pinctrl-names = "default";
0103 pinctrl-0 = <&pp2800_cam_en>;
0104
0105 enable-active-high;
0106 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
0107 startup-delay-us = <100>;
0108 vin-supply = <&pp3300>;
0109 };
0110
0111 /* EC turns on pp3300_s0_en */
0112 pp3300_s0: pp3300 {
0113 };
0114
0115 /* EC turns on pp3300_s3_en */
0116 pp3300_s3: pp3300 {
0117 };
0118
0119 /*
0120 * See b/66922012
0121 *
0122 * This is a hack to make sure the Bluetooth part of the QCA6174A
0123 * is reset at boot by toggling BT_EN. At boot BT_EN is first set
0124 * to low when the bt_3v3 regulator is registered (in disabled
0125 * state). The fake regulator is configured as a supply of the
0126 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
0127 * the boot process it also enables its supply regulator bt_3v3,
0128 * which changes BT_EN to high.
0129 */
0130 bt_3v3: bt-3v3 {
0131 compatible = "regulator-fixed";
0132 regulator-name = "bt_3v3";
0133 pinctrl-names = "default";
0134 pinctrl-0 = <&bt_en_1v8_l>;
0135
0136 enable-active-high;
0137 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
0138 vin-supply = <&pp3300_s3>;
0139 };
0140
0141 wlan_3v3: wlan-3v3 {
0142 compatible = "regulator-fixed";
0143 regulator-name = "wlan_3v3";
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&wlan_pd_1v8_l>;
0146
0147 /*
0148 * The WL_EN pin is driven low when the regulator is
0149 * registered, and transitions to high when the PCIe bus
0150 * is powered up.
0151 */
0152 enable-active-high;
0153 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
0154
0155 /*
0156 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
0157 * TODO (b/64444991): how long to assert PD#?
0158 */
0159 regulator-enable-ramp-delay = <10000>;
0160 /* See bt_3v3 hack above */
0161 vin-supply = <&bt_3v3>;
0162 };
0163
0164 backlight: backlight {
0165 compatible = "pwm-backlight";
0166 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&bl_en>;
0169 pwms = <&pwm1 0 1000000 0>;
0170 pwm-delay-us = <10000>;
0171 };
0172
0173 dmic: dmic {
0174 compatible = "dmic-codec";
0175 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
0176 pinctrl-names = "default";
0177 pinctrl-0 = <&dmic_en>;
0178 wakeup-delay-ms = <250>;
0179 };
0180
0181 gpio_keys: gpio-keys {
0182 compatible = "gpio-keys";
0183 pinctrl-names = "default";
0184 pinctrl-0 = <&pen_eject_odl>;
0185
0186 switch-pen-insert {
0187 label = "Pen Insert";
0188 /* Insert = low, eject = high */
0189 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0190 linux,code = <SW_PEN_INSERTED>;
0191 linux,input-type = <EV_SW>;
0192 wakeup-source;
0193 };
0194 };
0195 };
0196
0197 /* pp900_s0 aliases */
0198 pp900_ddrpll_ap: &pp900_s0 {
0199 };
0200 pp900_pcie: &pp900_s0 {
0201 };
0202 pp900_usb: &pp900_s0 {
0203 };
0204
0205 /* pp900_s3 aliases */
0206 pp900_emmcpll: &pp900_s3 {
0207 };
0208
0209 /* EC turns on; alias for pp1800_s0 */
0210 pp1800_pcie: &pp1800_s0 {
0211 };
0212
0213 /* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
0214 &ppvar_bigcpu {
0215 ctrl-voltage-range = <800074 1299226>;
0216 regulator-min-microvolt = <800074>;
0217 regulator-max-microvolt = <1299226>;
0218 };
0219
0220 &ppvar_bigcpu_pwm {
0221 /* On scarlet ppvar big cpu use pwm3 */
0222 pwms = <&pwm3 0 3337 0>;
0223 regulator-min-microvolt = <800074>;
0224 regulator-max-microvolt = <1299226>;
0225 };
0226
0227 &ppvar_litcpu {
0228 ctrl-voltage-range = <802122 1199620>;
0229 regulator-min-microvolt = <802122>;
0230 regulator-max-microvolt = <1199620>;
0231 };
0232
0233 &ppvar_litcpu_pwm {
0234 regulator-min-microvolt = <802122>;
0235 regulator-max-microvolt = <1199620>;
0236 };
0237
0238 &ppvar_gpu {
0239 ctrl-voltage-range = <799600 1099600>;
0240 regulator-min-microvolt = <799600>;
0241 regulator-max-microvolt = <1099600>;
0242 };
0243
0244 &ppvar_gpu_pwm {
0245 regulator-min-microvolt = <799600>;
0246 regulator-max-microvolt = <1099600>;
0247 };
0248
0249 &ppvar_sd_card_io {
0250 states = <1800000 0x0>, <3300000 0x1>;
0251 regulator-max-microvolt = <3300000>;
0252 };
0253
0254 &pp3000_sd_slot {
0255 vin-supply = <&pp3300>;
0256 };
0257
0258 ap_i2c_dig: &i2c2 {
0259 status = "okay";
0260
0261 clock-frequency = <400000>;
0262
0263 /* These are relatively safe rise/fall times. */
0264 i2c-scl-falling-time-ns = <50>;
0265 i2c-scl-rising-time-ns = <300>;
0266
0267 digitizer: digitizer@9 {
0268 compatible = "hid-over-i2c";
0269 reg = <0x9>;
0270 interrupt-parent = <&gpio1>;
0271 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
0272 hid-descr-addr = <0x1>;
0273 pinctrl-names = "default";
0274 pinctrl-0 = <&pen_int_odl &pen_reset_l>;
0275 };
0276 };
0277
0278 &ap_i2c_ts {
0279 touchscreen: touchscreen@10 {
0280 compatible = "elan,ekth3500";
0281 reg = <0x10>;
0282 interrupt-parent = <&gpio1>;
0283 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&touch_int_l &touch_reset_l>;
0286 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
0287 };
0288 };
0289
0290 camera: &i2c7 {
0291 status = "okay";
0292
0293 clock-frequency = <400000>;
0294
0295 /* These are relatively safe rise/fall times; TODO: measure */
0296 i2c-scl-falling-time-ns = <50>;
0297 i2c-scl-rising-time-ns = <300>;
0298
0299 /* 24M mclk is shared between world and user cameras */
0300 pinctrl-0 = <&i2c7_xfer &test_clkout1>;
0301
0302 /* Rear-facing camera */
0303 wcam: camera@36 {
0304 compatible = "ovti,ov5695";
0305 reg = <0x36>;
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&wcam_rst>;
0308
0309 clocks = <&cru SCLK_TESTCLKOUT1>;
0310 clock-names = "xvclk";
0311
0312 avdd-supply = <&pp2800_cam>;
0313 dvdd-supply = <&pp1250_cam>;
0314 dovdd-supply = <&pp1800_s0>;
0315 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
0316
0317 port {
0318 wcam_out: endpoint {
0319 remote-endpoint = <&mipi_in_wcam>;
0320 data-lanes = <1 2>;
0321 };
0322 };
0323 };
0324
0325 /* Front-facing camera */
0326 ucam: camera@3c {
0327 compatible = "ovti,ov2685";
0328 reg = <0x3c>;
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&ucam_rst>;
0331
0332 clocks = <&cru SCLK_TESTCLKOUT1>;
0333 clock-names = "xvclk";
0334
0335 avdd-supply = <&pp2800_cam>;
0336 dovdd-supply = <&pp1800_s0>;
0337 dvdd-supply = <&pp1800_s0>;
0338 reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
0339
0340 port {
0341 ucam_out: endpoint {
0342 remote-endpoint = <&mipi_in_ucam>;
0343 data-lanes = <1>;
0344 };
0345 };
0346 };
0347 };
0348
0349 &cdn_dp {
0350 extcon = <&usbc_extcon0>;
0351 phys = <&tcphy0_dp>;
0352 };
0353
0354 &cpu_alert0 {
0355 temperature = <66000>;
0356 };
0357
0358 &cpu_alert1 {
0359 temperature = <71000>;
0360 };
0361
0362 &cros_ec {
0363 interrupt-parent = <&gpio1>;
0364 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0365 };
0366
0367 &cru {
0368 assigned-clocks =
0369 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
0370 <&cru PLL_NPLL>,
0371 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
0372 <&cru PCLK_PERIHP>,
0373 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
0374 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
0375 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
0376 <&cru ACLK_VIO>,
0377 <&cru ACLK_GIC_PRE>,
0378 <&cru PCLK_DDR>,
0379 <&cru ACLK_HDCP>,
0380 <&cru ACLK_VDU>;
0381 assigned-clock-rates =
0382 <600000000>, <1600000000>,
0383 <1000000000>,
0384 <150000000>, <75000000>,
0385 <37500000>,
0386 <100000000>, <100000000>,
0387 <50000000>, <800000000>,
0388 <100000000>, <50000000>,
0389 <400000000>,
0390 <200000000>,
0391 <200000000>,
0392 <400000000>,
0393 <400000000>;
0394 };
0395
0396 /* The center supply is fixed to .9V on scarlet */
0397 &dmc {
0398 center-supply = <&pp900_s0>;
0399 };
0400
0401 /* We don't need .925 V for 928 MHz on scarlet */
0402 &dmc_opp_table {
0403 opp03 {
0404 opp-microvolt = <900000>;
0405 };
0406 };
0407
0408 &gpio0 {
0409 gpio-line-names = /* GPIO0 A 0-7 */
0410 "CLK_32K_AP",
0411 "EC_IN_RW_OD",
0412 "SPK_PA_EN",
0413 "WLAN_PERST_1V8_L",
0414 "WLAN_PD_1V8_L",
0415 "WLAN_RF_KILL_1V8_L",
0416 "BIGCPU_DVS_PWM",
0417 "SD_CD_L_JTAG_EN",
0418
0419 /* GPIO0 B 0-5 */
0420 "BT_EN_BT_RF_KILL_1V8_L",
0421 "PMUIO2_33_18_L_PP3300_S0_EN",
0422 "TOUCH_RESET_L",
0423 "AP_EC_WARM_RESET_REQ",
0424 "PEN_RESET_L",
0425 /*
0426 * AP_FLASH_WP_L is crossystem ABI. Schematics call
0427 * it AP_FLASH_WP_R_ODL.
0428 */
0429 "AP_FLASH_WP_L";
0430 };
0431
0432 &gpio1 {
0433 gpio-line-names = /* GPIO1 A 0-7 */
0434 "PEN_INT_ODL",
0435 "PEN_EJECT_ODL",
0436 "BT_HOST_WAKE_1V8_L",
0437 "WLAN_HOST_WAKE_1V8_L",
0438 "TOUCH_INT_ODL",
0439 "AP_EC_S3_S0_L",
0440 "AP_EC_OVERTEMP",
0441 "AP_SPI_FLASH_MISO",
0442
0443 /* GPIO1 B 0-7 */
0444 "AP_SPI_FLASH_MOSI_R",
0445 "AP_SPI_FLASH_CLK_R",
0446 "AP_SPI_FLASH_CS_L_R",
0447 "SD_CARD_DET_ODL",
0448 "",
0449 "AP_EXPANSION_IO1",
0450 "AP_EXPANSION_IO2",
0451 "AP_I2C_DISP_SDA",
0452
0453 /* GPIO1 C 0-7 */
0454 "AP_I2C_DISP_SCL",
0455 "H1_INT_ODL",
0456 "EC_AP_INT_ODL",
0457 "LITCPU_DVS_PWM",
0458 "AP_I2C_AUDIO_SDA",
0459 "AP_I2C_AUDIO_SCL",
0460 "AP_EXPANSION_IO3",
0461 "HEADSET_INT_ODL",
0462
0463 /* GPIO1 D0 */
0464 "AP_EXPANSION_IO4";
0465 };
0466
0467 &gpio2 {
0468 gpio-line-names = /* GPIO2 A 0-7 */
0469 "AP_I2C_PEN_SDA",
0470 "AP_I2C_PEN_SCL",
0471 "SD_IO_PWR_EN",
0472 "UCAM_RST_L",
0473 "PP1250_CAM_EN",
0474 "WCAM_RST_L",
0475 "AP_EXPANSION_IO5",
0476 "AP_I2C_CAM_SDA",
0477
0478 /* GPIO2 B 0-7 */
0479 "AP_I2C_CAM_SCL",
0480 "AP_H1_SPI_MISO",
0481 "AP_H1_SPI_MOSI",
0482 "AP_H1_SPI_CLK",
0483 "AP_H1_SPI_CS_L",
0484 "",
0485 "",
0486 "",
0487
0488 /* GPIO2 C 0-7 */
0489 "UART_EXPANSION_TX_AP_RX",
0490 "UART_AP_TX_EXPANSION_RX",
0491 "UART_EXPANSION_RTS_AP_CTS",
0492 "UART_AP_RTS_EXPANSION_CTS",
0493 "AP_SPI_EC_MISO",
0494 "AP_SPI_EC_MOSI",
0495 "AP_SPI_EC_CLK",
0496 "AP_SPI_EC_CS_L",
0497
0498 /* GPIO2 D 0-4 */
0499 "PP2800_CAM_EN",
0500 "CLK_24M_CAM",
0501 "WLAN_PCIE_CLKREQ_1V8_L",
0502 "",
0503 "SD_PWR_3000_1800_L";
0504 };
0505
0506 &gpio3 {
0507 gpio-line-names = /* GPIO3 A 0-7 */
0508 "",
0509 "",
0510 "",
0511 "",
0512 "",
0513 "",
0514 "",
0515 "",
0516
0517 /* GPIO3 B 0-7 */
0518 "",
0519 "",
0520 "",
0521 "",
0522 "",
0523 "",
0524 "",
0525 "",
0526
0527 /* GPIO3 C 0-7 */
0528 "",
0529 "",
0530 "",
0531 "",
0532 "",
0533 "",
0534 "",
0535 "",
0536
0537 /* GPIO3 D 0-7 */
0538 "I2S0_SCLK",
0539 "I2S0_LRCK_RX",
0540 "I2S0_LRCK_TX",
0541 "I2S0_SDI_0",
0542 "STRAP_LCDBIAS_L",
0543 "STRAP_FEATURE_1",
0544 "STRAP_FEATURE_2",
0545 "I2S0_SDO_0";
0546 };
0547
0548 &gpio4 {
0549 gpio-line-names = /* GPIO4 A 0-7 */
0550 "I2S_MCLK",
0551 "AP_I2C_EXPANSION_SDA",
0552 "AP_I2C_EXPANSION_SCL",
0553 "DMIC_EN",
0554 "",
0555 "",
0556 "",
0557 "",
0558
0559 /* GPIO4 B 0-7 */
0560 "",
0561 "",
0562 "",
0563 "",
0564 "",
0565 "",
0566 "",
0567 "",
0568
0569 /* GPIO4 C 0-7 */
0570 "AP_I2C_TS_SDA",
0571 "AP_I2C_TS_SCL",
0572 "GPU_DVS_PWM",
0573 "UART_DBG_TX_AP_RX",
0574 "UART_AP_TX_DBG_RX",
0575 "BL_EN",
0576 "BL_PWM",
0577 "",
0578
0579 /* GPIO4 D 0-5 */
0580 "",
0581 "DISPLAY_RST_L",
0582 "",
0583 "PPVARP_LCD_EN",
0584 "PPVARN_LCD_EN",
0585 "SD_SLOT_PWR_EN";
0586 };
0587
0588 &i2c_tunnel {
0589 google,remote-bus = <0>;
0590 };
0591
0592 &io_domains {
0593 bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */
0594 audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */
0595 gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */
0596 };
0597
0598 &isp0 {
0599 status = "okay";
0600
0601 ports {
0602 port@0 {
0603 mipi_in_wcam: endpoint@0 {
0604 reg = <0>;
0605 remote-endpoint = <&wcam_out>;
0606 data-lanes = <1 2>;
0607 };
0608
0609 mipi_in_ucam: endpoint@1 {
0610 reg = <1>;
0611 remote-endpoint = <&ucam_out>;
0612 data-lanes = <1>;
0613 };
0614 };
0615 };
0616 };
0617
0618 &isp0_mmu {
0619 status = "okay";
0620 };
0621
0622 &max98357a {
0623 sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
0624 };
0625
0626 &mipi_dphy_rx0 {
0627 status = "okay";
0628 };
0629
0630 &mipi_dsi {
0631 status = "okay";
0632 clock-master;
0633
0634 ports {
0635 mipi_out: port@1 {
0636 reg = <1>;
0637
0638 mipi_out_panel: endpoint {
0639 remote-endpoint = <&mipi_in_panel>;
0640 };
0641 };
0642 };
0643
0644 mipi_panel: panel@0 {
0645 /* 2 different panels are used, compatibles are in dts files */
0646 reg = <0>;
0647 backlight = <&backlight>;
0648 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
0649 pinctrl-names = "default";
0650 pinctrl-0 = <&display_rst_l>;
0651
0652 ports {
0653 #address-cells = <1>;
0654 #size-cells = <0>;
0655
0656 port@0 {
0657 reg = <0>;
0658
0659 mipi_in_panel: endpoint {
0660 remote-endpoint = <&mipi_out_panel>;
0661 };
0662 };
0663
0664 port@1 {
0665 reg = <1>;
0666
0667 mipi1_in_panel: endpoint@1 {
0668 remote-endpoint = <&mipi1_out_panel>;
0669 };
0670 };
0671 };
0672 };
0673 };
0674
0675 &mipi_dsi1 {
0676 status = "okay";
0677
0678 ports {
0679 mipi1_out: port@1 {
0680 reg = <1>;
0681
0682 mipi1_out_panel: endpoint {
0683 remote-endpoint = <&mipi1_in_panel>;
0684 };
0685 };
0686 };
0687 };
0688
0689 &pcie0 {
0690 ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
0691
0692 /* PERST# asserted in S3 */
0693 pcie-reset-suspend = <1>;
0694
0695 vpcie3v3-supply = <&wlan_3v3>;
0696 vpcie1v8-supply = <&pp1800_pcie>;
0697 };
0698
0699 &sdmmc {
0700 cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
0701 };
0702
0703 &sound {
0704 rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
0705 };
0706
0707 &spi2 {
0708 status = "okay";
0709
0710 cr50@0 {
0711 compatible = "google,cr50";
0712 reg = <0>;
0713 interrupt-parent = <&gpio1>;
0714 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
0715 pinctrl-names = "default";
0716 pinctrl-0 = <&h1_int_od_l>;
0717 spi-max-frequency = <800000>;
0718 };
0719 };
0720
0721 &usb_host0_ohci {
0722 #address-cells = <1>;
0723 #size-cells = <0>;
0724
0725 qca_bt: bluetooth@1 {
0726 compatible = "usbcf3,e300", "usb4ca,301a";
0727 reg = <1>;
0728 pinctrl-names = "default";
0729 pinctrl-0 = <&bt_host_wake_l>;
0730 interrupt-parent = <&gpio1>;
0731 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0732 interrupt-names = "wakeup";
0733 };
0734 };
0735
0736 /* PINCTRL OVERRIDES */
0737 &ec_ap_int_l {
0738 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
0739 };
0740
0741 &ap_fw_wp {
0742 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
0743 };
0744
0745 &bl_en {
0746 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
0747 };
0748
0749 &bt_host_wake_l {
0750 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
0751 };
0752
0753 &ec_ap_int_l {
0754 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
0755 };
0756
0757 &headset_int_l {
0758 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
0759 };
0760
0761 &i2s0_8ch_bus {
0762 rockchip,pins =
0763 <3 RK_PD0 1 &pcfg_pull_none_6ma>,
0764 <3 RK_PD1 1 &pcfg_pull_none_6ma>,
0765 <3 RK_PD2 1 &pcfg_pull_none_6ma>,
0766 <3 RK_PD3 1 &pcfg_pull_none_6ma>,
0767 <3 RK_PD7 1 &pcfg_pull_none_6ma>,
0768 <4 RK_PA0 1 &pcfg_pull_none_6ma>;
0769 };
0770
0771 /* there is no external pull up, so need to set this pin pull up */
0772 &sdmmc_cd_pin {
0773 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
0774 };
0775
0776 &sd_pwr_1800_sel {
0777 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
0778 };
0779
0780 &sdmode_en {
0781 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
0782 };
0783
0784 &touch_reset_l {
0785 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
0786 };
0787
0788 &touch_int_l {
0789 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
0790 };
0791
0792 &pinctrl {
0793 pinctrl-0 = <
0794 &ap_pwroff /* AP will auto-assert this when in S3 */
0795 &clk_32k /* This pin is always 32k on gru boards */
0796 &wlan_rf_kill_1v8_l
0797 >;
0798
0799 pcfg_pull_none_6ma: pcfg-pull-none-6ma {
0800 bias-disable;
0801 drive-strength = <6>;
0802 };
0803
0804 camera {
0805 pp1250_cam_en: pp1250-dvdd {
0806 rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
0807 };
0808
0809 pp2800_cam_en: pp2800-avdd {
0810 rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
0811 };
0812
0813 ucam_rst: ucam_rst {
0814 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
0815 };
0816
0817 wcam_rst: wcam_rst {
0818 rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
0819 };
0820 };
0821
0822 digitizer {
0823 pen_int_odl: pen-int-odl {
0824 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
0825 };
0826
0827 pen_reset_l: pen-reset-l {
0828 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
0829 };
0830 };
0831
0832 discrete-regulators {
0833 display_rst_l: display-rst-l {
0834 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
0835 };
0836
0837 ppvarp_lcd_en: ppvarp-lcd-en {
0838 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
0839 };
0840
0841 ppvarn_lcd_en: ppvarn-lcd-en {
0842 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
0843 };
0844 };
0845
0846 dmic {
0847 dmic_en: dmic-en {
0848 rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
0849 };
0850 };
0851
0852 pen {
0853 pen_eject_odl: pen-eject-odl {
0854 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
0855 };
0856 };
0857
0858 tpm {
0859 h1_int_od_l: h1-int-od-l {
0860 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
0861 };
0862 };
0863 };
0864
0865 &wifi {
0866 bt_en_1v8_l: bt-en-1v8-l {
0867 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
0868 };
0869
0870 wlan_pd_1v8_l: wlan-pd-1v8-l {
0871 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
0872 };
0873
0874 /* Default pull-up, but just to be clear */
0875 wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
0876 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
0877 };
0878
0879 wifi_perst_l: wifi-perst-l {
0880 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
0881 };
0882
0883 wlan_host_wake_l: wlan-host-wake-l {
0884 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
0885 };
0886 };
