0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
0004 */
0005
0006 #include <dt-bindings/clock/rk3368-cru.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/pinctrl/rockchip.h>
0011 #include <dt-bindings/power/rk3368-power.h>
0012 #include <dt-bindings/soc/rockchip,boot-mode.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 compatible = "rockchip,rk3368";
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 ethernet0 = &gmac;
0023 i2c0 = &i2c0;
0024 i2c1 = &i2c1;
0025 i2c2 = &i2c2;
0026 i2c3 = &i2c3;
0027 i2c4 = &i2c4;
0028 i2c5 = &i2c5;
0029 serial0 = &uart0;
0030 serial1 = &uart1;
0031 serial2 = &uart2;
0032 serial3 = &uart3;
0033 serial4 = &uart4;
0034 spi0 = &spi0;
0035 spi1 = &spi1;
0036 spi2 = &spi2;
0037 };
0038
0039 cpus {
0040 #address-cells = <0x2>;
0041 #size-cells = <0x0>;
0042
0043 cpu-map {
0044 cluster0 {
0045 core0 {
0046 cpu = <&cpu_b0>;
0047 };
0048 core1 {
0049 cpu = <&cpu_b1>;
0050 };
0051 core2 {
0052 cpu = <&cpu_b2>;
0053 };
0054 core3 {
0055 cpu = <&cpu_b3>;
0056 };
0057 };
0058
0059 cluster1 {
0060 core0 {
0061 cpu = <&cpu_l0>;
0062 };
0063 core1 {
0064 cpu = <&cpu_l1>;
0065 };
0066 core2 {
0067 cpu = <&cpu_l2>;
0068 };
0069 core3 {
0070 cpu = <&cpu_l3>;
0071 };
0072 };
0073 };
0074
0075 cpu_l0: cpu@0 {
0076 device_type = "cpu";
0077 compatible = "arm,cortex-a53";
0078 reg = <0x0 0x0>;
0079 enable-method = "psci";
0080 #cooling-cells = <2>; /* min followed by max */
0081 };
0082
0083 cpu_l1: cpu@1 {
0084 device_type = "cpu";
0085 compatible = "arm,cortex-a53";
0086 reg = <0x0 0x1>;
0087 enable-method = "psci";
0088 #cooling-cells = <2>; /* min followed by max */
0089 };
0090
0091 cpu_l2: cpu@2 {
0092 device_type = "cpu";
0093 compatible = "arm,cortex-a53";
0094 reg = <0x0 0x2>;
0095 enable-method = "psci";
0096 #cooling-cells = <2>; /* min followed by max */
0097 };
0098
0099 cpu_l3: cpu@3 {
0100 device_type = "cpu";
0101 compatible = "arm,cortex-a53";
0102 reg = <0x0 0x3>;
0103 enable-method = "psci";
0104 #cooling-cells = <2>; /* min followed by max */
0105 };
0106
0107 cpu_b0: cpu@100 {
0108 device_type = "cpu";
0109 compatible = "arm,cortex-a53";
0110 reg = <0x0 0x100>;
0111 enable-method = "psci";
0112 #cooling-cells = <2>; /* min followed by max */
0113 };
0114
0115 cpu_b1: cpu@101 {
0116 device_type = "cpu";
0117 compatible = "arm,cortex-a53";
0118 reg = <0x0 0x101>;
0119 enable-method = "psci";
0120 #cooling-cells = <2>; /* min followed by max */
0121 };
0122
0123 cpu_b2: cpu@102 {
0124 device_type = "cpu";
0125 compatible = "arm,cortex-a53";
0126 reg = <0x0 0x102>;
0127 enable-method = "psci";
0128 #cooling-cells = <2>; /* min followed by max */
0129 };
0130
0131 cpu_b3: cpu@103 {
0132 device_type = "cpu";
0133 compatible = "arm,cortex-a53";
0134 reg = <0x0 0x103>;
0135 enable-method = "psci";
0136 #cooling-cells = <2>; /* min followed by max */
0137 };
0138 };
0139
0140 arm-pmu {
0141 compatible = "arm,armv8-pmuv3";
0142 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0150 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
0151 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
0152 <&cpu_b2>, <&cpu_b3>;
0153 };
0154
0155 psci {
0156 compatible = "arm,psci-0.2";
0157 method = "smc";
0158 };
0159
0160 timer {
0161 compatible = "arm,armv8-timer";
0162 interrupts = <GIC_PPI 13
0163 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
0164 <GIC_PPI 14
0165 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
0166 <GIC_PPI 11
0167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
0168 <GIC_PPI 10
0169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0170 };
0171
0172 xin24m: oscillator {
0173 compatible = "fixed-clock";
0174 clock-frequency = <24000000>;
0175 clock-output-names = "xin24m";
0176 #clock-cells = <0>;
0177 };
0178
0179 sdmmc: mmc@ff0c0000 {
0180 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
0181 reg = <0x0 0xff0c0000 0x0 0x4000>;
0182 max-frequency = <150000000>;
0183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
0184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
0185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0186 fifo-depth = <0x100>;
0187 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0188 resets = <&cru SRST_MMC0>;
0189 reset-names = "reset";
0190 status = "disabled";
0191 };
0192
0193 sdio0: mmc@ff0d0000 {
0194 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
0195 reg = <0x0 0xff0d0000 0x0 0x4000>;
0196 max-frequency = <150000000>;
0197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
0198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
0199 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0200 fifo-depth = <0x100>;
0201 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0202 resets = <&cru SRST_SDIO0>;
0203 reset-names = "reset";
0204 status = "disabled";
0205 };
0206
0207 emmc: mmc@ff0f0000 {
0208 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
0209 reg = <0x0 0xff0f0000 0x0 0x4000>;
0210 max-frequency = <150000000>;
0211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0214 fifo-depth = <0x100>;
0215 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0216 resets = <&cru SRST_EMMC>;
0217 reset-names = "reset";
0218 status = "disabled";
0219 };
0220
0221 saradc: saradc@ff100000 {
0222 compatible = "rockchip,saradc";
0223 reg = <0x0 0xff100000 0x0 0x100>;
0224 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0225 #io-channel-cells = <1>;
0226 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
0227 clock-names = "saradc", "apb_pclk";
0228 resets = <&cru SRST_SARADC>;
0229 reset-names = "saradc-apb";
0230 status = "disabled";
0231 };
0232
0233 spi0: spi@ff110000 {
0234 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
0235 reg = <0x0 0xff110000 0x0 0x1000>;
0236 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
0237 clock-names = "spiclk", "apb_pclk";
0238 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0239 pinctrl-names = "default";
0240 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
0241 #address-cells = <1>;
0242 #size-cells = <0>;
0243 status = "disabled";
0244 };
0245
0246 spi1: spi@ff120000 {
0247 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
0248 reg = <0x0 0xff120000 0x0 0x1000>;
0249 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
0250 clock-names = "spiclk", "apb_pclk";
0251 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 status = "disabled";
0257 };
0258
0259 spi2: spi@ff130000 {
0260 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
0261 reg = <0x0 0xff130000 0x0 0x1000>;
0262 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
0263 clock-names = "spiclk", "apb_pclk";
0264 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0265 pinctrl-names = "default";
0266 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
0267 #address-cells = <1>;
0268 #size-cells = <0>;
0269 status = "disabled";
0270 };
0271
0272 i2c2: i2c@ff140000 {
0273 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0274 reg = <0x0 0xff140000 0x0 0x1000>;
0275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 clock-names = "i2c";
0279 clocks = <&cru PCLK_I2C2>;
0280 pinctrl-names = "default";
0281 pinctrl-0 = <&i2c2_xfer>;
0282 status = "disabled";
0283 };
0284
0285 i2c3: i2c@ff150000 {
0286 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0287 reg = <0x0 0xff150000 0x0 0x1000>;
0288 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 clock-names = "i2c";
0292 clocks = <&cru PCLK_I2C3>;
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&i2c3_xfer>;
0295 status = "disabled";
0296 };
0297
0298 i2c4: i2c@ff160000 {
0299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0300 reg = <0x0 0xff160000 0x0 0x1000>;
0301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304 clock-names = "i2c";
0305 clocks = <&cru PCLK_I2C4>;
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&i2c4_xfer>;
0308 status = "disabled";
0309 };
0310
0311 i2c5: i2c@ff170000 {
0312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0313 reg = <0x0 0xff170000 0x0 0x1000>;
0314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0315 #address-cells = <1>;
0316 #size-cells = <0>;
0317 clock-names = "i2c";
0318 clocks = <&cru PCLK_I2C5>;
0319 pinctrl-names = "default";
0320 pinctrl-0 = <&i2c5_xfer>;
0321 status = "disabled";
0322 };
0323
0324 uart0: serial@ff180000 {
0325 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
0326 reg = <0x0 0xff180000 0x0 0x100>;
0327 clock-frequency = <24000000>;
0328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0329 clock-names = "baudclk", "apb_pclk";
0330 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0331 reg-shift = <2>;
0332 reg-io-width = <4>;
0333 status = "disabled";
0334 };
0335
0336 uart1: serial@ff190000 {
0337 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
0338 reg = <0x0 0xff190000 0x0 0x100>;
0339 clock-frequency = <24000000>;
0340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0341 clock-names = "baudclk", "apb_pclk";
0342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0343 reg-shift = <2>;
0344 reg-io-width = <4>;
0345 status = "disabled";
0346 };
0347
0348 uart3: serial@ff1b0000 {
0349 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
0350 reg = <0x0 0xff1b0000 0x0 0x100>;
0351 clock-frequency = <24000000>;
0352 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
0353 clock-names = "baudclk", "apb_pclk";
0354 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0355 reg-shift = <2>;
0356 reg-io-width = <4>;
0357 status = "disabled";
0358 };
0359
0360 uart4: serial@ff1c0000 {
0361 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
0362 reg = <0x0 0xff1c0000 0x0 0x100>;
0363 clock-frequency = <24000000>;
0364 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
0365 clock-names = "baudclk", "apb_pclk";
0366 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0367 reg-shift = <2>;
0368 reg-io-width = <4>;
0369 status = "disabled";
0370 };
0371
0372 dmac_peri: dma-controller@ff250000 {
0373 compatible = "arm,pl330", "arm,primecell";
0374 reg = <0x0 0xff250000 0x0 0x4000>;
0375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0376 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0377 #dma-cells = <1>;
0378 arm,pl330-broken-no-flushp;
0379 arm,pl330-periph-burst;
0380 clocks = <&cru ACLK_DMAC_PERI>;
0381 clock-names = "apb_pclk";
0382 };
0383
0384 thermal-zones {
0385 cpu_thermal: cpu-thermal {
0386 polling-delay-passive = <100>; /* milliseconds */
0387 polling-delay = <5000>; /* milliseconds */
0388
0389 thermal-sensors = <&tsadc 0>;
0390
0391 trips {
0392 cpu_alert0: cpu_alert0 {
0393 temperature = <75000>; /* millicelsius */
0394 hysteresis = <2000>; /* millicelsius */
0395 type = "passive";
0396 };
0397 cpu_alert1: cpu_alert1 {
0398 temperature = <80000>; /* millicelsius */
0399 hysteresis = <2000>; /* millicelsius */
0400 type = "passive";
0401 };
0402 cpu_crit: cpu_crit {
0403 temperature = <95000>; /* millicelsius */
0404 hysteresis = <2000>; /* millicelsius */
0405 type = "critical";
0406 };
0407 };
0408
0409 cooling-maps {
0410 map0 {
0411 trip = <&cpu_alert0>;
0412 cooling-device =
0413 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0414 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0415 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0416 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0417 };
0418 map1 {
0419 trip = <&cpu_alert1>;
0420 cooling-device =
0421 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0422 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0423 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0424 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0425 };
0426 };
0427 };
0428
0429 gpu_thermal: gpu-thermal {
0430 polling-delay-passive = <100>; /* milliseconds */
0431 polling-delay = <5000>; /* milliseconds */
0432
0433 thermal-sensors = <&tsadc 1>;
0434
0435 trips {
0436 gpu_alert0: gpu_alert0 {
0437 temperature = <80000>; /* millicelsius */
0438 hysteresis = <2000>; /* millicelsius */
0439 type = "passive";
0440 };
0441 gpu_crit: gpu_crit {
0442 temperature = <115000>; /* millicelsius */
0443 hysteresis = <2000>; /* millicelsius */
0444 type = "critical";
0445 };
0446 };
0447
0448 cooling-maps {
0449 map0 {
0450 trip = <&gpu_alert0>;
0451 cooling-device =
0452 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0453 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0454 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0455 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0456 };
0457 };
0458 };
0459 };
0460
0461 tsadc: tsadc@ff280000 {
0462 compatible = "rockchip,rk3368-tsadc";
0463 reg = <0x0 0xff280000 0x0 0x100>;
0464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0465 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0466 clock-names = "tsadc", "apb_pclk";
0467 resets = <&cru SRST_TSADC>;
0468 reset-names = "tsadc-apb";
0469 pinctrl-names = "init", "default", "sleep";
0470 pinctrl-0 = <&otp_pin>;
0471 pinctrl-1 = <&otp_out>;
0472 pinctrl-2 = <&otp_pin>;
0473 #thermal-sensor-cells = <1>;
0474 rockchip,hw-tshut-temp = <95000>;
0475 status = "disabled";
0476 };
0477
0478 gmac: ethernet@ff290000 {
0479 compatible = "rockchip,rk3368-gmac";
0480 reg = <0x0 0xff290000 0x0 0x10000>;
0481 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0482 interrupt-names = "macirq";
0483 rockchip,grf = <&grf>;
0484 clocks = <&cru SCLK_MAC>,
0485 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
0486 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
0487 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
0488 clock-names = "stmmaceth",
0489 "mac_clk_rx", "mac_clk_tx",
0490 "clk_mac_ref", "clk_mac_refout",
0491 "aclk_mac", "pclk_mac";
0492 status = "disabled";
0493 };
0494
0495 usb_host0_ehci: usb@ff500000 {
0496 compatible = "generic-ehci";
0497 reg = <0x0 0xff500000 0x0 0x100>;
0498 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0499 clocks = <&cru HCLK_HOST0>;
0500 status = "disabled";
0501 };
0502
0503 usb_otg: usb@ff580000 {
0504 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
0505 "snps,dwc2";
0506 reg = <0x0 0xff580000 0x0 0x40000>;
0507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0508 clocks = <&cru HCLK_OTG0>;
0509 clock-names = "otg";
0510 dr_mode = "otg";
0511 g-np-tx-fifo-size = <16>;
0512 g-rx-fifo-size = <275>;
0513 g-tx-fifo-size = <256 128 128 64 64 32>;
0514 status = "disabled";
0515 };
0516
0517 dmac_bus: dma-controller@ff600000 {
0518 compatible = "arm,pl330", "arm,primecell";
0519 reg = <0x0 0xff600000 0x0 0x4000>;
0520 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0521 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0522 #dma-cells = <1>;
0523 arm,pl330-broken-no-flushp;
0524 arm,pl330-periph-burst;
0525 clocks = <&cru ACLK_DMAC_BUS>;
0526 clock-names = "apb_pclk";
0527 };
0528
0529 i2c0: i2c@ff650000 {
0530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0531 reg = <0x0 0xff650000 0x0 0x1000>;
0532 clocks = <&cru PCLK_I2C0>;
0533 clock-names = "i2c";
0534 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&i2c0_xfer>;
0537 #address-cells = <1>;
0538 #size-cells = <0>;
0539 status = "disabled";
0540 };
0541
0542 i2c1: i2c@ff660000 {
0543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
0544 reg = <0x0 0xff660000 0x0 0x1000>;
0545 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0546 #address-cells = <1>;
0547 #size-cells = <0>;
0548 clock-names = "i2c";
0549 clocks = <&cru PCLK_I2C1>;
0550 pinctrl-names = "default";
0551 pinctrl-0 = <&i2c1_xfer>;
0552 status = "disabled";
0553 };
0554
0555 pwm0: pwm@ff680000 {
0556 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
0557 reg = <0x0 0xff680000 0x0 0x10>;
0558 #pwm-cells = <3>;
0559 pinctrl-names = "default";
0560 pinctrl-0 = <&pwm0_pin>;
0561 clocks = <&cru PCLK_PWM1>;
0562 status = "disabled";
0563 };
0564
0565 pwm1: pwm@ff680010 {
0566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
0567 reg = <0x0 0xff680010 0x0 0x10>;
0568 #pwm-cells = <3>;
0569 pinctrl-names = "default";
0570 pinctrl-0 = <&pwm1_pin>;
0571 clocks = <&cru PCLK_PWM1>;
0572 status = "disabled";
0573 };
0574
0575 pwm2: pwm@ff680020 {
0576 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
0577 reg = <0x0 0xff680020 0x0 0x10>;
0578 #pwm-cells = <3>;
0579 clocks = <&cru PCLK_PWM1>;
0580 status = "disabled";
0581 };
0582
0583 pwm3: pwm@ff680030 {
0584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
0585 reg = <0x0 0xff680030 0x0 0x10>;
0586 #pwm-cells = <3>;
0587 pinctrl-names = "default";
0588 pinctrl-0 = <&pwm3_pin>;
0589 clocks = <&cru PCLK_PWM1>;
0590 status = "disabled";
0591 };
0592
0593 uart2: serial@ff690000 {
0594 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
0595 reg = <0x0 0xff690000 0x0 0x100>;
0596 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0597 clock-names = "baudclk", "apb_pclk";
0598 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0599 pinctrl-names = "default";
0600 pinctrl-0 = <&uart2_xfer>;
0601 reg-shift = <2>;
0602 reg-io-width = <4>;
0603 status = "disabled";
0604 };
0605
0606 mbox: mbox@ff6b0000 {
0607 compatible = "rockchip,rk3368-mailbox";
0608 reg = <0x0 0xff6b0000 0x0 0x1000>;
0609 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0610 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0611 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0612 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0613 clocks = <&cru PCLK_MAILBOX>;
0614 clock-names = "pclk_mailbox";
0615 #mbox-cells = <1>;
0616 status = "disabled";
0617 };
0618
0619 pmu: power-management@ff730000 {
0620 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
0621 reg = <0x0 0xff730000 0x0 0x1000>;
0622
0623 power: power-controller {
0624 compatible = "rockchip,rk3368-power-controller";
0625 #power-domain-cells = <1>;
0626 #address-cells = <1>;
0627 #size-cells = <0>;
0628
0629 /*
0630 * Note: Although SCLK_* are the working clocks
0631 * of device without including on the NOC, needed for
0632 * synchronous reset.
0633 *
0634 * The clocks on the which NOC:
0635 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
0636 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
0637 * ACLK_RGA is on ACLK_RGA_NIU.
0638 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
0639 *
0640 * Which clock are device clocks:
0641 * clocks devices
0642 * *_IEP IEP:Image Enhancement Processor
0643 * *_ISP ISP:Image Signal Processing
0644 * *_VIP VIP:Video Input Processor
0645 * *_VOP* VOP:Visual Output Processor
0646 * *_RGA RGA
0647 * *_EDP* EDP
0648 * *_DPHY* LVDS
0649 * *_HDMI HDMI
0650 * *_MIPI_* MIPI
0651 */
0652 power-domain@RK3368_PD_VIO {
0653 reg = <RK3368_PD_VIO>;
0654 clocks = <&cru ACLK_IEP>,
0655 <&cru ACLK_ISP>,
0656 <&cru ACLK_VIP>,
0657 <&cru ACLK_RGA>,
0658 <&cru ACLK_VOP>,
0659 <&cru ACLK_VOP_IEP>,
0660 <&cru DCLK_VOP>,
0661 <&cru HCLK_IEP>,
0662 <&cru HCLK_ISP>,
0663 <&cru HCLK_RGA>,
0664 <&cru HCLK_VIP>,
0665 <&cru HCLK_VOP>,
0666 <&cru HCLK_VIO_HDCPMMU>,
0667 <&cru PCLK_EDP_CTRL>,
0668 <&cru PCLK_HDMI_CTRL>,
0669 <&cru PCLK_HDCP>,
0670 <&cru PCLK_ISP>,
0671 <&cru PCLK_VIP>,
0672 <&cru PCLK_DPHYRX>,
0673 <&cru PCLK_DPHYTX0>,
0674 <&cru PCLK_MIPI_CSI>,
0675 <&cru PCLK_MIPI_DSI0>,
0676 <&cru SCLK_VOP0_PWM>,
0677 <&cru SCLK_EDP_24M>,
0678 <&cru SCLK_EDP>,
0679 <&cru SCLK_HDCP>,
0680 <&cru SCLK_ISP>,
0681 <&cru SCLK_RGA>,
0682 <&cru SCLK_HDMI_CEC>,
0683 <&cru SCLK_HDMI_HDCP>;
0684 pm_qos = <&qos_iep>,
0685 <&qos_isp_r0>,
0686 <&qos_isp_r1>,
0687 <&qos_isp_w0>,
0688 <&qos_isp_w1>,
0689 <&qos_vip>,
0690 <&qos_vop>,
0691 <&qos_rga_r>,
0692 <&qos_rga_w>;
0693 #power-domain-cells = <0>;
0694 };
0695
0696 /*
0697 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
0698 * (video endecoder & decoder) clocks that on the
0699 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
0700 */
0701 power-domain@RK3368_PD_VIDEO {
0702 reg = <RK3368_PD_VIDEO>;
0703 clocks = <&cru ACLK_VIDEO>,
0704 <&cru HCLK_VIDEO>,
0705 <&cru SCLK_HEVC_CABAC>,
0706 <&cru SCLK_HEVC_CORE>;
0707 pm_qos = <&qos_hevc_r>,
0708 <&qos_vpu_r>,
0709 <&qos_vpu_w>;
0710 #power-domain-cells = <0>;
0711 };
0712
0713 /*
0714 * Note: ACLK_GPU is the GPU clock,
0715 * and on the ACLK_GPU_NIU (NOC).
0716 */
0717 power-domain@RK3368_PD_GPU_1 {
0718 reg = <RK3368_PD_GPU_1>;
0719 clocks = <&cru ACLK_GPU_CFG>,
0720 <&cru ACLK_GPU_MEM>,
0721 <&cru SCLK_GPU_CORE>;
0722 pm_qos = <&qos_gpu>;
0723 #power-domain-cells = <0>;
0724 };
0725 };
0726 };
0727
0728 pmugrf: syscon@ff738000 {
0729 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
0730 reg = <0x0 0xff738000 0x0 0x1000>;
0731
0732 pmu_io_domains: io-domains {
0733 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
0734 status = "disabled";
0735 };
0736
0737 reboot-mode {
0738 compatible = "syscon-reboot-mode";
0739 offset = <0x200>;
0740 mode-normal = <BOOT_NORMAL>;
0741 mode-recovery = <BOOT_RECOVERY>;
0742 mode-bootloader = <BOOT_FASTBOOT>;
0743 mode-loader = <BOOT_BL_DOWNLOAD>;
0744 };
0745 };
0746
0747 cru: clock-controller@ff760000 {
0748 compatible = "rockchip,rk3368-cru";
0749 reg = <0x0 0xff760000 0x0 0x1000>;
0750 clocks = <&xin24m>;
0751 clock-names = "xin24m";
0752 rockchip,grf = <&grf>;
0753 #clock-cells = <1>;
0754 #reset-cells = <1>;
0755 };
0756
0757 grf: syscon@ff770000 {
0758 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
0759 reg = <0x0 0xff770000 0x0 0x1000>;
0760
0761 io_domains: io-domains {
0762 compatible = "rockchip,rk3368-io-voltage-domain";
0763 status = "disabled";
0764 };
0765 };
0766
0767 wdt: watchdog@ff800000 {
0768 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
0769 reg = <0x0 0xff800000 0x0 0x100>;
0770 clocks = <&cru PCLK_WDT>;
0771 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0772 status = "disabled";
0773 };
0774
0775 timer0: timer@ff810000 {
0776 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
0777 reg = <0x0 0xff810000 0x0 0x20>;
0778 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0779 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
0780 clock-names = "pclk", "timer";
0781 };
0782
0783 spdif: spdif@ff880000 {
0784 compatible = "rockchip,rk3368-spdif";
0785 reg = <0x0 0xff880000 0x0 0x1000>;
0786 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0787 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
0788 clock-names = "mclk", "hclk";
0789 dmas = <&dmac_bus 3>;
0790 dma-names = "tx";
0791 pinctrl-names = "default";
0792 pinctrl-0 = <&spdif_tx>;
0793 status = "disabled";
0794 };
0795
0796 i2s_2ch: i2s-2ch@ff890000 {
0797 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
0798 reg = <0x0 0xff890000 0x0 0x1000>;
0799 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0800 clock-names = "i2s_clk", "i2s_hclk";
0801 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
0802 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
0803 dma-names = "tx", "rx";
0804 status = "disabled";
0805 };
0806
0807 i2s_8ch: i2s-8ch@ff898000 {
0808 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
0809 reg = <0x0 0xff898000 0x0 0x1000>;
0810 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0811 clock-names = "i2s_clk", "i2s_hclk";
0812 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
0813 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
0814 dma-names = "tx", "rx";
0815 pinctrl-names = "default";
0816 pinctrl-0 = <&i2s_8ch_bus>;
0817 status = "disabled";
0818 };
0819
0820 iep_mmu: iommu@ff900800 {
0821 compatible = "rockchip,iommu";
0822 reg = <0x0 0xff900800 0x0 0x100>;
0823 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0824 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
0825 clock-names = "aclk", "iface";
0826 power-domains = <&power RK3368_PD_VIO>;
0827 #iommu-cells = <0>;
0828 status = "disabled";
0829 };
0830
0831 isp_mmu: iommu@ff914000 {
0832 compatible = "rockchip,iommu";
0833 reg = <0x0 0xff914000 0x0 0x100>,
0834 <0x0 0xff915000 0x0 0x100>;
0835 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0836 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
0837 clock-names = "aclk", "iface";
0838 #iommu-cells = <0>;
0839 power-domains = <&power RK3368_PD_VIO>;
0840 rockchip,disable-mmu-reset;
0841 status = "disabled";
0842 };
0843
0844 vop_mmu: iommu@ff930300 {
0845 compatible = "rockchip,iommu";
0846 reg = <0x0 0xff930300 0x0 0x100>;
0847 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0848 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
0849 clock-names = "aclk", "iface";
0850 power-domains = <&power RK3368_PD_VIO>;
0851 #iommu-cells = <0>;
0852 status = "disabled";
0853 };
0854
0855 hevc_mmu: iommu@ff9a0440 {
0856 compatible = "rockchip,iommu";
0857 reg = <0x0 0xff9a0440 0x0 0x40>,
0858 <0x0 0xff9a0480 0x0 0x40>;
0859 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0860 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
0861 clock-names = "aclk", "iface";
0862 #iommu-cells = <0>;
0863 status = "disabled";
0864 };
0865
0866 vpu_mmu: iommu@ff9a0800 {
0867 compatible = "rockchip,iommu";
0868 reg = <0x0 0xff9a0800 0x0 0x100>;
0869 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0870 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0871 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
0872 clock-names = "aclk", "iface";
0873 #iommu-cells = <0>;
0874 status = "disabled";
0875 };
0876
0877 qos_iep: qos@ffad0000 {
0878 compatible = "rockchip,rk3368-qos", "syscon";
0879 reg = <0x0 0xffad0000 0x0 0x20>;
0880 };
0881
0882 qos_isp_r0: qos@ffad0080 {
0883 compatible = "rockchip,rk3368-qos", "syscon";
0884 reg = <0x0 0xffad0080 0x0 0x20>;
0885 };
0886
0887 qos_isp_r1: qos@ffad0100 {
0888 compatible = "rockchip,rk3368-qos", "syscon";
0889 reg = <0x0 0xffad0100 0x0 0x20>;
0890 };
0891
0892 qos_isp_w0: qos@ffad0180 {
0893 compatible = "rockchip,rk3368-qos", "syscon";
0894 reg = <0x0 0xffad0180 0x0 0x20>;
0895 };
0896
0897 qos_isp_w1: qos@ffad0200 {
0898 compatible = "rockchip,rk3368-qos", "syscon";
0899 reg = <0x0 0xffad0200 0x0 0x20>;
0900 };
0901
0902 qos_vip: qos@ffad0280 {
0903 compatible = "rockchip,rk3368-qos", "syscon";
0904 reg = <0x0 0xffad0280 0x0 0x20>;
0905 };
0906
0907 qos_vop: qos@ffad0300 {
0908 compatible = "rockchip,rk3368-qos", "syscon";
0909 reg = <0x0 0xffad0300 0x0 0x20>;
0910 };
0911
0912 qos_rga_r: qos@ffad0380 {
0913 compatible = "rockchip,rk3368-qos", "syscon";
0914 reg = <0x0 0xffad0380 0x0 0x20>;
0915 };
0916
0917 qos_rga_w: qos@ffad0400 {
0918 compatible = "rockchip,rk3368-qos", "syscon";
0919 reg = <0x0 0xffad0400 0x0 0x20>;
0920 };
0921
0922 qos_hevc_r: qos@ffae0000 {
0923 compatible = "rockchip,rk3368-qos", "syscon";
0924 reg = <0x0 0xffae0000 0x0 0x20>;
0925 };
0926
0927 qos_vpu_r: qos@ffae0100 {
0928 compatible = "rockchip,rk3368-qos", "syscon";
0929 reg = <0x0 0xffae0100 0x0 0x20>;
0930 };
0931
0932 qos_vpu_w: qos@ffae0180 {
0933 compatible = "rockchip,rk3368-qos", "syscon";
0934 reg = <0x0 0xffae0180 0x0 0x20>;
0935 };
0936
0937 qos_gpu: qos@ffaf0000 {
0938 compatible = "rockchip,rk3368-qos", "syscon";
0939 reg = <0x0 0xffaf0000 0x0 0x20>;
0940 };
0941
0942 efuse256: efuse@ffb00000 {
0943 compatible = "rockchip,rk3368-efuse";
0944 reg = <0x0 0xffb00000 0x0 0x20>;
0945 #address-cells = <1>;
0946 #size-cells = <1>;
0947 clocks = <&cru PCLK_EFUSE256>;
0948 clock-names = "pclk_efuse";
0949
0950 cpu_leakage: cpu-leakage@17 {
0951 reg = <0x17 0x1>;
0952 };
0953 temp_adjust: temp-adjust@1f {
0954 reg = <0x1f 0x1>;
0955 };
0956 };
0957
0958 gic: interrupt-controller@ffb71000 {
0959 compatible = "arm,gic-400";
0960 interrupt-controller;
0961 #interrupt-cells = <3>;
0962 #address-cells = <0>;
0963
0964 reg = <0x0 0xffb71000 0x0 0x1000>,
0965 <0x0 0xffb72000 0x0 0x2000>,
0966 <0x0 0xffb74000 0x0 0x2000>,
0967 <0x0 0xffb76000 0x0 0x2000>;
0968 interrupts = <GIC_PPI 9
0969 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0970 };
0971
0972 pinctrl: pinctrl {
0973 compatible = "rockchip,rk3368-pinctrl";
0974 rockchip,grf = <&grf>;
0975 rockchip,pmu = <&pmugrf>;
0976 #address-cells = <0x2>;
0977 #size-cells = <0x2>;
0978 ranges;
0979
0980 gpio0: gpio@ff750000 {
0981 compatible = "rockchip,gpio-bank";
0982 reg = <0x0 0xff750000 0x0 0x100>;
0983 clocks = <&cru PCLK_GPIO0>;
0984 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
0985
0986 gpio-controller;
0987 #gpio-cells = <0x2>;
0988
0989 interrupt-controller;
0990 #interrupt-cells = <0x2>;
0991 };
0992
0993 gpio1: gpio@ff780000 {
0994 compatible = "rockchip,gpio-bank";
0995 reg = <0x0 0xff780000 0x0 0x100>;
0996 clocks = <&cru PCLK_GPIO1>;
0997 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
0998
0999 gpio-controller;
1000 #gpio-cells = <0x2>;
1001
1002 interrupt-controller;
1003 #interrupt-cells = <0x2>;
1004 };
1005
1006 gpio2: gpio@ff790000 {
1007 compatible = "rockchip,gpio-bank";
1008 reg = <0x0 0xff790000 0x0 0x100>;
1009 clocks = <&cru PCLK_GPIO2>;
1010 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1011
1012 gpio-controller;
1013 #gpio-cells = <0x2>;
1014
1015 interrupt-controller;
1016 #interrupt-cells = <0x2>;
1017 };
1018
1019 gpio3: gpio@ff7a0000 {
1020 compatible = "rockchip,gpio-bank";
1021 reg = <0x0 0xff7a0000 0x0 0x100>;
1022 clocks = <&cru PCLK_GPIO3>;
1023 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1024
1025 gpio-controller;
1026 #gpio-cells = <0x2>;
1027
1028 interrupt-controller;
1029 #interrupt-cells = <0x2>;
1030 };
1031
1032 pcfg_pull_up: pcfg-pull-up {
1033 bias-pull-up;
1034 };
1035
1036 pcfg_pull_down: pcfg-pull-down {
1037 bias-pull-down;
1038 };
1039
1040 pcfg_pull_none: pcfg-pull-none {
1041 bias-disable;
1042 };
1043
1044 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1045 bias-disable;
1046 drive-strength = <12>;
1047 };
1048
1049 emmc {
1050 emmc_clk: emmc-clk {
1051 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1052 };
1053
1054 emmc_cmd: emmc-cmd {
1055 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1056 };
1057
1058 emmc_pwr: emmc-pwr {
1059 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1060 };
1061
1062 emmc_bus1: emmc-bus1 {
1063 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1064 };
1065
1066 emmc_bus4: emmc-bus4 {
1067 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1068 <1 RK_PC3 2 &pcfg_pull_up>,
1069 <1 RK_PC4 2 &pcfg_pull_up>,
1070 <1 RK_PC5 2 &pcfg_pull_up>;
1071 };
1072
1073 emmc_bus8: emmc-bus8 {
1074 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1075 <1 RK_PC3 2 &pcfg_pull_up>,
1076 <1 RK_PC4 2 &pcfg_pull_up>,
1077 <1 RK_PC5 2 &pcfg_pull_up>,
1078 <1 RK_PC6 2 &pcfg_pull_up>,
1079 <1 RK_PC7 2 &pcfg_pull_up>,
1080 <1 RK_PD0 2 &pcfg_pull_up>,
1081 <1 RK_PD1 2 &pcfg_pull_up>;
1082 };
1083 };
1084
1085 gmac {
1086 rgmii_pins: rgmii-pins {
1087 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1088 <3 RK_PD0 1 &pcfg_pull_none>,
1089 <3 RK_PC3 1 &pcfg_pull_none>,
1090 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1091 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1092 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1093 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1094 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1095 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1096 <3 RK_PB7 1 &pcfg_pull_none>,
1097 <3 RK_PC0 1 &pcfg_pull_none>,
1098 <3 RK_PC1 1 &pcfg_pull_none>,
1099 <3 RK_PC2 1 &pcfg_pull_none>,
1100 <3 RK_PD1 1 &pcfg_pull_none>,
1101 <3 RK_PC4 1 &pcfg_pull_none>;
1102 };
1103
1104 rmii_pins: rmii-pins {
1105 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1106 <3 RK_PD0 1 &pcfg_pull_none>,
1107 <3 RK_PC3 1 &pcfg_pull_none>,
1108 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1109 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1110 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1111 <3 RK_PB7 1 &pcfg_pull_none>,
1112 <3 RK_PC0 1 &pcfg_pull_none>,
1113 <3 RK_PC4 1 &pcfg_pull_none>,
1114 <3 RK_PC5 1 &pcfg_pull_none>;
1115 };
1116 };
1117
1118 i2c0 {
1119 i2c0_xfer: i2c0-xfer {
1120 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1121 <0 RK_PA7 1 &pcfg_pull_none>;
1122 };
1123 };
1124
1125 i2c1 {
1126 i2c1_xfer: i2c1-xfer {
1127 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1128 <2 RK_PC6 1 &pcfg_pull_none>;
1129 };
1130 };
1131
1132 i2c2 {
1133 i2c2_xfer: i2c2-xfer {
1134 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1135 <3 RK_PD7 2 &pcfg_pull_none>;
1136 };
1137 };
1138
1139 i2c3 {
1140 i2c3_xfer: i2c3-xfer {
1141 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1142 <1 RK_PC1 1 &pcfg_pull_none>;
1143 };
1144 };
1145
1146 i2c4 {
1147 i2c4_xfer: i2c4-xfer {
1148 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1149 <3 RK_PD1 2 &pcfg_pull_none>;
1150 };
1151 };
1152
1153 i2c5 {
1154 i2c5_xfer: i2c5-xfer {
1155 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1156 <3 RK_PD3 2 &pcfg_pull_none>;
1157 };
1158 };
1159
1160 i2s {
1161 i2s_8ch_bus: i2s-8ch-bus {
1162 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1163 <2 RK_PB5 1 &pcfg_pull_none>,
1164 <2 RK_PB6 1 &pcfg_pull_none>,
1165 <2 RK_PB7 1 &pcfg_pull_none>,
1166 <2 RK_PC0 1 &pcfg_pull_none>,
1167 <2 RK_PC1 1 &pcfg_pull_none>,
1168 <2 RK_PC2 1 &pcfg_pull_none>,
1169 <2 RK_PC3 1 &pcfg_pull_none>,
1170 <2 RK_PC4 1 &pcfg_pull_none>;
1171 };
1172 };
1173
1174 pwm0 {
1175 pwm0_pin: pwm0-pin {
1176 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1177 };
1178 };
1179
1180 pwm1 {
1181 pwm1_pin: pwm1-pin {
1182 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1183 };
1184 };
1185
1186 pwm3 {
1187 pwm3_pin: pwm3-pin {
1188 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1189 };
1190 };
1191
1192 sdio0 {
1193 sdio0_bus1: sdio0-bus1 {
1194 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1195 };
1196
1197 sdio0_bus4: sdio0-bus4 {
1198 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1199 <2 RK_PD5 1 &pcfg_pull_up>,
1200 <2 RK_PD6 1 &pcfg_pull_up>,
1201 <2 RK_PD7 1 &pcfg_pull_up>;
1202 };
1203
1204 sdio0_cmd: sdio0-cmd {
1205 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1206 };
1207
1208 sdio0_clk: sdio0-clk {
1209 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1210 };
1211
1212 sdio0_cd: sdio0-cd {
1213 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1214 };
1215
1216 sdio0_wp: sdio0-wp {
1217 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1218 };
1219
1220 sdio0_pwr: sdio0-pwr {
1221 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1222 };
1223
1224 sdio0_bkpwr: sdio0-bkpwr {
1225 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1226 };
1227
1228 sdio0_int: sdio0-int {
1229 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1230 };
1231 };
1232
1233 sdmmc {
1234 sdmmc_clk: sdmmc-clk {
1235 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1236 };
1237
1238 sdmmc_cmd: sdmmc-cmd {
1239 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1240 };
1241
1242 sdmmc_cd: sdmmc-cd {
1243 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1244 };
1245
1246 sdmmc_bus1: sdmmc-bus1 {
1247 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1248 };
1249
1250 sdmmc_bus4: sdmmc-bus4 {
1251 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1252 <2 RK_PA6 1 &pcfg_pull_up>,
1253 <2 RK_PA7 1 &pcfg_pull_up>,
1254 <2 RK_PB0 1 &pcfg_pull_up>;
1255 };
1256 };
1257
1258 spdif {
1259 spdif_tx: spdif-tx {
1260 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1261 };
1262 };
1263
1264 spi0 {
1265 spi0_clk: spi0-clk {
1266 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1267 };
1268 spi0_cs0: spi0-cs0 {
1269 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1270 };
1271 spi0_cs1: spi0-cs1 {
1272 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1273 };
1274 spi0_tx: spi0-tx {
1275 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1276 };
1277 spi0_rx: spi0-rx {
1278 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1279 };
1280 };
1281
1282 spi1 {
1283 spi1_clk: spi1-clk {
1284 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1285 };
1286 spi1_cs0: spi1-cs0 {
1287 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1288 };
1289 spi1_cs1: spi1-cs1 {
1290 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1291 };
1292 spi1_rx: spi1-rx {
1293 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1294 };
1295 spi1_tx: spi1-tx {
1296 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1297 };
1298 };
1299
1300 spi2 {
1301 spi2_clk: spi2-clk {
1302 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1303 };
1304 spi2_cs0: spi2-cs0 {
1305 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1306 };
1307 spi2_rx: spi2-rx {
1308 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1309 };
1310 spi2_tx: spi2-tx {
1311 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1312 };
1313 };
1314
1315 tsadc {
1316 otp_pin: otp-pin {
1317 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1318 };
1319
1320 otp_out: otp-out {
1321 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1322 };
1323 };
1324
1325 uart0 {
1326 uart0_xfer: uart0-xfer {
1327 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1328 <2 RK_PD1 1 &pcfg_pull_none>;
1329 };
1330
1331 uart0_cts: uart0-cts {
1332 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1333 };
1334
1335 uart0_rts: uart0-rts {
1336 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1337 };
1338 };
1339
1340 uart1 {
1341 uart1_xfer: uart1-xfer {
1342 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1343 <0 RK_PC5 3 &pcfg_pull_none>;
1344 };
1345
1346 uart1_cts: uart1-cts {
1347 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1348 };
1349
1350 uart1_rts: uart1-rts {
1351 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1352 };
1353 };
1354
1355 uart2 {
1356 uart2_xfer: uart2-xfer {
1357 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1358 <2 RK_PA5 2 &pcfg_pull_none>;
1359 };
1360 /* no rts / cts for uart2 */
1361 };
1362
1363 uart3 {
1364 uart3_xfer: uart3-xfer {
1365 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1366 <3 RK_PD6 3 &pcfg_pull_none>;
1367 };
1368
1369 uart3_cts: uart3-cts {
1370 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1371 };
1372
1373 uart3_rts: uart3-rts {
1374 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1375 };
1376 };
1377
1378 uart4 {
1379 uart4_xfer: uart4-xfer {
1380 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1381 <0 RK_PD2 3 &pcfg_pull_none>;
1382 };
1383
1384 uart4_cts: uart4-cts {
1385 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1386 };
1387
1388 uart4_rts: uart4-rts {
1389 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1390 };
1391 };
1392 };
1393 };
