0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
0004 */
0005
0006 #include <dt-bindings/clock/rk3328-cru.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/pinctrl/rockchip.h>
0011 #include <dt-bindings/power/rk3328-power.h>
0012 #include <dt-bindings/soc/rockchip,boot-mode.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 compatible = "rockchip,rk3328";
0017
0018 interrupt-parent = <&gic>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 aliases {
0023 serial0 = &uart0;
0024 serial1 = &uart1;
0025 serial2 = &uart2;
0026 i2c0 = &i2c0;
0027 i2c1 = &i2c1;
0028 i2c2 = &i2c2;
0029 i2c3 = &i2c3;
0030 ethernet0 = &gmac2io;
0031 ethernet1 = &gmac2phy;
0032 };
0033
0034 cpus {
0035 #address-cells = <2>;
0036 #size-cells = <0>;
0037
0038 cpu0: cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a53";
0041 reg = <0x0 0x0>;
0042 clocks = <&cru ARMCLK>;
0043 #cooling-cells = <2>;
0044 cpu-idle-states = <&CPU_SLEEP>;
0045 dynamic-power-coefficient = <120>;
0046 enable-method = "psci";
0047 next-level-cache = <&l2>;
0048 operating-points-v2 = <&cpu0_opp_table>;
0049 };
0050
0051 cpu1: cpu@1 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a53";
0054 reg = <0x0 0x1>;
0055 clocks = <&cru ARMCLK>;
0056 #cooling-cells = <2>;
0057 cpu-idle-states = <&CPU_SLEEP>;
0058 dynamic-power-coefficient = <120>;
0059 enable-method = "psci";
0060 next-level-cache = <&l2>;
0061 operating-points-v2 = <&cpu0_opp_table>;
0062 };
0063
0064 cpu2: cpu@2 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a53";
0067 reg = <0x0 0x2>;
0068 clocks = <&cru ARMCLK>;
0069 #cooling-cells = <2>;
0070 cpu-idle-states = <&CPU_SLEEP>;
0071 dynamic-power-coefficient = <120>;
0072 enable-method = "psci";
0073 next-level-cache = <&l2>;
0074 operating-points-v2 = <&cpu0_opp_table>;
0075 };
0076
0077 cpu3: cpu@3 {
0078 device_type = "cpu";
0079 compatible = "arm,cortex-a53";
0080 reg = <0x0 0x3>;
0081 clocks = <&cru ARMCLK>;
0082 #cooling-cells = <2>;
0083 cpu-idle-states = <&CPU_SLEEP>;
0084 dynamic-power-coefficient = <120>;
0085 enable-method = "psci";
0086 next-level-cache = <&l2>;
0087 operating-points-v2 = <&cpu0_opp_table>;
0088 };
0089
0090 idle-states {
0091 entry-method = "psci";
0092
0093 CPU_SLEEP: cpu-sleep {
0094 compatible = "arm,idle-state";
0095 local-timer-stop;
0096 arm,psci-suspend-param = <0x0010000>;
0097 entry-latency-us = <120>;
0098 exit-latency-us = <250>;
0099 min-residency-us = <900>;
0100 };
0101 };
0102
0103 l2: l2-cache0 {
0104 compatible = "cache";
0105 };
0106 };
0107
0108 cpu0_opp_table: opp-table-0 {
0109 compatible = "operating-points-v2";
0110 opp-shared;
0111
0112 opp-408000000 {
0113 opp-hz = /bits/ 64 <408000000>;
0114 opp-microvolt = <950000>;
0115 clock-latency-ns = <40000>;
0116 opp-suspend;
0117 };
0118 opp-600000000 {
0119 opp-hz = /bits/ 64 <600000000>;
0120 opp-microvolt = <950000>;
0121 clock-latency-ns = <40000>;
0122 };
0123 opp-816000000 {
0124 opp-hz = /bits/ 64 <816000000>;
0125 opp-microvolt = <1000000>;
0126 clock-latency-ns = <40000>;
0127 };
0128 opp-1008000000 {
0129 opp-hz = /bits/ 64 <1008000000>;
0130 opp-microvolt = <1100000>;
0131 clock-latency-ns = <40000>;
0132 };
0133 opp-1200000000 {
0134 opp-hz = /bits/ 64 <1200000000>;
0135 opp-microvolt = <1225000>;
0136 clock-latency-ns = <40000>;
0137 };
0138 opp-1296000000 {
0139 opp-hz = /bits/ 64 <1296000000>;
0140 opp-microvolt = <1300000>;
0141 clock-latency-ns = <40000>;
0142 };
0143 };
0144
0145 analog_sound: analog-sound {
0146 compatible = "simple-audio-card";
0147 simple-audio-card,format = "i2s";
0148 simple-audio-card,mclk-fs = <256>;
0149 simple-audio-card,name = "Analog";
0150 status = "disabled";
0151
0152 simple-audio-card,cpu {
0153 sound-dai = <&i2s1>;
0154 };
0155
0156 simple-audio-card,codec {
0157 sound-dai = <&codec>;
0158 };
0159 };
0160
0161 arm-pmu {
0162 compatible = "arm,cortex-a53-pmu";
0163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0168 };
0169
0170 display_subsystem: display-subsystem {
0171 compatible = "rockchip,display-subsystem";
0172 ports = <&vop_out>;
0173 };
0174
0175 hdmi_sound: hdmi-sound {
0176 compatible = "simple-audio-card";
0177 simple-audio-card,format = "i2s";
0178 simple-audio-card,mclk-fs = <128>;
0179 simple-audio-card,name = "HDMI";
0180 status = "disabled";
0181
0182 simple-audio-card,cpu {
0183 sound-dai = <&i2s0>;
0184 };
0185
0186 simple-audio-card,codec {
0187 sound-dai = <&hdmi>;
0188 };
0189 };
0190
0191 psci {
0192 compatible = "arm,psci-1.0", "arm,psci-0.2";
0193 method = "smc";
0194 };
0195
0196 timer {
0197 compatible = "arm,armv8-timer";
0198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0202 };
0203
0204 xin24m: xin24m {
0205 compatible = "fixed-clock";
0206 #clock-cells = <0>;
0207 clock-frequency = <24000000>;
0208 clock-output-names = "xin24m";
0209 };
0210
0211 i2s0: i2s@ff000000 {
0212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
0213 reg = <0x0 0xff000000 0x0 0x1000>;
0214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
0216 clock-names = "i2s_clk", "i2s_hclk";
0217 dmas = <&dmac 11>, <&dmac 12>;
0218 dma-names = "tx", "rx";
0219 #sound-dai-cells = <0>;
0220 status = "disabled";
0221 };
0222
0223 i2s1: i2s@ff010000 {
0224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
0225 reg = <0x0 0xff010000 0x0 0x1000>;
0226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
0228 clock-names = "i2s_clk", "i2s_hclk";
0229 dmas = <&dmac 14>, <&dmac 15>;
0230 dma-names = "tx", "rx";
0231 #sound-dai-cells = <0>;
0232 status = "disabled";
0233 };
0234
0235 i2s2: i2s@ff020000 {
0236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
0237 reg = <0x0 0xff020000 0x0 0x1000>;
0238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
0240 clock-names = "i2s_clk", "i2s_hclk";
0241 dmas = <&dmac 0>, <&dmac 1>;
0242 dma-names = "tx", "rx";
0243 #sound-dai-cells = <0>;
0244 status = "disabled";
0245 };
0246
0247 spdif: spdif@ff030000 {
0248 compatible = "rockchip,rk3328-spdif";
0249 reg = <0x0 0xff030000 0x0 0x1000>;
0250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
0252 clock-names = "mclk", "hclk";
0253 dmas = <&dmac 10>;
0254 dma-names = "tx";
0255 pinctrl-names = "default";
0256 pinctrl-0 = <&spdifm2_tx>;
0257 #sound-dai-cells = <0>;
0258 status = "disabled";
0259 };
0260
0261 pdm: pdm@ff040000 {
0262 compatible = "rockchip,pdm";
0263 reg = <0x0 0xff040000 0x0 0x1000>;
0264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
0265 clock-names = "pdm_clk", "pdm_hclk";
0266 dmas = <&dmac 16>;
0267 dma-names = "rx";
0268 pinctrl-names = "default", "sleep";
0269 pinctrl-0 = <&pdmm0_clk
0270 &pdmm0_sdi0
0271 &pdmm0_sdi1
0272 &pdmm0_sdi2
0273 &pdmm0_sdi3>;
0274 pinctrl-1 = <&pdmm0_clk_sleep
0275 &pdmm0_sdi0_sleep
0276 &pdmm0_sdi1_sleep
0277 &pdmm0_sdi2_sleep
0278 &pdmm0_sdi3_sleep>;
0279 status = "disabled";
0280 };
0281
0282 grf: syscon@ff100000 {
0283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
0284 reg = <0x0 0xff100000 0x0 0x1000>;
0285
0286 io_domains: io-domains {
0287 compatible = "rockchip,rk3328-io-voltage-domain";
0288 status = "disabled";
0289 };
0290
0291 grf_gpio: gpio {
0292 compatible = "rockchip,rk3328-grf-gpio";
0293 gpio-controller;
0294 #gpio-cells = <2>;
0295 };
0296
0297 power: power-controller {
0298 compatible = "rockchip,rk3328-power-controller";
0299 #power-domain-cells = <1>;
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302
0303 power-domain@RK3328_PD_HEVC {
0304 reg = <RK3328_PD_HEVC>;
0305 #power-domain-cells = <0>;
0306 };
0307 power-domain@RK3328_PD_VIDEO {
0308 reg = <RK3328_PD_VIDEO>;
0309 clocks = <&cru ACLK_RKVDEC>,
0310 <&cru HCLK_RKVDEC>,
0311 <&cru SCLK_VDEC_CABAC>,
0312 <&cru SCLK_VDEC_CORE>;
0313 #power-domain-cells = <0>;
0314 };
0315 power-domain@RK3328_PD_VPU {
0316 reg = <RK3328_PD_VPU>;
0317 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0318 #power-domain-cells = <0>;
0319 };
0320 };
0321
0322 reboot-mode {
0323 compatible = "syscon-reboot-mode";
0324 offset = <0x5c8>;
0325 mode-normal = <BOOT_NORMAL>;
0326 mode-recovery = <BOOT_RECOVERY>;
0327 mode-bootloader = <BOOT_FASTBOOT>;
0328 mode-loader = <BOOT_BL_DOWNLOAD>;
0329 };
0330 };
0331
0332 uart0: serial@ff110000 {
0333 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
0334 reg = <0x0 0xff110000 0x0 0x100>;
0335 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0336 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0337 clock-names = "baudclk", "apb_pclk";
0338 dmas = <&dmac 2>, <&dmac 3>;
0339 dma-names = "tx", "rx";
0340 pinctrl-names = "default";
0341 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0342 reg-io-width = <4>;
0343 reg-shift = <2>;
0344 status = "disabled";
0345 };
0346
0347 uart1: serial@ff120000 {
0348 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
0349 reg = <0x0 0xff120000 0x0 0x100>;
0350 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0351 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0352 clock-names = "baudclk", "apb_pclk";
0353 dmas = <&dmac 4>, <&dmac 5>;
0354 dma-names = "tx", "rx";
0355 pinctrl-names = "default";
0356 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
0357 reg-io-width = <4>;
0358 reg-shift = <2>;
0359 status = "disabled";
0360 };
0361
0362 uart2: serial@ff130000 {
0363 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
0364 reg = <0x0 0xff130000 0x0 0x100>;
0365 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0366 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0367 clock-names = "baudclk", "apb_pclk";
0368 dmas = <&dmac 6>, <&dmac 7>;
0369 dma-names = "tx", "rx";
0370 pinctrl-names = "default";
0371 pinctrl-0 = <&uart2m1_xfer>;
0372 reg-io-width = <4>;
0373 reg-shift = <2>;
0374 status = "disabled";
0375 };
0376
0377 i2c0: i2c@ff150000 {
0378 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
0379 reg = <0x0 0xff150000 0x0 0x1000>;
0380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0381 #address-cells = <1>;
0382 #size-cells = <0>;
0383 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
0384 clock-names = "i2c", "pclk";
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&i2c0_xfer>;
0387 status = "disabled";
0388 };
0389
0390 i2c1: i2c@ff160000 {
0391 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
0392 reg = <0x0 0xff160000 0x0 0x1000>;
0393 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0394 #address-cells = <1>;
0395 #size-cells = <0>;
0396 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
0397 clock-names = "i2c", "pclk";
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&i2c1_xfer>;
0400 status = "disabled";
0401 };
0402
0403 i2c2: i2c@ff170000 {
0404 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
0405 reg = <0x0 0xff170000 0x0 0x1000>;
0406 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
0410 clock-names = "i2c", "pclk";
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&i2c2_xfer>;
0413 status = "disabled";
0414 };
0415
0416 i2c3: i2c@ff180000 {
0417 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
0418 reg = <0x0 0xff180000 0x0 0x1000>;
0419 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
0423 clock-names = "i2c", "pclk";
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&i2c3_xfer>;
0426 status = "disabled";
0427 };
0428
0429 spi0: spi@ff190000 {
0430 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
0431 reg = <0x0 0xff190000 0x0 0x1000>;
0432 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0433 #address-cells = <1>;
0434 #size-cells = <0>;
0435 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
0436 clock-names = "spiclk", "apb_pclk";
0437 dmas = <&dmac 8>, <&dmac 9>;
0438 dma-names = "tx", "rx";
0439 pinctrl-names = "default";
0440 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
0441 status = "disabled";
0442 };
0443
0444 wdt: watchdog@ff1a0000 {
0445 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
0446 reg = <0x0 0xff1a0000 0x0 0x100>;
0447 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0448 clocks = <&cru PCLK_WDT>;
0449 };
0450
0451 pwm0: pwm@ff1b0000 {
0452 compatible = "rockchip,rk3328-pwm";
0453 reg = <0x0 0xff1b0000 0x0 0x10>;
0454 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0455 clock-names = "pwm", "pclk";
0456 pinctrl-names = "default";
0457 pinctrl-0 = <&pwm0_pin>;
0458 #pwm-cells = <3>;
0459 status = "disabled";
0460 };
0461
0462 pwm1: pwm@ff1b0010 {
0463 compatible = "rockchip,rk3328-pwm";
0464 reg = <0x0 0xff1b0010 0x0 0x10>;
0465 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0466 clock-names = "pwm", "pclk";
0467 pinctrl-names = "default";
0468 pinctrl-0 = <&pwm1_pin>;
0469 #pwm-cells = <3>;
0470 status = "disabled";
0471 };
0472
0473 pwm2: pwm@ff1b0020 {
0474 compatible = "rockchip,rk3328-pwm";
0475 reg = <0x0 0xff1b0020 0x0 0x10>;
0476 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0477 clock-names = "pwm", "pclk";
0478 pinctrl-names = "default";
0479 pinctrl-0 = <&pwm2_pin>;
0480 #pwm-cells = <3>;
0481 status = "disabled";
0482 };
0483
0484 pwm3: pwm@ff1b0030 {
0485 compatible = "rockchip,rk3328-pwm";
0486 reg = <0x0 0xff1b0030 0x0 0x10>;
0487 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0488 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0489 clock-names = "pwm", "pclk";
0490 pinctrl-names = "default";
0491 pinctrl-0 = <&pwmir_pin>;
0492 #pwm-cells = <3>;
0493 status = "disabled";
0494 };
0495
0496 dmac: dma-controller@ff1f0000 {
0497 compatible = "arm,pl330", "arm,primecell";
0498 reg = <0x0 0xff1f0000 0x0 0x4000>;
0499 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0500 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0501 arm,pl330-periph-burst;
0502 clocks = <&cru ACLK_DMAC>;
0503 clock-names = "apb_pclk";
0504 #dma-cells = <1>;
0505 };
0506
0507 thermal-zones {
0508 soc_thermal: soc-thermal {
0509 polling-delay-passive = <20>;
0510 polling-delay = <1000>;
0511 sustainable-power = <1000>;
0512
0513 thermal-sensors = <&tsadc 0>;
0514
0515 trips {
0516 threshold: trip-point0 {
0517 temperature = <70000>;
0518 hysteresis = <2000>;
0519 type = "passive";
0520 };
0521 target: trip-point1 {
0522 temperature = <85000>;
0523 hysteresis = <2000>;
0524 type = "passive";
0525 };
0526 soc_crit: soc-crit {
0527 temperature = <95000>;
0528 hysteresis = <2000>;
0529 type = "critical";
0530 };
0531 };
0532
0533 cooling-maps {
0534 map0 {
0535 trip = <&target>;
0536 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0537 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0538 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0539 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0540 contribution = <4096>;
0541 };
0542 };
0543 };
0544
0545 };
0546
0547 tsadc: tsadc@ff250000 {
0548 compatible = "rockchip,rk3328-tsadc";
0549 reg = <0x0 0xff250000 0x0 0x100>;
0550 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0551 assigned-clocks = <&cru SCLK_TSADC>;
0552 assigned-clock-rates = <50000>;
0553 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0554 clock-names = "tsadc", "apb_pclk";
0555 pinctrl-names = "init", "default", "sleep";
0556 pinctrl-0 = <&otp_pin>;
0557 pinctrl-1 = <&otp_out>;
0558 pinctrl-2 = <&otp_pin>;
0559 resets = <&cru SRST_TSADC>;
0560 reset-names = "tsadc-apb";
0561 rockchip,grf = <&grf>;
0562 rockchip,hw-tshut-temp = <100000>;
0563 #thermal-sensor-cells = <1>;
0564 status = "disabled";
0565 };
0566
0567 efuse: efuse@ff260000 {
0568 compatible = "rockchip,rk3328-efuse";
0569 reg = <0x0 0xff260000 0x0 0x50>;
0570 #address-cells = <1>;
0571 #size-cells = <1>;
0572 clocks = <&cru SCLK_EFUSE>;
0573 clock-names = "pclk_efuse";
0574 rockchip,efuse-size = <0x20>;
0575
0576 /* Data cells */
0577 efuse_id: id@7 {
0578 reg = <0x07 0x10>;
0579 };
0580 cpu_leakage: cpu-leakage@17 {
0581 reg = <0x17 0x1>;
0582 };
0583 logic_leakage: logic-leakage@19 {
0584 reg = <0x19 0x1>;
0585 };
0586 efuse_cpu_version: cpu-version@1a {
0587 reg = <0x1a 0x1>;
0588 bits = <3 3>;
0589 };
0590 };
0591
0592 saradc: adc@ff280000 {
0593 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
0594 reg = <0x0 0xff280000 0x0 0x100>;
0595 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0596 #io-channel-cells = <1>;
0597 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
0598 clock-names = "saradc", "apb_pclk";
0599 resets = <&cru SRST_SARADC_P>;
0600 reset-names = "saradc-apb";
0601 status = "disabled";
0602 };
0603
0604 gpu: gpu@ff300000 {
0605 compatible = "rockchip,rk3328-mali", "arm,mali-450";
0606 reg = <0x0 0xff300000 0x0 0x30000>;
0607 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0608 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0609 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
0610 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0611 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0612 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0613 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0614 interrupt-names = "gp",
0615 "gpmmu",
0616 "pp",
0617 "pp0",
0618 "ppmmu0",
0619 "pp1",
0620 "ppmmu1";
0621 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
0622 clock-names = "bus", "core";
0623 resets = <&cru SRST_GPU_A>;
0624 };
0625
0626 h265e_mmu: iommu@ff330200 {
0627 compatible = "rockchip,iommu";
0628 reg = <0x0 0xff330200 0 0x100>;
0629 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0630 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
0631 clock-names = "aclk", "iface";
0632 #iommu-cells = <0>;
0633 status = "disabled";
0634 };
0635
0636 vepu_mmu: iommu@ff340800 {
0637 compatible = "rockchip,iommu";
0638 reg = <0x0 0xff340800 0x0 0x40>;
0639 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0640 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0641 clock-names = "aclk", "iface";
0642 #iommu-cells = <0>;
0643 status = "disabled";
0644 };
0645
0646 vpu: video-codec@ff350000 {
0647 compatible = "rockchip,rk3328-vpu";
0648 reg = <0x0 0xff350000 0x0 0x800>;
0649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0650 interrupt-names = "vdpu";
0651 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0652 clock-names = "aclk", "hclk";
0653 iommus = <&vpu_mmu>;
0654 power-domains = <&power RK3328_PD_VPU>;
0655 };
0656
0657 vpu_mmu: iommu@ff350800 {
0658 compatible = "rockchip,iommu";
0659 reg = <0x0 0xff350800 0x0 0x40>;
0660 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0661 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0662 clock-names = "aclk", "iface";
0663 #iommu-cells = <0>;
0664 power-domains = <&power RK3328_PD_VPU>;
0665 };
0666
0667 vdec: video-codec@ff360000 {
0668 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
0669 reg = <0x0 0xff360000 0x0 0x400>;
0670 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0671 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
0672 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
0673 clock-names = "axi", "ahb", "cabac", "core";
0674 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
0675 <&cru SCLK_VDEC_CORE>;
0676 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
0677 iommus = <&vdec_mmu>;
0678 power-domains = <&power RK3328_PD_VIDEO>;
0679 };
0680
0681 vdec_mmu: iommu@ff360480 {
0682 compatible = "rockchip,iommu";
0683 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
0684 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0685 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
0686 clock-names = "aclk", "iface";
0687 #iommu-cells = <0>;
0688 power-domains = <&power RK3328_PD_VIDEO>;
0689 };
0690
0691 vop: vop@ff370000 {
0692 compatible = "rockchip,rk3328-vop";
0693 reg = <0x0 0xff370000 0x0 0x3efc>;
0694 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0695 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
0696 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0697 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
0698 reset-names = "axi", "ahb", "dclk";
0699 iommus = <&vop_mmu>;
0700 status = "disabled";
0701
0702 vop_out: port {
0703 #address-cells = <1>;
0704 #size-cells = <0>;
0705
0706 vop_out_hdmi: endpoint@0 {
0707 reg = <0>;
0708 remote-endpoint = <&hdmi_in_vop>;
0709 };
0710 };
0711 };
0712
0713 vop_mmu: iommu@ff373f00 {
0714 compatible = "rockchip,iommu";
0715 reg = <0x0 0xff373f00 0x0 0x100>;
0716 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0717 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
0718 clock-names = "aclk", "iface";
0719 #iommu-cells = <0>;
0720 status = "disabled";
0721 };
0722
0723 hdmi: hdmi@ff3c0000 {
0724 compatible = "rockchip,rk3328-dw-hdmi";
0725 reg = <0x0 0xff3c0000 0x0 0x20000>;
0726 reg-io-width = <4>;
0727 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0728 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0729 clocks = <&cru PCLK_HDMI>,
0730 <&cru SCLK_HDMI_SFC>,
0731 <&cru SCLK_RTC32K>;
0732 clock-names = "iahb",
0733 "isfr",
0734 "cec";
0735 phys = <&hdmiphy>;
0736 phy-names = "hdmi";
0737 pinctrl-names = "default";
0738 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
0739 rockchip,grf = <&grf>;
0740 #sound-dai-cells = <0>;
0741 status = "disabled";
0742
0743 ports {
0744 hdmi_in: port {
0745 hdmi_in_vop: endpoint {
0746 remote-endpoint = <&vop_out_hdmi>;
0747 };
0748 };
0749 };
0750 };
0751
0752 codec: codec@ff410000 {
0753 compatible = "rockchip,rk3328-codec";
0754 reg = <0x0 0xff410000 0x0 0x1000>;
0755 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
0756 clock-names = "pclk", "mclk";
0757 rockchip,grf = <&grf>;
0758 #sound-dai-cells = <0>;
0759 status = "disabled";
0760 };
0761
0762 hdmiphy: phy@ff430000 {
0763 compatible = "rockchip,rk3328-hdmi-phy";
0764 reg = <0x0 0xff430000 0x0 0x10000>;
0765 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0766 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
0767 clock-names = "sysclk", "refoclk", "refpclk";
0768 clock-output-names = "hdmi_phy";
0769 #clock-cells = <0>;
0770 nvmem-cells = <&efuse_cpu_version>;
0771 nvmem-cell-names = "cpu-version";
0772 #phy-cells = <0>;
0773 status = "disabled";
0774 };
0775
0776 cru: clock-controller@ff440000 {
0777 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
0778 reg = <0x0 0xff440000 0x0 0x1000>;
0779 rockchip,grf = <&grf>;
0780 #clock-cells = <1>;
0781 #reset-cells = <1>;
0782 assigned-clocks =
0783 /*
0784 * CPLL should run at 1200, but that is to high for
0785 * the initial dividers of most of its children.
0786 * We need set cpll child clk div first,
0787 * and then set the cpll frequency.
0788 */
0789 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
0790 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
0791 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
0792 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
0793 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
0794 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
0795 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
0796 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
0797 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
0798 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
0799 <&cru SCLK_WIFI>, <&cru ARMCLK>,
0800 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
0801 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
0802 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
0803 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
0804 <&cru SCLK_RTC32K>;
0805 assigned-clock-parents =
0806 <&cru HDMIPHY>, <&cru PLL_APLL>,
0807 <&cru PLL_GPLL>, <&xin24m>,
0808 <&xin24m>, <&xin24m>;
0809 assigned-clock-rates =
0810 <0>, <61440000>,
0811 <0>, <24000000>,
0812 <24000000>, <24000000>,
0813 <15000000>, <15000000>,
0814 <100000000>, <100000000>,
0815 <100000000>, <100000000>,
0816 <50000000>, <100000000>,
0817 <100000000>, <100000000>,
0818 <50000000>, <50000000>,
0819 <50000000>, <50000000>,
0820 <24000000>, <600000000>,
0821 <491520000>, <1200000000>,
0822 <150000000>, <75000000>,
0823 <75000000>, <150000000>,
0824 <75000000>, <75000000>,
0825 <32768>;
0826 };
0827
0828 usb2phy_grf: syscon@ff450000 {
0829 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
0830 "simple-mfd";
0831 reg = <0x0 0xff450000 0x0 0x10000>;
0832 #address-cells = <1>;
0833 #size-cells = <1>;
0834
0835 u2phy: usb2phy@100 {
0836 compatible = "rockchip,rk3328-usb2phy";
0837 reg = <0x100 0x10>;
0838 clocks = <&xin24m>;
0839 clock-names = "phyclk";
0840 clock-output-names = "usb480m_phy";
0841 #clock-cells = <0>;
0842 assigned-clocks = <&cru USB480M>;
0843 assigned-clock-parents = <&u2phy>;
0844 status = "disabled";
0845
0846 u2phy_otg: otg-port {
0847 #phy-cells = <0>;
0848 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0849 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0850 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0851 interrupt-names = "otg-bvalid", "otg-id",
0852 "linestate";
0853 status = "disabled";
0854 };
0855
0856 u2phy_host: host-port {
0857 #phy-cells = <0>;
0858 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0859 interrupt-names = "linestate";
0860 status = "disabled";
0861 };
0862 };
0863 };
0864
0865 sdmmc: mmc@ff500000 {
0866 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
0867 reg = <0x0 0xff500000 0x0 0x4000>;
0868 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0869 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
0870 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
0871 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0872 fifo-depth = <0x100>;
0873 max-frequency = <150000000>;
0874 status = "disabled";
0875 };
0876
0877 sdio: mmc@ff510000 {
0878 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
0879 reg = <0x0 0xff510000 0x0 0x4000>;
0880 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0881 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
0882 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
0883 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0884 fifo-depth = <0x100>;
0885 max-frequency = <150000000>;
0886 status = "disabled";
0887 };
0888
0889 emmc: mmc@ff520000 {
0890 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
0891 reg = <0x0 0xff520000 0x0 0x4000>;
0892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0893 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0894 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0895 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0896 fifo-depth = <0x100>;
0897 max-frequency = <150000000>;
0898 status = "disabled";
0899 };
0900
0901 gmac2io: ethernet@ff540000 {
0902 compatible = "rockchip,rk3328-gmac";
0903 reg = <0x0 0xff540000 0x0 0x10000>;
0904 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0905 interrupt-names = "macirq";
0906 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
0907 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
0908 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
0909 <&cru PCLK_MAC2IO>;
0910 clock-names = "stmmaceth", "mac_clk_rx",
0911 "mac_clk_tx", "clk_mac_ref",
0912 "clk_mac_refout", "aclk_mac",
0913 "pclk_mac";
0914 resets = <&cru SRST_GMAC2IO_A>;
0915 reset-names = "stmmaceth";
0916 rockchip,grf = <&grf>;
0917 snps,txpbl = <0x4>;
0918 status = "disabled";
0919 };
0920
0921 gmac2phy: ethernet@ff550000 {
0922 compatible = "rockchip,rk3328-gmac";
0923 reg = <0x0 0xff550000 0x0 0x10000>;
0924 rockchip,grf = <&grf>;
0925 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0926 interrupt-names = "macirq";
0927 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
0928 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
0929 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
0930 <&cru SCLK_MAC2PHY_OUT>;
0931 clock-names = "stmmaceth", "mac_clk_rx",
0932 "mac_clk_tx", "clk_mac_ref",
0933 "aclk_mac", "pclk_mac",
0934 "clk_macphy";
0935 resets = <&cru SRST_GMAC2PHY_A>;
0936 reset-names = "stmmaceth";
0937 phy-mode = "rmii";
0938 phy-handle = <&phy>;
0939 snps,txpbl = <0x4>;
0940 clock_in_out = "output";
0941 status = "disabled";
0942
0943 mdio {
0944 compatible = "snps,dwmac-mdio";
0945 #address-cells = <1>;
0946 #size-cells = <0>;
0947
0948 phy: ethernet-phy@0 {
0949 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
0950 reg = <0>;
0951 clocks = <&cru SCLK_MAC2PHY_OUT>;
0952 resets = <&cru SRST_MACPHY>;
0953 pinctrl-names = "default";
0954 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
0955 phy-is-integrated;
0956 };
0957 };
0958 };
0959
0960 usb20_otg: usb@ff580000 {
0961 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
0962 "snps,dwc2";
0963 reg = <0x0 0xff580000 0x0 0x40000>;
0964 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0965 clocks = <&cru HCLK_OTG>;
0966 clock-names = "otg";
0967 dr_mode = "otg";
0968 g-np-tx-fifo-size = <16>;
0969 g-rx-fifo-size = <280>;
0970 g-tx-fifo-size = <256 128 128 64 32 16>;
0971 phys = <&u2phy_otg>;
0972 phy-names = "usb2-phy";
0973 status = "disabled";
0974 };
0975
0976 usb_host0_ehci: usb@ff5c0000 {
0977 compatible = "generic-ehci";
0978 reg = <0x0 0xff5c0000 0x0 0x10000>;
0979 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0980 clocks = <&cru HCLK_HOST0>, <&u2phy>;
0981 phys = <&u2phy_host>;
0982 phy-names = "usb";
0983 status = "disabled";
0984 };
0985
0986 usb_host0_ohci: usb@ff5d0000 {
0987 compatible = "generic-ohci";
0988 reg = <0x0 0xff5d0000 0x0 0x10000>;
0989 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0990 clocks = <&cru HCLK_HOST0>, <&u2phy>;
0991 phys = <&u2phy_host>;
0992 phy-names = "usb";
0993 status = "disabled";
0994 };
0995
0996 usbdrd3: usb@ff600000 {
0997 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
0998 reg = <0x0 0xff600000 0x0 0x100000>;
0999 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1001 <&cru ACLK_USB3OTG>;
1002 clock-names = "ref_clk", "suspend_clk",
1003 "bus_clk";
1004 dr_mode = "otg";
1005 phy_type = "utmi_wide";
1006 snps,dis-del-phy-power-chg-quirk;
1007 snps,dis_enblslpm_quirk;
1008 snps,dis-tx-ipgap-linecheck-quirk;
1009 snps,dis-u2-freeclk-exists-quirk;
1010 snps,dis_u2_susphy_quirk;
1011 snps,dis_u3_susphy_quirk;
1012 status = "disabled";
1013 };
1014
1015 gic: interrupt-controller@ff811000 {
1016 compatible = "arm,gic-400";
1017 #interrupt-cells = <3>;
1018 #address-cells = <0>;
1019 interrupt-controller;
1020 reg = <0x0 0xff811000 0 0x1000>,
1021 <0x0 0xff812000 0 0x2000>,
1022 <0x0 0xff814000 0 0x2000>,
1023 <0x0 0xff816000 0 0x2000>;
1024 interrupts = <GIC_PPI 9
1025 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1026 };
1027
1028 pinctrl: pinctrl {
1029 compatible = "rockchip,rk3328-pinctrl";
1030 rockchip,grf = <&grf>;
1031 #address-cells = <2>;
1032 #size-cells = <2>;
1033 ranges;
1034
1035 gpio0: gpio@ff210000 {
1036 compatible = "rockchip,gpio-bank";
1037 reg = <0x0 0xff210000 0x0 0x100>;
1038 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&cru PCLK_GPIO0>;
1040
1041 gpio-controller;
1042 #gpio-cells = <2>;
1043
1044 interrupt-controller;
1045 #interrupt-cells = <2>;
1046 };
1047
1048 gpio1: gpio@ff220000 {
1049 compatible = "rockchip,gpio-bank";
1050 reg = <0x0 0xff220000 0x0 0x100>;
1051 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&cru PCLK_GPIO1>;
1053
1054 gpio-controller;
1055 #gpio-cells = <2>;
1056
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1059 };
1060
1061 gpio2: gpio@ff230000 {
1062 compatible = "rockchip,gpio-bank";
1063 reg = <0x0 0xff230000 0x0 0x100>;
1064 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cru PCLK_GPIO2>;
1066
1067 gpio-controller;
1068 #gpio-cells = <2>;
1069
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1072 };
1073
1074 gpio3: gpio@ff240000 {
1075 compatible = "rockchip,gpio-bank";
1076 reg = <0x0 0xff240000 0x0 0x100>;
1077 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&cru PCLK_GPIO3>;
1079
1080 gpio-controller;
1081 #gpio-cells = <2>;
1082
1083 interrupt-controller;
1084 #interrupt-cells = <2>;
1085 };
1086
1087 pcfg_pull_up: pcfg-pull-up {
1088 bias-pull-up;
1089 };
1090
1091 pcfg_pull_down: pcfg-pull-down {
1092 bias-pull-down;
1093 };
1094
1095 pcfg_pull_none: pcfg-pull-none {
1096 bias-disable;
1097 };
1098
1099 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1100 bias-disable;
1101 drive-strength = <2>;
1102 };
1103
1104 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1105 bias-pull-up;
1106 drive-strength = <2>;
1107 };
1108
1109 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1110 bias-pull-up;
1111 drive-strength = <4>;
1112 };
1113
1114 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1115 bias-disable;
1116 drive-strength = <4>;
1117 };
1118
1119 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1120 bias-pull-down;
1121 drive-strength = <4>;
1122 };
1123
1124 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1125 bias-disable;
1126 drive-strength = <8>;
1127 };
1128
1129 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1130 bias-pull-up;
1131 drive-strength = <8>;
1132 };
1133
1134 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1135 bias-disable;
1136 drive-strength = <12>;
1137 };
1138
1139 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1140 bias-pull-up;
1141 drive-strength = <12>;
1142 };
1143
1144 pcfg_output_high: pcfg-output-high {
1145 output-high;
1146 };
1147
1148 pcfg_output_low: pcfg-output-low {
1149 output-low;
1150 };
1151
1152 pcfg_input_high: pcfg-input-high {
1153 bias-pull-up;
1154 input-enable;
1155 };
1156
1157 pcfg_input: pcfg-input {
1158 input-enable;
1159 };
1160
1161 i2c0 {
1162 i2c0_xfer: i2c0-xfer {
1163 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1164 <2 RK_PD1 1 &pcfg_pull_none>;
1165 };
1166 };
1167
1168 i2c1 {
1169 i2c1_xfer: i2c1-xfer {
1170 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1171 <2 RK_PA5 2 &pcfg_pull_none>;
1172 };
1173 };
1174
1175 i2c2 {
1176 i2c2_xfer: i2c2-xfer {
1177 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1178 <2 RK_PB6 1 &pcfg_pull_none>;
1179 };
1180 };
1181
1182 i2c3 {
1183 i2c3_xfer: i2c3-xfer {
1184 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1185 <0 RK_PA6 2 &pcfg_pull_none>;
1186 };
1187 i2c3_pins: i2c3-pins {
1188 rockchip,pins =
1189 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1190 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1191 };
1192 };
1193
1194 hdmi_i2c {
1195 hdmii2c_xfer: hdmii2c-xfer {
1196 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1197 <0 RK_PA6 1 &pcfg_pull_none>;
1198 };
1199 };
1200
1201 pdm-0 {
1202 pdmm0_clk: pdmm0-clk {
1203 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1204 };
1205
1206 pdmm0_fsync: pdmm0-fsync {
1207 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1208 };
1209
1210 pdmm0_sdi0: pdmm0-sdi0 {
1211 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1212 };
1213
1214 pdmm0_sdi1: pdmm0-sdi1 {
1215 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1216 };
1217
1218 pdmm0_sdi2: pdmm0-sdi2 {
1219 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1220 };
1221
1222 pdmm0_sdi3: pdmm0-sdi3 {
1223 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1224 };
1225
1226 pdmm0_clk_sleep: pdmm0-clk-sleep {
1227 rockchip,pins =
1228 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1229 };
1230
1231 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1232 rockchip,pins =
1233 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1234 };
1235
1236 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1237 rockchip,pins =
1238 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1239 };
1240
1241 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1242 rockchip,pins =
1243 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1244 };
1245
1246 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1247 rockchip,pins =
1248 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1249 };
1250
1251 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1252 rockchip,pins =
1253 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1254 };
1255 };
1256
1257 tsadc {
1258 otp_pin: otp-pin {
1259 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1260 };
1261
1262 otp_out: otp-out {
1263 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1264 };
1265 };
1266
1267 uart0 {
1268 uart0_xfer: uart0-xfer {
1269 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1270 <1 RK_PB0 1 &pcfg_pull_up>;
1271 };
1272
1273 uart0_cts: uart0-cts {
1274 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1275 };
1276
1277 uart0_rts: uart0-rts {
1278 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1279 };
1280
1281 uart0_rts_pin: uart0-rts-pin {
1282 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1283 };
1284 };
1285
1286 uart1 {
1287 uart1_xfer: uart1-xfer {
1288 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1289 <3 RK_PA6 4 &pcfg_pull_up>;
1290 };
1291
1292 uart1_cts: uart1-cts {
1293 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1294 };
1295
1296 uart1_rts: uart1-rts {
1297 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1298 };
1299
1300 uart1_rts_pin: uart1-rts-pin {
1301 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1302 };
1303 };
1304
1305 uart2-0 {
1306 uart2m0_xfer: uart2m0-xfer {
1307 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1308 <1 RK_PA1 2 &pcfg_pull_up>;
1309 };
1310 };
1311
1312 uart2-1 {
1313 uart2m1_xfer: uart2m1-xfer {
1314 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1315 <2 RK_PA1 1 &pcfg_pull_up>;
1316 };
1317 };
1318
1319 spi0-0 {
1320 spi0m0_clk: spi0m0-clk {
1321 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1322 };
1323
1324 spi0m0_cs0: spi0m0-cs0 {
1325 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1326 };
1327
1328 spi0m0_tx: spi0m0-tx {
1329 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1330 };
1331
1332 spi0m0_rx: spi0m0-rx {
1333 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1334 };
1335
1336 spi0m0_cs1: spi0m0-cs1 {
1337 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1338 };
1339 };
1340
1341 spi0-1 {
1342 spi0m1_clk: spi0m1-clk {
1343 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1344 };
1345
1346 spi0m1_cs0: spi0m1-cs0 {
1347 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1348 };
1349
1350 spi0m1_tx: spi0m1-tx {
1351 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1352 };
1353
1354 spi0m1_rx: spi0m1-rx {
1355 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1356 };
1357
1358 spi0m1_cs1: spi0m1-cs1 {
1359 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1360 };
1361 };
1362
1363 spi0-2 {
1364 spi0m2_clk: spi0m2-clk {
1365 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1366 };
1367
1368 spi0m2_cs0: spi0m2-cs0 {
1369 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1370 };
1371
1372 spi0m2_tx: spi0m2-tx {
1373 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1374 };
1375
1376 spi0m2_rx: spi0m2-rx {
1377 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1378 };
1379 };
1380
1381 i2s1 {
1382 i2s1_mclk: i2s1-mclk {
1383 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1384 };
1385
1386 i2s1_sclk: i2s1-sclk {
1387 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1388 };
1389
1390 i2s1_lrckrx: i2s1-lrckrx {
1391 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1392 };
1393
1394 i2s1_lrcktx: i2s1-lrcktx {
1395 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1396 };
1397
1398 i2s1_sdi: i2s1-sdi {
1399 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1400 };
1401
1402 i2s1_sdo: i2s1-sdo {
1403 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1404 };
1405
1406 i2s1_sdio1: i2s1-sdio1 {
1407 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1408 };
1409
1410 i2s1_sdio2: i2s1-sdio2 {
1411 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1412 };
1413
1414 i2s1_sdio3: i2s1-sdio3 {
1415 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1416 };
1417
1418 i2s1_sleep: i2s1-sleep {
1419 rockchip,pins =
1420 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1421 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1422 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1423 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1424 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1425 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1426 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1427 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1428 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1429 };
1430 };
1431
1432 i2s2-0 {
1433 i2s2m0_mclk: i2s2m0-mclk {
1434 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1435 };
1436
1437 i2s2m0_sclk: i2s2m0-sclk {
1438 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1439 };
1440
1441 i2s2m0_lrckrx: i2s2m0-lrckrx {
1442 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1443 };
1444
1445 i2s2m0_lrcktx: i2s2m0-lrcktx {
1446 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1447 };
1448
1449 i2s2m0_sdi: i2s2m0-sdi {
1450 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1451 };
1452
1453 i2s2m0_sdo: i2s2m0-sdo {
1454 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1455 };
1456
1457 i2s2m0_sleep: i2s2m0-sleep {
1458 rockchip,pins =
1459 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1460 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1461 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1462 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1463 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1464 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1465 };
1466 };
1467
1468 i2s2-1 {
1469 i2s2m1_mclk: i2s2m1-mclk {
1470 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1471 };
1472
1473 i2s2m1_sclk: i2s2m1-sclk {
1474 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1475 };
1476
1477 i2s2m1_lrckrx: i2sm1-lrckrx {
1478 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1479 };
1480
1481 i2s2m1_lrcktx: i2s2m1-lrcktx {
1482 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1483 };
1484
1485 i2s2m1_sdi: i2s2m1-sdi {
1486 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1487 };
1488
1489 i2s2m1_sdo: i2s2m1-sdo {
1490 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1491 };
1492
1493 i2s2m1_sleep: i2s2m1-sleep {
1494 rockchip,pins =
1495 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1496 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1497 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1498 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1499 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1500 };
1501 };
1502
1503 spdif-0 {
1504 spdifm0_tx: spdifm0-tx {
1505 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1506 };
1507 };
1508
1509 spdif-1 {
1510 spdifm1_tx: spdifm1-tx {
1511 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1512 };
1513 };
1514
1515 spdif-2 {
1516 spdifm2_tx: spdifm2-tx {
1517 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1518 };
1519 };
1520
1521 sdmmc0-0 {
1522 sdmmc0m0_pwren: sdmmc0m0-pwren {
1523 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1524 };
1525
1526 sdmmc0m0_pin: sdmmc0m0-pin {
1527 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1528 };
1529 };
1530
1531 sdmmc0-1 {
1532 sdmmc0m1_pwren: sdmmc0m1-pwren {
1533 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1534 };
1535
1536 sdmmc0m1_pin: sdmmc0m1-pin {
1537 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1538 };
1539 };
1540
1541 sdmmc0 {
1542 sdmmc0_clk: sdmmc0-clk {
1543 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1544 };
1545
1546 sdmmc0_cmd: sdmmc0-cmd {
1547 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1548 };
1549
1550 sdmmc0_dectn: sdmmc0-dectn {
1551 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1552 };
1553
1554 sdmmc0_wrprt: sdmmc0-wrprt {
1555 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1556 };
1557
1558 sdmmc0_bus1: sdmmc0-bus1 {
1559 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1560 };
1561
1562 sdmmc0_bus4: sdmmc0-bus4 {
1563 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1564 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1565 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1566 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1567 };
1568
1569 sdmmc0_pins: sdmmc0-pins {
1570 rockchip,pins =
1571 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1572 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1573 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1574 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1575 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1576 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1577 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1578 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1579 };
1580 };
1581
1582 sdmmc0ext {
1583 sdmmc0ext_clk: sdmmc0ext-clk {
1584 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1585 };
1586
1587 sdmmc0ext_cmd: sdmmc0ext-cmd {
1588 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1589 };
1590
1591 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1592 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1593 };
1594
1595 sdmmc0ext_dectn: sdmmc0ext-dectn {
1596 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1597 };
1598
1599 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1600 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1601 };
1602
1603 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1604 rockchip,pins =
1605 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1606 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1607 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1608 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1609 };
1610
1611 sdmmc0ext_pins: sdmmc0ext-pins {
1612 rockchip,pins =
1613 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1614 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1615 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1616 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1617 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1618 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1619 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1620 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1621 };
1622 };
1623
1624 sdmmc1 {
1625 sdmmc1_clk: sdmmc1-clk {
1626 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1627 };
1628
1629 sdmmc1_cmd: sdmmc1-cmd {
1630 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1631 };
1632
1633 sdmmc1_pwren: sdmmc1-pwren {
1634 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1635 };
1636
1637 sdmmc1_wrprt: sdmmc1-wrprt {
1638 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1639 };
1640
1641 sdmmc1_dectn: sdmmc1-dectn {
1642 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1643 };
1644
1645 sdmmc1_bus1: sdmmc1-bus1 {
1646 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1647 };
1648
1649 sdmmc1_bus4: sdmmc1-bus4 {
1650 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1651 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1652 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1653 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1654 };
1655
1656 sdmmc1_pins: sdmmc1-pins {
1657 rockchip,pins =
1658 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1659 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1660 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1661 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1662 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1663 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1664 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1665 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1666 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1667 };
1668 };
1669
1670 emmc {
1671 emmc_clk: emmc-clk {
1672 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1673 };
1674
1675 emmc_cmd: emmc-cmd {
1676 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1677 };
1678
1679 emmc_pwren: emmc-pwren {
1680 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1681 };
1682
1683 emmc_rstnout: emmc-rstnout {
1684 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1685 };
1686
1687 emmc_bus1: emmc-bus1 {
1688 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1689 };
1690
1691 emmc_bus4: emmc-bus4 {
1692 rockchip,pins =
1693 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1694 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1695 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1696 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1697 };
1698
1699 emmc_bus8: emmc-bus8 {
1700 rockchip,pins =
1701 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1702 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1703 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1704 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1705 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1706 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1707 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1708 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1709 };
1710 };
1711
1712 pwm0 {
1713 pwm0_pin: pwm0-pin {
1714 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1715 };
1716 };
1717
1718 pwm1 {
1719 pwm1_pin: pwm1-pin {
1720 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1721 };
1722 };
1723
1724 pwm2 {
1725 pwm2_pin: pwm2-pin {
1726 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1727 };
1728 };
1729
1730 pwmir {
1731 pwmir_pin: pwmir-pin {
1732 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1733 };
1734 };
1735
1736 gmac-1 {
1737 rgmiim1_pins: rgmiim1-pins {
1738 rockchip,pins =
1739 /* mac_txclk */
1740 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1741 /* mac_rxclk */
1742 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1743 /* mac_mdio */
1744 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1745 /* mac_txen */
1746 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1747 /* mac_clk */
1748 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1749 /* mac_rxdv */
1750 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1751 /* mac_mdc */
1752 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1753 /* mac_rxd1 */
1754 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1755 /* mac_rxd0 */
1756 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1757 /* mac_txd1 */
1758 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1759 /* mac_txd0 */
1760 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1761 /* mac_rxd3 */
1762 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1763 /* mac_rxd2 */
1764 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1765 /* mac_txd3 */
1766 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1767 /* mac_txd2 */
1768 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1769
1770 /* mac_txclk */
1771 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1772 /* mac_txen */
1773 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1774 /* mac_clk */
1775 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1776 /* mac_txd1 */
1777 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1778 /* mac_txd0 */
1779 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1780 /* mac_txd3 */
1781 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1782 /* mac_txd2 */
1783 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1784 };
1785
1786 rmiim1_pins: rmiim1-pins {
1787 rockchip,pins =
1788 /* mac_mdio */
1789 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1790 /* mac_txen */
1791 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1792 /* mac_clk */
1793 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1794 /* mac_rxer */
1795 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1796 /* mac_rxdv */
1797 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1798 /* mac_mdc */
1799 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1800 /* mac_rxd1 */
1801 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1802 /* mac_rxd0 */
1803 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1804 /* mac_txd1 */
1805 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1806 /* mac_txd0 */
1807 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1808
1809 /* mac_mdio */
1810 <0 RK_PB3 1 &pcfg_pull_none>,
1811 /* mac_txen */
1812 <0 RK_PB4 1 &pcfg_pull_none>,
1813 /* mac_clk */
1814 <0 RK_PD0 1 &pcfg_pull_none>,
1815 /* mac_mdc */
1816 <0 RK_PC3 1 &pcfg_pull_none>,
1817 /* mac_txd1 */
1818 <0 RK_PC0 1 &pcfg_pull_none>,
1819 /* mac_txd0 */
1820 <0 RK_PC1 1 &pcfg_pull_none>;
1821 };
1822 };
1823
1824 gmac2phy {
1825 fephyled_speed10: fephyled-speed10 {
1826 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1827 };
1828
1829 fephyled_duplex: fephyled-duplex {
1830 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1831 };
1832
1833 fephyled_rxm1: fephyled-rxm1 {
1834 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1835 };
1836
1837 fephyled_txm1: fephyled-txm1 {
1838 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1839 };
1840
1841 fephyled_linkm1: fephyled-linkm1 {
1842 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1843 };
1844 };
1845
1846 tsadc_pin {
1847 tsadc_int: tsadc-int {
1848 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1849 };
1850 tsadc_pin: tsadc-pin {
1851 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1852 };
1853 };
1854
1855 hdmi_pin {
1856 hdmi_cec: hdmi-cec {
1857 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1858 };
1859
1860 hdmi_hpd: hdmi-hpd {
1861 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1862 };
1863 };
1864
1865 cif-0 {
1866 dvp_d2d9_m0:dvp-d2d9-m0 {
1867 rockchip,pins =
1868 /* cif_d0 */
1869 <3 RK_PA4 2 &pcfg_pull_none>,
1870 /* cif_d1 */
1871 <3 RK_PA5 2 &pcfg_pull_none>,
1872 /* cif_d2 */
1873 <3 RK_PA6 2 &pcfg_pull_none>,
1874 /* cif_d3 */
1875 <3 RK_PA7 2 &pcfg_pull_none>,
1876 /* cif_d4 */
1877 <3 RK_PB0 2 &pcfg_pull_none>,
1878 /* cif_d5m0 */
1879 <3 RK_PB1 2 &pcfg_pull_none>,
1880 /* cif_d6m0 */
1881 <3 RK_PB2 2 &pcfg_pull_none>,
1882 /* cif_d7m0 */
1883 <3 RK_PB3 2 &pcfg_pull_none>,
1884 /* cif_href */
1885 <3 RK_PA1 2 &pcfg_pull_none>,
1886 /* cif_vsync */
1887 <3 RK_PA0 2 &pcfg_pull_none>,
1888 /* cif_clkoutm0 */
1889 <3 RK_PA3 2 &pcfg_pull_none>,
1890 /* cif_clkin */
1891 <3 RK_PA2 2 &pcfg_pull_none>;
1892 };
1893 };
1894
1895 cif-1 {
1896 dvp_d2d9_m1:dvp-d2d9-m1 {
1897 rockchip,pins =
1898 /* cif_d0 */
1899 <3 RK_PA4 2 &pcfg_pull_none>,
1900 /* cif_d1 */
1901 <3 RK_PA5 2 &pcfg_pull_none>,
1902 /* cif_d2 */
1903 <3 RK_PA6 2 &pcfg_pull_none>,
1904 /* cif_d3 */
1905 <3 RK_PA7 2 &pcfg_pull_none>,
1906 /* cif_d4 */
1907 <3 RK_PB0 2 &pcfg_pull_none>,
1908 /* cif_d5m1 */
1909 <2 RK_PC0 4 &pcfg_pull_none>,
1910 /* cif_d6m1 */
1911 <2 RK_PC1 4 &pcfg_pull_none>,
1912 /* cif_d7m1 */
1913 <2 RK_PC2 4 &pcfg_pull_none>,
1914 /* cif_href */
1915 <3 RK_PA1 2 &pcfg_pull_none>,
1916 /* cif_vsync */
1917 <3 RK_PA0 2 &pcfg_pull_none>,
1918 /* cif_clkoutm1 */
1919 <2 RK_PB7 4 &pcfg_pull_none>,
1920 /* cif_clkin */
1921 <3 RK_PA2 2 &pcfg_pull_none>;
1922 };
1923 };
1924 };
1925 };
