arm64/renesas/rzg2ul-smarc-som.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003  * Device Tree Source for the RZ/G2UL SMARC SOM common parts
0004  *
0005  * Copyright (C) 2022 Renesas Electronics Corp.
0006  */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
0010
0011 / {
0012         aliases {
0013                 ethernet0 = &eth0;
0014                 ethernet1 = &eth1;
0015         };
0016
0017         chosen {
0018                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0019         };
0020
0021         memory@48000000 {
0022                 device_type = "memory";
0023                 /* first 128MB is reserved for secure area. */
0024                 reg = <0x0 0x48000000 0x0 0x38000000>;
0025         };
0026
0027         reg_1p8v: regulator-1p8v {
0028                 compatible = "regulator-fixed";
0029                 regulator-name = "fixed-1.8V";
0030                 regulator-min-microvolt = <1800000>;
0031                 regulator-max-microvolt = <1800000>;
0032                 regulator-boot-on;
0033                 regulator-always-on;
0034         };
0035
0036         reg_3p3v: regulator-3p3v {
0037                 compatible = "regulator-fixed";
0038                 regulator-name = "fixed-3.3V";
0039                 regulator-min-microvolt = <3300000>;
0040                 regulator-max-microvolt = <3300000>;
0041                 regulator-boot-on;
0042                 regulator-always-on;
0043         };
0044
0045 #if !(SW_SW0_DEV_SEL)
0046         vccq_sdhi0: regulator-vccq-sdhi0 {
0047                 compatible = "regulator-gpio";
0048
0049                 regulator-name = "SDHI0 VccQ";
0050                 regulator-min-microvolt = <1800000>;
0051                 regulator-max-microvolt = <3300000>;
0052                 states = <3300000 1>, <1800000 0>;
0053                 regulator-boot-on;
0054                 gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
0055                 regulator-always-on;
0056         };
0057 #endif
0058 };
0059
0060 #if (SW_SW0_DEV_SEL)
0061 &adc {
0062         pinctrl-0 = <&adc_pins>;
0063         pinctrl-names = "default";
0064         status = "okay";
0065 };
0066 #endif
0067
0068 #if (!SW_ET0_EN_N)
0069 &eth0 {
0070         pinctrl-0 = <&eth0_pins>;
0071         pinctrl-names = "default";
0072         phy-handle = <&phy0>;
0073         phy-mode = "rgmii-id";
0074         status = "okay";
0075
0076         phy0: ethernet-phy@7 {
0077                 compatible = "ethernet-phy-id0022.1640",
0078                              "ethernet-phy-ieee802.3-c22";
0079                 reg = <7>;
0080                 rxc-skew-psec = <2400>;
0081                 txc-skew-psec = <2400>;
0082                 rxdv-skew-psec = <0>;
0083                 txdv-skew-psec = <0>;
0084                 rxd0-skew-psec = <0>;
0085                 rxd1-skew-psec = <0>;
0086                 rxd2-skew-psec = <0>;
0087                 rxd3-skew-psec = <0>;
0088                 txd0-skew-psec = <0>;
0089                 txd1-skew-psec = <0>;
0090                 txd2-skew-psec = <0>;
0091                 txd3-skew-psec = <0>;
0092         };
0093 };
0094 #endif
0095
0096 &eth1 {
0097         pinctrl-0 = <&eth1_pins>;
0098         pinctrl-names = "default";
0099         phy-handle = <&phy1>;
0100         phy-mode = "rgmii-id";
0101         status = "okay";
0102
0103         phy1: ethernet-phy@7 {
0104                 compatible = "ethernet-phy-id0022.1640",
0105                              "ethernet-phy-ieee802.3-c22";
0106                 reg = <7>;
0107                 rxc-skew-psec = <2400>;
0108                 txc-skew-psec = <2400>;
0109                 rxdv-skew-psec = <0>;
0110                 txdv-skew-psec = <0>;
0111                 rxd0-skew-psec = <0>;
0112                 rxd1-skew-psec = <0>;
0113                 rxd2-skew-psec = <0>;
0114                 rxd3-skew-psec = <0>;
0115                 txd0-skew-psec = <0>;
0116                 txd1-skew-psec = <0>;
0117                 txd2-skew-psec = <0>;
0118                 txd3-skew-psec = <0>;
0119         };
0120 };
0121
0122 &extal_clk {
0123         clock-frequency = <24000000>;
0124 };
0125
0126 &ostm1 {
0127         status = "okay";
0128 };
0129
0130 &ostm2 {
0131         status = "okay";
0132 };
0133
0134 &pinctrl {
0135         adc_pins: adc {
0136                 pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
0137         };
0138
0139         eth0_pins: eth0 {
0140                 pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
0141                          <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
0142                          <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
0143                          <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
0144                          <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
0145                          <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
0146                          <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
0147                          <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
0148                          <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
0149                          <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
0150                          <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
0151                          <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
0152                          <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
0153                          <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
0154                          <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
0155         };
0156
0157         eth1_pins: eth1 {
0158                 pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
0159                          <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
0160                          <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
0161                          <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
0162                          <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
0163                          <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
0164                          <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
0165                          <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
0166                          <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
0167                          <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
0168                          <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
0169                          <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
0170                          <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
0171                          <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
0172                          <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
0173         };
0174
0175         sdhi0_emmc_pins: sd0emmc {
0176                 sd0_emmc_data {
0177                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
0178                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
0179                         power-source = <1800>;
0180                 };
0181
0182                 sd0_emmc_ctrl {
0183                         pins = "SD0_CLK", "SD0_CMD";
0184                         power-source = <1800>;
0185                 };
0186
0187                 sd0_emmc_rst {
0188                         pins = "SD0_RST#";
0189                         power-source = <1800>;
0190                 };
0191         };
0192
0193         sdhi0_pins: sd0 {
0194                 sd0_data {
0195                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0196                         power-source = <3300>;
0197                 };
0198
0199                 sd0_ctrl {
0200                         pins = "SD0_CLK", "SD0_CMD";
0201                         power-source = <3300>;
0202                 };
0203
0204                 sd0_mux {
0205                         pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
0206                 };
0207         };
0208
0209         sdhi0_pins_uhs: sd0_uhs {
0210                 sd0_data_uhs {
0211                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0212                         power-source = <1800>;
0213                 };
0214
0215                 sd0_ctrl_uhs {
0216                         pins = "SD0_CLK", "SD0_CMD";
0217                         power-source = <1800>;
0218                 };
0219
0220                 sd0_mux_uhs {
0221                         pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
0222                 };
0223         };
0224
0225         spi1_pins: rspi1 {
0226                 pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
0227                          <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
0228                          <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
0229                          <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
0230         };
0231 };
0232
0233 #if (SW_SW0_DEV_SEL)
0234 &sdhi0 {
0235         pinctrl-0 = <&sdhi0_emmc_pins>;
0236         pinctrl-1 = <&sdhi0_emmc_pins>;
0237         pinctrl-names = "default", "state_uhs";
0238
0239         vmmc-supply = <&reg_3p3v>;
0240         vqmmc-supply = <&reg_1p8v>;
0241         bus-width = <8>;
0242         mmc-hs200-1_8v;
0243         non-removable;
0244         fixed-emmc-driver-type = <1>;
0245         status = "okay";
0246 };
0247 #else
0248 &sdhi0 {
0249         pinctrl-0 = <&sdhi0_pins>;
0250         pinctrl-1 = <&sdhi0_pins_uhs>;
0251         pinctrl-names = "default", "state_uhs";
0252
0253         vmmc-supply = <&reg_3p3v>;
0254         vqmmc-supply = <&vccq_sdhi0>;
0255         bus-width = <4>;
0256         sd-uhs-sdr50;
0257         sd-uhs-sdr104;
0258         status = "okay";
0259 };
0260 #endif
0261
0262 &wdt0 {
0263         status = "okay";
0264         timeout-sec = <60>;
0265 };
0266
0267 &wdt2 {
0268         status = "okay";
0269         timeout-sec = <60>;
0270 };