0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/G2LC SMARC SOM common parts
0004 *
0005 * Copyright (C) 2021 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
0010
0011 / {
0012 aliases {
0013 ethernet0 = ð0;
0014 };
0015
0016 chosen {
0017 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0018 };
0019
0020 memory@48000000 {
0021 device_type = "memory";
0022 /* first 128MB is reserved for secure area. */
0023 reg = <0x0 0x48000000 0x0 0x38000000>;
0024 };
0025
0026 reg_1p8v: regulator-1p8v {
0027 compatible = "regulator-fixed";
0028 regulator-name = "fixed-1.8V";
0029 regulator-min-microvolt = <1800000>;
0030 regulator-max-microvolt = <1800000>;
0031 regulator-boot-on;
0032 regulator-always-on;
0033 };
0034
0035 reg_3p3v: regulator-3p3v {
0036 compatible = "regulator-fixed";
0037 regulator-name = "fixed-3.3V";
0038 regulator-min-microvolt = <3300000>;
0039 regulator-max-microvolt = <3300000>;
0040 regulator-boot-on;
0041 regulator-always-on;
0042 };
0043
0044 reg_1p1v: regulator-vdd-core {
0045 compatible = "regulator-fixed";
0046 regulator-name = "fixed-1.1V";
0047 regulator-min-microvolt = <1100000>;
0048 regulator-max-microvolt = <1100000>;
0049 regulator-boot-on;
0050 regulator-always-on;
0051 };
0052
0053 vccq_sdhi0: regulator-vccq-sdhi0 {
0054 compatible = "regulator-gpio";
0055
0056 regulator-name = "SDHI0 VccQ";
0057 regulator-min-microvolt = <1800000>;
0058 regulator-max-microvolt = <3300000>;
0059 states = <3300000 1>, <1800000 0>;
0060 regulator-boot-on;
0061 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
0062 regulator-always-on;
0063 };
0064 };
0065
0066 ð0 {
0067 pinctrl-0 = <ð0_pins>;
0068 pinctrl-names = "default";
0069 phy-handle = <&phy0>;
0070 phy-mode = "rgmii-id";
0071 status = "okay";
0072
0073 phy0: ethernet-phy@7 {
0074 compatible = "ethernet-phy-id0022.1640",
0075 "ethernet-phy-ieee802.3-c22";
0076 reg = <7>;
0077 rxc-skew-psec = <2400>;
0078 txc-skew-psec = <2400>;
0079 rxdv-skew-psec = <0>;
0080 txdv-skew-psec = <0>;
0081 rxd0-skew-psec = <0>;
0082 rxd1-skew-psec = <0>;
0083 rxd2-skew-psec = <0>;
0084 rxd3-skew-psec = <0>;
0085 txd0-skew-psec = <0>;
0086 txd1-skew-psec = <0>;
0087 txd2-skew-psec = <0>;
0088 txd3-skew-psec = <0>;
0089 };
0090 };
0091
0092 &extal_clk {
0093 clock-frequency = <24000000>;
0094 };
0095
0096 &gpu {
0097 mali-supply = <®_1p1v>;
0098 };
0099
0100 &ostm1 {
0101 status = "okay";
0102 };
0103
0104 &ostm2 {
0105 status = "okay";
0106 };
0107
0108 &pinctrl {
0109 eth0_pins: eth0 {
0110 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
0111 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
0112 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
0113 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
0114 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
0115 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
0116 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
0117 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
0118 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
0119 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
0120 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
0121 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
0122 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
0123 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
0124 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
0125 };
0126
0127 gpio-sd0-pwr-en-hog {
0128 gpio-hog;
0129 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
0130 output-high;
0131 line-name = "gpio_sd0_pwr_en";
0132 };
0133
0134 qspi0_pins: qspi0 {
0135 qspi0-data {
0136 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
0137 power-source = <1800>;
0138 };
0139
0140 qspi0-ctrl {
0141 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
0142 power-source = <1800>;
0143 };
0144 };
0145
0146 /*
0147 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
0148 * The below switch logic can be used to select the device between
0149 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
0150 * SW1[2] should be at OFF position to enable 64 GB eMMC
0151 * SW1[2] should be at position ON to enable uSD card CN3
0152 */
0153 gpio-sd0-dev-sel-hog {
0154 gpio-hog;
0155 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
0156 output-high;
0157 line-name = "gpio_sd0_dev_sel";
0158 };
0159
0160 sdhi0_emmc_pins: sd0emmc {
0161 sd0_emmc_data {
0162 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
0163 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
0164 power-source = <1800>;
0165 };
0166
0167 sd0_emmc_ctrl {
0168 pins = "SD0_CLK", "SD0_CMD";
0169 power-source = <1800>;
0170 };
0171
0172 sd0_emmc_rst {
0173 pins = "SD0_RST#";
0174 power-source = <1800>;
0175 };
0176 };
0177
0178 sdhi0_pins: sd0 {
0179 sd0_data {
0180 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0181 power-source = <3300>;
0182 };
0183
0184 sd0_ctrl {
0185 pins = "SD0_CLK", "SD0_CMD";
0186 power-source = <3300>;
0187 };
0188
0189 sd0_mux {
0190 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
0191 };
0192 };
0193
0194 sdhi0_pins_uhs: sd0_uhs {
0195 sd0_data_uhs {
0196 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0197 power-source = <1800>;
0198 };
0199
0200 sd0_ctrl_uhs {
0201 pins = "SD0_CLK", "SD0_CMD";
0202 power-source = <1800>;
0203 };
0204
0205 sd0_mux_uhs {
0206 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
0207 };
0208 };
0209 };
0210
0211 &sbc {
0212 pinctrl-0 = <&qspi0_pins>;
0213 pinctrl-names = "default";
0214 status = "okay";
0215
0216 flash@0 {
0217 compatible = "micron,mt25qu512a", "jedec,spi-nor";
0218 reg = <0>;
0219 m25p,fast-read;
0220 spi-max-frequency = <50000000>;
0221 spi-rx-bus-width = <4>;
0222
0223 partitions {
0224 compatible = "fixed-partitions";
0225 #address-cells = <1>;
0226 #size-cells = <1>;
0227
0228 boot@0 {
0229 reg = <0x00000000 0x2000000>;
0230 read-only;
0231 };
0232 user@2000000 {
0233 reg = <0x2000000 0x2000000>;
0234 };
0235 };
0236 };
0237 };
0238
0239 #if (!SW_SD0_DEV_SEL)
0240 &sdhi0 {
0241 pinctrl-0 = <&sdhi0_pins>;
0242 pinctrl-1 = <&sdhi0_pins_uhs>;
0243 pinctrl-names = "default", "state_uhs";
0244
0245 vmmc-supply = <®_3p3v>;
0246 vqmmc-supply = <&vccq_sdhi0>;
0247 bus-width = <4>;
0248 sd-uhs-sdr50;
0249 sd-uhs-sdr104;
0250 status = "okay";
0251 };
0252 #endif
0253
0254 #if SW_SD0_DEV_SEL
0255 &sdhi0 {
0256 pinctrl-0 = <&sdhi0_emmc_pins>;
0257 pinctrl-1 = <&sdhi0_emmc_pins>;
0258 pinctrl-names = "default", "state_uhs";
0259
0260 vmmc-supply = <®_3p3v>;
0261 vqmmc-supply = <®_1p8v>;
0262 bus-width = <8>;
0263 mmc-hs200-1_8v;
0264 non-removable;
0265 fixed-emmc-driver-type = <1>;
0266 status = "okay";
0267 };
0268 #endif
0269
0270 &wdt0 {
0271 status = "okay";
0272 timeout-sec = <60>;
0273 };
0274
0275 &wdt1 {
0276 status = "okay";
0277 timeout-sec = <60>;
0278 };
0279
0280 &wdt2 {
0281 status = "okay";
0282 timeout-sec = <60>;
0283 };
