arm64/renesas/rzg2l-smarc-som.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003  * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
0004  *
0005  * Copyright (C) 2021 Renesas Electronics Corp.
0006  */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
0010
0011 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
0012 #define EMMC    1
0013
0014 /*
0015  * To enable uSD card on CN3,
0016  * SW1[2] should be at position 3/ON.
0017  * Disable eMMC by setting "#define EMMC        0" above.
0018  */
0019 #define SDHI    (!EMMC)
0020
0021 / {
0022         aliases {
0023                 ethernet0 = &eth0;
0024                 ethernet1 = &eth1;
0025         };
0026
0027         chosen {
0028                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0029         };
0030
0031         memory@48000000 {
0032                 device_type = "memory";
0033                 /* first 128MB is reserved for secure area. */
0034                 reg = <0x0 0x48000000 0x0 0x78000000>;
0035         };
0036
0037         reg_1p8v: regulator-1p8v {
0038                 compatible = "regulator-fixed";
0039                 regulator-name = "fixed-1.8V";
0040                 regulator-min-microvolt = <1800000>;
0041                 regulator-max-microvolt = <1800000>;
0042                 regulator-boot-on;
0043                 regulator-always-on;
0044         };
0045
0046         reg_3p3v: regulator-3p3v {
0047                 compatible = "regulator-fixed";
0048                 regulator-name = "fixed-3.3V";
0049                 regulator-min-microvolt = <3300000>;
0050                 regulator-max-microvolt = <3300000>;
0051                 regulator-boot-on;
0052                 regulator-always-on;
0053         };
0054
0055         reg_1p1v: regulator-vdd-core {
0056                 compatible = "regulator-fixed";
0057                 regulator-name = "fixed-1.1V";
0058                 regulator-min-microvolt = <1100000>;
0059                 regulator-max-microvolt = <1100000>;
0060                 regulator-boot-on;
0061                 regulator-always-on;
0062         };
0063
0064         vccq_sdhi0: regulator-vccq-sdhi0 {
0065                 compatible = "regulator-gpio";
0066
0067                 regulator-name = "SDHI0 VccQ";
0068                 regulator-min-microvolt = <1800000>;
0069                 regulator-max-microvolt = <3300000>;
0070                 states = <3300000 1>, <1800000 0>;
0071                 regulator-boot-on;
0072                 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
0073                 regulator-always-on;
0074         };
0075 };
0076
0077 &adc {
0078         pinctrl-0 = <&adc_pins>;
0079         pinctrl-names = "default";
0080         status = "okay";
0081
0082         /delete-node/ channel@6;
0083         /delete-node/ channel@7;
0084 };
0085
0086 &eth0 {
0087         pinctrl-0 = <&eth0_pins>;
0088         pinctrl-names = "default";
0089         phy-handle = <&phy0>;
0090         phy-mode = "rgmii-id";
0091         status = "okay";
0092
0093         phy0: ethernet-phy@7 {
0094                 compatible = "ethernet-phy-id0022.1640",
0095                              "ethernet-phy-ieee802.3-c22";
0096                 reg = <7>;
0097                 rxc-skew-psec = <2400>;
0098                 txc-skew-psec = <2400>;
0099                 rxdv-skew-psec = <0>;
0100                 txdv-skew-psec = <0>;
0101                 rxd0-skew-psec = <0>;
0102                 rxd1-skew-psec = <0>;
0103                 rxd2-skew-psec = <0>;
0104                 rxd3-skew-psec = <0>;
0105                 txd0-skew-psec = <0>;
0106                 txd1-skew-psec = <0>;
0107                 txd2-skew-psec = <0>;
0108                 txd3-skew-psec = <0>;
0109         };
0110 };
0111
0112 &eth1 {
0113         pinctrl-0 = <&eth1_pins>;
0114         pinctrl-names = "default";
0115         phy-handle = <&phy1>;
0116         phy-mode = "rgmii-id";
0117         status = "okay";
0118
0119         phy1: ethernet-phy@7 {
0120                 compatible = "ethernet-phy-id0022.1640",
0121                              "ethernet-phy-ieee802.3-c22";
0122                 reg = <7>;
0123                 rxc-skew-psec = <2400>;
0124                 txc-skew-psec = <2400>;
0125                 rxdv-skew-psec = <0>;
0126                 txdv-skew-psec = <0>;
0127                 rxd0-skew-psec = <0>;
0128                 rxd1-skew-psec = <0>;
0129                 rxd2-skew-psec = <0>;
0130                 rxd3-skew-psec = <0>;
0131                 txd0-skew-psec = <0>;
0132                 txd1-skew-psec = <0>;
0133                 txd2-skew-psec = <0>;
0134                 txd3-skew-psec = <0>;
0135         };
0136 };
0137
0138 &extal_clk {
0139         clock-frequency = <24000000>;
0140 };
0141
0142 &gpu {
0143         mali-supply = <&reg_1p1v>;
0144 };
0145
0146 &ostm1 {
0147         status = "okay";
0148 };
0149
0150 &ostm2 {
0151         status = "okay";
0152 };
0153
0154 &pinctrl {
0155         adc_pins: adc {
0156                 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
0157         };
0158
0159         eth0_pins: eth0 {
0160                 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
0161                          <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
0162                          <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
0163                          <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
0164                          <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
0165                          <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
0166                          <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
0167                          <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
0168                          <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
0169                          <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
0170                          <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
0171                          <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
0172                          <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
0173                          <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
0174                          <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
0175         };
0176
0177         eth1_pins: eth1 {
0178                 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
0179                          <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
0180                          <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
0181                          <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
0182                          <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
0183                          <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
0184                          <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
0185                          <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
0186                          <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
0187                          <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
0188                          <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
0189                          <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
0190                          <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
0191                          <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
0192                          <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
0193         };
0194
0195         gpio-sd0-pwr-en-hog {
0196                 gpio-hog;
0197                 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
0198                 output-high;
0199                 line-name = "gpio_sd0_pwr_en";
0200         };
0201
0202         qspi0_pins: qspi0 {
0203                 qspi0-data {
0204                         pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
0205                         power-source = <1800>;
0206                 };
0207
0208                 qspi0-ctrl {
0209                         pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
0210                         power-source = <1800>;
0211                 };
0212         };
0213
0214         /*
0215          * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
0216          * The below switch logic can be used to select the device between
0217          * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
0218          * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
0219          * SW1[2] should be at position 3/ON to enable uSD card CN3
0220          */
0221         sd0-dev-sel-hog {
0222                 gpio-hog;
0223                 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
0224                 output-high;
0225                 line-name = "sd0_dev_sel";
0226         };
0227
0228         sdhi0_emmc_pins: sd0emmc {
0229                 sd0_emmc_data {
0230                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
0231                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
0232                         power-source = <1800>;
0233                 };
0234
0235                 sd0_emmc_ctrl {
0236                         pins = "SD0_CLK", "SD0_CMD";
0237                         power-source = <1800>;
0238                 };
0239
0240                 sd0_emmc_rst {
0241                         pins = "SD0_RST#";
0242                         power-source = <1800>;
0243                 };
0244         };
0245
0246         sdhi0_pins: sd0 {
0247                 sd0_data {
0248                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0249                         power-source = <3300>;
0250                 };
0251
0252                 sd0_ctrl {
0253                         pins = "SD0_CLK", "SD0_CMD";
0254                         power-source = <3300>;
0255                 };
0256
0257                 sd0_mux {
0258                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
0259                 };
0260         };
0261
0262         sdhi0_pins_uhs: sd0_uhs {
0263                 sd0_data_uhs {
0264                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
0265                         power-source = <1800>;
0266                 };
0267
0268                 sd0_ctrl_uhs {
0269                         pins = "SD0_CLK", "SD0_CMD";
0270                         power-source = <1800>;
0271                 };
0272
0273                 sd0_mux_uhs {
0274                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
0275                 };
0276         };
0277 };
0278
0279 &sbc {
0280         pinctrl-0 = <&qspi0_pins>;
0281         pinctrl-names = "default";
0282         status = "okay";
0283
0284         flash@0 {
0285                 compatible = "micron,mt25qu512a", "jedec,spi-nor";
0286                 reg = <0>;
0287                 m25p,fast-read;
0288                 spi-max-frequency = <50000000>;
0289                 spi-rx-bus-width = <4>;
0290
0291                 partitions {
0292                         compatible = "fixed-partitions";
0293                         #address-cells = <1>;
0294                         #size-cells = <1>;
0295
0296                         boot@0 {
0297                                 reg = <0x00000000 0x2000000>;
0298                                 read-only;
0299                         };
0300                         user@2000000 {
0301                                 reg = <0x2000000 0x2000000>;
0302                         };
0303                 };
0304         };
0305 };
0306
0307 #if SDHI
0308 &sdhi0 {
0309         pinctrl-0 = <&sdhi0_pins>;
0310         pinctrl-1 = <&sdhi0_pins_uhs>;
0311         pinctrl-names = "default", "state_uhs";
0312
0313         vmmc-supply = <&reg_3p3v>;
0314         vqmmc-supply = <&vccq_sdhi0>;
0315         bus-width = <4>;
0316         sd-uhs-sdr50;
0317         sd-uhs-sdr104;
0318         status = "okay";
0319 };
0320 #endif
0321
0322 #if EMMC
0323 &sdhi0 {
0324         pinctrl-0 = <&sdhi0_emmc_pins>;
0325         pinctrl-1 = <&sdhi0_emmc_pins>;
0326         pinctrl-names = "default", "state_uhs";
0327
0328         vmmc-supply = <&reg_3p3v>;
0329         vqmmc-supply = <&reg_1p8v>;
0330         bus-width = <8>;
0331         mmc-hs200-1_8v;
0332         non-removable;
0333         fixed-emmc-driver-type = <1>;
0334         status = "okay";
0335 };
0336 #endif
0337
0338 &wdt0 {
0339         status = "okay";
0340         timeout-sec = <60>;
0341 };
0342
0343 &wdt1 {
0344         status = "okay";
0345         timeout-sec = <60>;
0346 };
0347
0348 &wdt2 {
0349         status = "okay";
0350         timeout-sec = <60>;
0351 };