0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/V2M SoC
0004 *
0005 * Copyright (C) 2022 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/r9a09g011-cpg.h>
0010
0011 / {
0012 compatible = "renesas,r9a09g011";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
0017 extal_clk: extal {
0018 compatible = "fixed-clock";
0019 #clock-cells = <0>;
0020 /* This value must be overridden by the board */
0021 clock-frequency = <0>;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu-map {
0029 cluster0 {
0030 core0 {
0031 cpu = <&cpu0>;
0032 };
0033 };
0034 };
0035
0036 cpu0: cpu@0 {
0037 compatible = "arm,cortex-a53";
0038 reg = <0>;
0039 device_type = "cpu";
0040 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
0041 };
0042 };
0043
0044 soc: soc {
0045 compatible = "simple-bus";
0046 interrupt-parent = <&gic>;
0047 #address-cells = <2>;
0048 #size-cells = <2>;
0049 ranges;
0050
0051 gic: interrupt-controller@82000000 {
0052 compatible = "arm,gic-400";
0053 #interrupt-cells = <3>;
0054 #address-cells = <0>;
0055 interrupt-controller;
0056 reg = <0x0 0x82010000 0 0x1000>,
0057 <0x0 0x82020000 0 0x20000>,
0058 <0x0 0x82040000 0 0x20000>,
0059 <0x0 0x82060000 0 0x20000>;
0060 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0061 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
0062 clock-names = "clk";
0063 };
0064
0065 avb: ethernet@a3300000 {
0066 compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
0067 reg = <0 0xa3300000 0 0x800>;
0068 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
0069 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
0070 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
0072 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
0073 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
0074 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
0075 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
0076 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
0077 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
0078 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
0079 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
0085 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
0086 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
0087 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
0088 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
0090 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
0091 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
0092 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
0093 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
0094 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
0095 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
0096 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
0097 interrupt-names = "ch0", "ch1", "ch2", "ch3",
0098 "ch4", "ch5", "ch6", "ch7",
0099 "ch8", "ch9", "ch10", "ch11",
0100 "ch12", "ch13", "ch14", "ch15",
0101 "ch16", "ch17", "ch18", "ch19",
0102 "ch20", "ch21", "dia", "dib",
0103 "err_a", "err_b", "mgmt_a", "mgmt_b",
0104 "line3";
0105 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
0106 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
0107 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
0108 clock-names = "axi", "chi", "gptp";
0109 resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
0110 power-domains = <&cpg>;
0111 #address-cells = <1>;
0112 #size-cells = <0>;
0113 status = "disable";
0114 };
0115
0116 cpg: clock-controller@a3500000 {
0117 compatible = "renesas,r9a09g011-cpg";
0118 reg = <0 0xa3500000 0 0x1000>;
0119 clocks = <&extal_clk>;
0120 clock-names = "extal";
0121 #clock-cells = <2>;
0122 #reset-cells = <1>;
0123 #power-domain-cells = <0>;
0124 };
0125
0126 uart0: serial@a4040000 {
0127 compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
0128 reg = <0 0xa4040000 0 0x80>;
0129 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
0130 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
0131 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
0132 clock-names = "sclk", "pclk";
0133 status = "disabled";
0134 };
0135 };
0136
0137 timer {
0138 compatible = "arm,armv8-timer";
0139 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0140 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0141 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0142 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0143 };
0144 };
