0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/V2L SoC
0004 *
0005 * Copyright (C) 2021 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/r9a07g054-cpg.h>
0010
0011 / {
0012 compatible = "renesas,r9a07g054";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 audio_clk1: audio1-clk {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 /* This value must be overridden by boards that provide it */
0020 clock-frequency = <0>;
0021 };
0022
0023 audio_clk2: audio2-clk {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 /* This value must be overridden by boards that provide it */
0027 clock-frequency = <0>;
0028 };
0029
0030 /* External CAN clock - to be overridden by boards that provide it */
0031 can_clk: can-clk {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <0>;
0035 };
0036
0037 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
0038 extal_clk: extal-clk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 /* This value must be overridden by the board */
0042 clock-frequency = <0>;
0043 };
0044
0045 cluster0_opp: opp-table-0 {
0046 compatible = "operating-points-v2";
0047 opp-shared;
0048
0049 opp-150000000 {
0050 opp-hz = /bits/ 64 <150000000>;
0051 opp-microvolt = <1100000>;
0052 clock-latency-ns = <300000>;
0053 };
0054 opp-300000000 {
0055 opp-hz = /bits/ 64 <300000000>;
0056 opp-microvolt = <1100000>;
0057 clock-latency-ns = <300000>;
0058 };
0059 opp-600000000 {
0060 opp-hz = /bits/ 64 <600000000>;
0061 opp-microvolt = <1100000>;
0062 clock-latency-ns = <300000>;
0063 };
0064 opp-1200000000 {
0065 opp-hz = /bits/ 64 <1200000000>;
0066 opp-microvolt = <1100000>;
0067 clock-latency-ns = <300000>;
0068 opp-suspend;
0069 };
0070 };
0071
0072 cpus {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 cpu-map {
0077 cluster0 {
0078 core0 {
0079 cpu = <&cpu0>;
0080 };
0081 core1 {
0082 cpu = <&cpu1>;
0083 };
0084 };
0085 };
0086
0087 cpu0: cpu@0 {
0088 compatible = "arm,cortex-a55";
0089 reg = <0>;
0090 device_type = "cpu";
0091 #cooling-cells = <2>;
0092 next-level-cache = <&L3_CA55>;
0093 enable-method = "psci";
0094 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
0095 operating-points-v2 = <&cluster0_opp>;
0096 };
0097
0098 cpu1: cpu@100 {
0099 compatible = "arm,cortex-a55";
0100 reg = <0x100>;
0101 device_type = "cpu";
0102 next-level-cache = <&L3_CA55>;
0103 enable-method = "psci";
0104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
0105 operating-points-v2 = <&cluster0_opp>;
0106 };
0107
0108 L3_CA55: cache-controller-0 {
0109 compatible = "cache";
0110 cache-unified;
0111 cache-size = <0x40000>;
0112 };
0113 };
0114
0115 gpu_opp_table: opp-table-1 {
0116 compatible = "operating-points-v2";
0117
0118 opp-500000000 {
0119 opp-hz = /bits/ 64 <500000000>;
0120 opp-microvolt = <1100000>;
0121 };
0122
0123 opp-400000000 {
0124 opp-hz = /bits/ 64 <400000000>;
0125 opp-microvolt = <1100000>;
0126 };
0127
0128 opp-250000000 {
0129 opp-hz = /bits/ 64 <250000000>;
0130 opp-microvolt = <1100000>;
0131 };
0132
0133 opp-200000000 {
0134 opp-hz = /bits/ 64 <200000000>;
0135 opp-microvolt = <1100000>;
0136 };
0137
0138 opp-125000000 {
0139 opp-hz = /bits/ 64 <125000000>;
0140 opp-microvolt = <1100000>;
0141 };
0142
0143 opp-100000000 {
0144 opp-hz = /bits/ 64 <100000000>;
0145 opp-microvolt = <1100000>;
0146 };
0147
0148 opp-62500000 {
0149 opp-hz = /bits/ 64 <62500000>;
0150 opp-microvolt = <1100000>;
0151 };
0152
0153 opp-50000000 {
0154 opp-hz = /bits/ 64 <50000000>;
0155 opp-microvolt = <1100000>;
0156 };
0157 };
0158
0159 psci {
0160 compatible = "arm,psci-1.0", "arm,psci-0.2";
0161 method = "smc";
0162 };
0163
0164 soc: soc {
0165 compatible = "simple-bus";
0166 interrupt-parent = <&gic>;
0167 #address-cells = <2>;
0168 #size-cells = <2>;
0169 ranges;
0170
0171 ssi0: ssi@10049c00 {
0172 compatible = "renesas,r9a07g054-ssi",
0173 "renesas,rz-ssi";
0174 reg = <0 0x10049c00 0 0x400>;
0175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
0177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
0178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
0179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
0181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
0182 <&audio_clk1>, <&audio_clk2>;
0183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
0185 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
0186 dma-names = "tx", "rx";
0187 power-domains = <&cpg>;
0188 #sound-dai-cells = <0>;
0189 status = "disabled";
0190 };
0191
0192 ssi1: ssi@1004a000 {
0193 compatible = "renesas,r9a07g054-ssi",
0194 "renesas,rz-ssi";
0195 reg = <0 0x1004a000 0 0x400>;
0196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
0197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
0198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
0199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
0200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
0202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
0203 <&audio_clk1>, <&audio_clk2>;
0204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
0206 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
0207 dma-names = "tx", "rx";
0208 power-domains = <&cpg>;
0209 #sound-dai-cells = <0>;
0210 status = "disabled";
0211 };
0212
0213 ssi2: ssi@1004a400 {
0214 compatible = "renesas,r9a07g054-ssi",
0215 "renesas,rz-ssi";
0216 reg = <0 0x1004a400 0 0x400>;
0217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
0219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
0220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
0221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0222 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
0223 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
0224 <&audio_clk1>, <&audio_clk2>;
0225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0226 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
0227 dmas = <&dmac 0x265f>;
0228 dma-names = "rt";
0229 power-domains = <&cpg>;
0230 #sound-dai-cells = <0>;
0231 status = "disabled";
0232 };
0233
0234 ssi3: ssi@1004a800 {
0235 compatible = "renesas,r9a07g054-ssi",
0236 "renesas,rz-ssi";
0237 reg = <0 0x1004a800 0 0x400>;
0238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
0239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
0240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
0241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
0242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0243 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
0244 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
0245 <&audio_clk1>, <&audio_clk2>;
0246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0247 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
0248 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
0249 dma-names = "tx", "rx";
0250 power-domains = <&cpg>;
0251 #sound-dai-cells = <0>;
0252 status = "disabled";
0253 };
0254
0255 spi0: spi@1004ac00 {
0256 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
0257 reg = <0 0x1004ac00 0 0x400>;
0258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
0260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
0261 interrupt-names = "error", "rx", "tx";
0262 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
0263 resets = <&cpg R9A07G054_RSPI0_RST>;
0264 power-domains = <&cpg>;
0265 num-cs = <1>;
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268 status = "disabled";
0269 };
0270
0271 spi1: spi@1004b000 {
0272 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
0273 reg = <0 0x1004b000 0 0x400>;
0274 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
0275 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
0277 interrupt-names = "error", "rx", "tx";
0278 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
0279 resets = <&cpg R9A07G054_RSPI1_RST>;
0280 power-domains = <&cpg>;
0281 num-cs = <1>;
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 status = "disabled";
0285 };
0286
0287 spi2: spi@1004b400 {
0288 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
0289 reg = <0 0x1004b400 0 0x400>;
0290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
0293 interrupt-names = "error", "rx", "tx";
0294 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
0295 resets = <&cpg R9A07G054_RSPI2_RST>;
0296 power-domains = <&cpg>;
0297 num-cs = <1>;
0298 #address-cells = <1>;
0299 #size-cells = <0>;
0300 status = "disabled";
0301 };
0302
0303 scif0: serial@1004b800 {
0304 compatible = "renesas,scif-r9a07g054",
0305 "renesas,scif-r9a07g044";
0306 reg = <0 0x1004b800 0 0x400>;
0307 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
0309 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
0310 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
0311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
0312 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
0313 interrupt-names = "eri", "rxi", "txi",
0314 "bri", "dri", "tei";
0315 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
0316 clock-names = "fck";
0317 power-domains = <&cpg>;
0318 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
0319 status = "disabled";
0320 };
0321
0322 scif1: serial@1004bc00 {
0323 compatible = "renesas,scif-r9a07g054",
0324 "renesas,scif-r9a07g044";
0325 reg = <0 0x1004bc00 0 0x400>;
0326 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
0329 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
0330 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
0331 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
0332 interrupt-names = "eri", "rxi", "txi",
0333 "bri", "dri", "tei";
0334 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
0335 clock-names = "fck";
0336 power-domains = <&cpg>;
0337 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
0338 status = "disabled";
0339 };
0340
0341 scif2: serial@1004c000 {
0342 compatible = "renesas,scif-r9a07g054",
0343 "renesas,scif-r9a07g044";
0344 reg = <0 0x1004c000 0 0x400>;
0345 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
0348 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
0349 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
0350 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
0351 interrupt-names = "eri", "rxi", "txi",
0352 "bri", "dri", "tei";
0353 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
0354 clock-names = "fck";
0355 power-domains = <&cpg>;
0356 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
0357 status = "disabled";
0358 };
0359
0360 scif3: serial@1004c400 {
0361 compatible = "renesas,scif-r9a07g054",
0362 "renesas,scif-r9a07g044";
0363 reg = <0 0x1004c400 0 0x400>;
0364 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
0365 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
0366 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
0367 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
0368 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
0369 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
0370 interrupt-names = "eri", "rxi", "txi",
0371 "bri", "dri", "tei";
0372 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
0373 clock-names = "fck";
0374 power-domains = <&cpg>;
0375 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
0376 status = "disabled";
0377 };
0378
0379 scif4: serial@1004c800 {
0380 compatible = "renesas,scif-r9a07g054",
0381 "renesas,scif-r9a07g044";
0382 reg = <0 0x1004c800 0 0x400>;
0383 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
0384 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
0385 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
0386 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
0387 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
0388 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
0389 interrupt-names = "eri", "rxi", "txi",
0390 "bri", "dri", "tei";
0391 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
0392 clock-names = "fck";
0393 power-domains = <&cpg>;
0394 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
0395 status = "disabled";
0396 };
0397
0398 sci0: serial@1004d000 {
0399 compatible = "renesas,r9a07g054-sci", "renesas,sci";
0400 reg = <0 0x1004d000 0 0x400>;
0401 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
0402 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
0403 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
0404 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
0405 interrupt-names = "eri", "rxi", "txi", "tei";
0406 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
0407 clock-names = "fck";
0408 power-domains = <&cpg>;
0409 resets = <&cpg R9A07G054_SCI0_RST>;
0410 status = "disabled";
0411 };
0412
0413 sci1: serial@1004d400 {
0414 compatible = "renesas,r9a07g054-sci", "renesas,sci";
0415 reg = <0 0x1004d400 0 0x400>;
0416 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
0417 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
0418 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
0419 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
0420 interrupt-names = "eri", "rxi", "txi", "tei";
0421 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
0422 clock-names = "fck";
0423 power-domains = <&cpg>;
0424 resets = <&cpg R9A07G054_SCI1_RST>;
0425 status = "disabled";
0426 };
0427
0428 canfd: can@10050000 {
0429 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
0430 reg = <0 0x10050000 0 0x8000>;
0431 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
0432 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
0433 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
0434 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
0435 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
0436 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
0437 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
0438 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
0439 interrupt-names = "g_err", "g_recc",
0440 "ch0_err", "ch0_rec", "ch0_trx",
0441 "ch1_err", "ch1_rec", "ch1_trx";
0442 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
0443 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
0444 <&can_clk>;
0445 clock-names = "fck", "canfd", "can_clk";
0446 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
0447 assigned-clock-rates = <50000000>;
0448 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
0449 <&cpg R9A07G054_CANFD_RSTC_N>;
0450 reset-names = "rstp_n", "rstc_n";
0451 power-domains = <&cpg>;
0452 status = "disabled";
0453
0454 channel0 {
0455 status = "disabled";
0456 };
0457 channel1 {
0458 status = "disabled";
0459 };
0460 };
0461
0462 i2c0: i2c@10058000 {
0463 #address-cells = <1>;
0464 #size-cells = <0>;
0465 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
0466 reg = <0 0x10058000 0 0x400>;
0467 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
0468 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
0469 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
0470 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
0471 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
0472 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
0473 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
0474 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0475 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0476 "naki", "ali", "tmoi";
0477 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
0478 clock-frequency = <100000>;
0479 resets = <&cpg R9A07G054_I2C0_MRST>;
0480 power-domains = <&cpg>;
0481 status = "disabled";
0482 };
0483
0484 i2c1: i2c@10058400 {
0485 #address-cells = <1>;
0486 #size-cells = <0>;
0487 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
0488 reg = <0 0x10058400 0 0x400>;
0489 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
0490 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
0491 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
0492 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
0493 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
0494 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
0495 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
0496 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
0497 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0498 "naki", "ali", "tmoi";
0499 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
0500 clock-frequency = <100000>;
0501 resets = <&cpg R9A07G054_I2C1_MRST>;
0502 power-domains = <&cpg>;
0503 status = "disabled";
0504 };
0505
0506 i2c2: i2c@10058800 {
0507 #address-cells = <1>;
0508 #size-cells = <0>;
0509 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
0510 reg = <0 0x10058800 0 0x400>;
0511 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
0512 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
0513 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
0514 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
0515 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
0516 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
0517 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
0518 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
0519 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0520 "naki", "ali", "tmoi";
0521 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
0522 clock-frequency = <100000>;
0523 resets = <&cpg R9A07G054_I2C2_MRST>;
0524 power-domains = <&cpg>;
0525 status = "disabled";
0526 };
0527
0528 i2c3: i2c@10058c00 {
0529 #address-cells = <1>;
0530 #size-cells = <0>;
0531 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
0532 reg = <0 0x10058c00 0 0x400>;
0533 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
0534 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
0535 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
0536 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
0537 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
0538 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
0539 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
0540 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
0541 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0542 "naki", "ali", "tmoi";
0543 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
0544 clock-frequency = <100000>;
0545 resets = <&cpg R9A07G054_I2C3_MRST>;
0546 power-domains = <&cpg>;
0547 status = "disabled";
0548 };
0549
0550 adc: adc@10059000 {
0551 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
0552 reg = <0 0x10059000 0 0x400>;
0553 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
0554 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
0555 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
0556 clock-names = "adclk", "pclk";
0557 resets = <&cpg R9A07G054_ADC_PRESETN>,
0558 <&cpg R9A07G054_ADC_ADRST_N>;
0559 reset-names = "presetn", "adrst-n";
0560 power-domains = <&cpg>;
0561 status = "disabled";
0562
0563 #address-cells = <1>;
0564 #size-cells = <0>;
0565
0566 channel@0 {
0567 reg = <0>;
0568 };
0569 channel@1 {
0570 reg = <1>;
0571 };
0572 channel@2 {
0573 reg = <2>;
0574 };
0575 channel@3 {
0576 reg = <3>;
0577 };
0578 channel@4 {
0579 reg = <4>;
0580 };
0581 channel@5 {
0582 reg = <5>;
0583 };
0584 channel@6 {
0585 reg = <6>;
0586 };
0587 channel@7 {
0588 reg = <7>;
0589 };
0590 };
0591
0592 tsu: thermal@10059400 {
0593 compatible = "renesas,r9a07g054-tsu",
0594 "renesas,rzg2l-tsu";
0595 reg = <0 0x10059400 0 0x400>;
0596 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
0597 resets = <&cpg R9A07G054_TSU_PRESETN>;
0598 power-domains = <&cpg>;
0599 #thermal-sensor-cells = <1>;
0600 };
0601
0602 sbc: spi@10060000 {
0603 compatible = "renesas,r9a07g054-rpc-if",
0604 "renesas,rzg2l-rpc-if";
0605 reg = <0 0x10060000 0 0x10000>,
0606 <0 0x20000000 0 0x10000000>,
0607 <0 0x10070000 0 0x10000>;
0608 reg-names = "regs", "dirmap", "wbuf";
0609 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0610 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
0611 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
0612 resets = <&cpg R9A07G054_SPI_RST>;
0613 power-domains = <&cpg>;
0614 #address-cells = <1>;
0615 #size-cells = <0>;
0616 status = "disabled";
0617 };
0618
0619 cpg: clock-controller@11010000 {
0620 compatible = "renesas,r9a07g054-cpg";
0621 reg = <0 0x11010000 0 0x10000>;
0622 clocks = <&extal_clk>;
0623 clock-names = "extal";
0624 #clock-cells = <2>;
0625 #reset-cells = <1>;
0626 #power-domain-cells = <0>;
0627 };
0628
0629 sysc: system-controller@11020000 {
0630 compatible = "renesas,r9a07g054-sysc";
0631 reg = <0 0x11020000 0 0x10000>;
0632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0633 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0634 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0635 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0636 interrupt-names = "lpm_int", "ca55stbydone_int",
0637 "cm33stbyr_int", "ca55_deny";
0638 status = "disabled";
0639 };
0640
0641 pinctrl: pinctrl@11030000 {
0642 compatible = "renesas,r9a07g054-pinctrl",
0643 "renesas,r9a07g044-pinctrl";
0644 reg = <0 0x11030000 0 0x10000>;
0645 gpio-controller;
0646 #gpio-cells = <2>;
0647 gpio-ranges = <&pinctrl 0 0 392>;
0648 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
0649 power-domains = <&cpg>;
0650 resets = <&cpg R9A07G054_GPIO_RSTN>,
0651 <&cpg R9A07G054_GPIO_PORT_RESETN>,
0652 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
0653 };
0654
0655 dmac: dma-controller@11820000 {
0656 compatible = "renesas,r9a07g054-dmac",
0657 "renesas,rz-dmac";
0658 reg = <0 0x11820000 0 0x10000>,
0659 <0 0x11830000 0 0x10000>;
0660 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
0661 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
0662 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
0663 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
0664 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
0665 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
0666 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
0667 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
0668 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
0669 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
0670 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
0671 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
0672 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
0673 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
0674 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
0675 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
0676 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
0677 interrupt-names = "error",
0678 "ch0", "ch1", "ch2", "ch3",
0679 "ch4", "ch5", "ch6", "ch7",
0680 "ch8", "ch9", "ch10", "ch11",
0681 "ch12", "ch13", "ch14", "ch15";
0682 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
0683 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
0684 power-domains = <&cpg>;
0685 resets = <&cpg R9A07G054_DMAC_ARESETN>,
0686 <&cpg R9A07G054_DMAC_RST_ASYNC>;
0687 #dma-cells = <1>;
0688 dma-channels = <16>;
0689 };
0690
0691 gpu: gpu@11840000 {
0692 compatible = "renesas,r9a07g054-mali",
0693 "arm,mali-bifrost";
0694 reg = <0x0 0x11840000 0x0 0x10000>;
0695 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0696 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0697 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0698 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0699 interrupt-names = "job", "mmu", "gpu", "event";
0700 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
0701 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
0702 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
0703 clock-names = "gpu", "bus", "bus_ace";
0704 power-domains = <&cpg>;
0705 resets = <&cpg R9A07G054_GPU_RESETN>,
0706 <&cpg R9A07G054_GPU_AXI_RESETN>,
0707 <&cpg R9A07G054_GPU_ACE_RESETN>;
0708 reset-names = "rst", "axi_rst", "ace_rst";
0709 operating-points-v2 = <&gpu_opp_table>;
0710 };
0711
0712 gic: interrupt-controller@11900000 {
0713 compatible = "arm,gic-v3";
0714 #interrupt-cells = <3>;
0715 #address-cells = <0>;
0716 interrupt-controller;
0717 reg = <0x0 0x11900000 0 0x40000>,
0718 <0x0 0x11940000 0 0x60000>;
0719 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
0720 };
0721
0722 sdhi0: mmc@11c00000 {
0723 compatible = "renesas,sdhi-r9a07g054",
0724 "renesas,rcar-gen3-sdhi";
0725 reg = <0x0 0x11c00000 0 0x10000>;
0726 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0727 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0728 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
0729 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
0730 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
0731 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
0732 clock-names = "core", "clkh", "cd", "aclk";
0733 resets = <&cpg R9A07G054_SDHI0_IXRST>;
0734 power-domains = <&cpg>;
0735 status = "disabled";
0736 };
0737
0738 sdhi1: mmc@11c10000 {
0739 compatible = "renesas,sdhi-r9a07g054",
0740 "renesas,rcar-gen3-sdhi";
0741 reg = <0x0 0x11c10000 0 0x10000>;
0742 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0743 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0744 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
0745 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
0746 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
0747 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
0748 clock-names = "core", "clkh", "cd", "aclk";
0749 resets = <&cpg R9A07G054_SDHI1_IXRST>;
0750 power-domains = <&cpg>;
0751 status = "disabled";
0752 };
0753
0754 eth0: ethernet@11c20000 {
0755 compatible = "renesas,r9a07g054-gbeth",
0756 "renesas,rzg2l-gbeth";
0757 reg = <0 0x11c20000 0 0x10000>;
0758 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0759 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0760 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0761 interrupt-names = "mux", "fil", "arp_ns";
0762 phy-mode = "rgmii";
0763 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
0764 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
0765 <&cpg CPG_CORE R9A07G054_CLK_HP>;
0766 clock-names = "axi", "chi", "refclk";
0767 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
0768 power-domains = <&cpg>;
0769 #address-cells = <1>;
0770 #size-cells = <0>;
0771 status = "disabled";
0772 };
0773
0774 eth1: ethernet@11c30000 {
0775 compatible = "renesas,r9a07g054-gbeth",
0776 "renesas,rzg2l-gbeth";
0777 reg = <0 0x11c30000 0 0x10000>;
0778 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0779 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0780 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0781 interrupt-names = "mux", "fil", "arp_ns";
0782 phy-mode = "rgmii";
0783 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
0784 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
0785 <&cpg CPG_CORE R9A07G054_CLK_HP>;
0786 clock-names = "axi", "chi", "refclk";
0787 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
0788 power-domains = <&cpg>;
0789 #address-cells = <1>;
0790 #size-cells = <0>;
0791 status = "disabled";
0792 };
0793
0794 phyrst: usbphy-ctrl@11c40000 {
0795 compatible = "renesas,r9a07g054-usbphy-ctrl",
0796 "renesas,rzg2l-usbphy-ctrl";
0797 reg = <0 0x11c40000 0 0x10000>;
0798 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
0799 resets = <&cpg R9A07G054_USB_PRESETN>;
0800 power-domains = <&cpg>;
0801 #reset-cells = <1>;
0802 status = "disabled";
0803 };
0804
0805 ohci0: usb@11c50000 {
0806 compatible = "generic-ohci";
0807 reg = <0 0x11c50000 0 0x100>;
0808 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0809 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0810 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
0811 resets = <&phyrst 0>,
0812 <&cpg R9A07G054_USB_U2H0_HRESETN>;
0813 phys = <&usb2_phy0 1>;
0814 phy-names = "usb";
0815 power-domains = <&cpg>;
0816 status = "disabled";
0817 };
0818
0819 ohci1: usb@11c70000 {
0820 compatible = "generic-ohci";
0821 reg = <0 0x11c70000 0 0x100>;
0822 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0823 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0824 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
0825 resets = <&phyrst 1>,
0826 <&cpg R9A07G054_USB_U2H1_HRESETN>;
0827 phys = <&usb2_phy1 1>;
0828 phy-names = "usb";
0829 power-domains = <&cpg>;
0830 status = "disabled";
0831 };
0832
0833 ehci0: usb@11c50100 {
0834 compatible = "generic-ehci";
0835 reg = <0 0x11c50100 0 0x100>;
0836 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0837 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0838 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
0839 resets = <&phyrst 0>,
0840 <&cpg R9A07G054_USB_U2H0_HRESETN>;
0841 phys = <&usb2_phy0 2>;
0842 phy-names = "usb";
0843 companion = <&ohci0>;
0844 power-domains = <&cpg>;
0845 status = "disabled";
0846 };
0847
0848 ehci1: usb@11c70100 {
0849 compatible = "generic-ehci";
0850 reg = <0 0x11c70100 0 0x100>;
0851 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0852 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0853 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
0854 resets = <&phyrst 1>,
0855 <&cpg R9A07G054_USB_U2H1_HRESETN>;
0856 phys = <&usb2_phy1 2>;
0857 phy-names = "usb";
0858 companion = <&ohci1>;
0859 power-domains = <&cpg>;
0860 status = "disabled";
0861 };
0862
0863 usb2_phy0: usb-phy@11c50200 {
0864 compatible = "renesas,usb2-phy-r9a07g054",
0865 "renesas,rzg2l-usb2-phy";
0866 reg = <0 0x11c50200 0 0x700>;
0867 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0868 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0869 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
0870 resets = <&phyrst 0>;
0871 #phy-cells = <1>;
0872 power-domains = <&cpg>;
0873 status = "disabled";
0874 };
0875
0876 usb2_phy1: usb-phy@11c70200 {
0877 compatible = "renesas,usb2-phy-r9a07g054",
0878 "renesas,rzg2l-usb2-phy";
0879 reg = <0 0x11c70200 0 0x700>;
0880 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0881 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0882 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
0883 resets = <&phyrst 1>;
0884 #phy-cells = <1>;
0885 power-domains = <&cpg>;
0886 status = "disabled";
0887 };
0888
0889 hsusb: usb@11c60000 {
0890 compatible = "renesas,usbhs-r9a07g054",
0891 "renesas,rza2-usbhs";
0892 reg = <0 0x11c60000 0 0x10000>;
0893 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
0894 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0895 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0896 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0897 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
0898 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
0899 resets = <&phyrst 0>,
0900 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
0901 renesas,buswait = <7>;
0902 phys = <&usb2_phy0 3>;
0903 phy-names = "usb";
0904 power-domains = <&cpg>;
0905 status = "disabled";
0906 };
0907
0908 wdt0: watchdog@12800800 {
0909 compatible = "renesas,r9a07g054-wdt",
0910 "renesas,rzg2l-wdt";
0911 reg = <0 0x12800800 0 0x400>;
0912 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
0913 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
0914 clock-names = "pclk", "oscclk";
0915 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0916 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0917 interrupt-names = "wdt", "perrout";
0918 resets = <&cpg R9A07G054_WDT0_PRESETN>;
0919 power-domains = <&cpg>;
0920 status = "disabled";
0921 };
0922
0923 wdt1: watchdog@12800c00 {
0924 compatible = "renesas,r9a07g054-wdt",
0925 "renesas,rzg2l-wdt";
0926 reg = <0 0x12800C00 0 0x400>;
0927 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
0928 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
0929 clock-names = "pclk", "oscclk";
0930 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0931 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0932 interrupt-names = "wdt", "perrout";
0933 resets = <&cpg R9A07G054_WDT1_PRESETN>;
0934 power-domains = <&cpg>;
0935 status = "disabled";
0936 };
0937
0938 wdt2: watchdog@12800400 {
0939 compatible = "renesas,r9a07g054-wdt",
0940 "renesas,rzg2l-wdt";
0941 reg = <0 0x12800400 0 0x400>;
0942 clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
0943 <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
0944 clock-names = "pclk", "oscclk";
0945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0946 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0947 interrupt-names = "wdt", "perrout";
0948 resets = <&cpg R9A07G054_WDT2_PRESETN>;
0949 power-domains = <&cpg>;
0950 status = "disabled";
0951 };
0952
0953 ostm0: timer@12801000 {
0954 compatible = "renesas,r9a07g054-ostm",
0955 "renesas,ostm";
0956 reg = <0x0 0x12801000 0x0 0x400>;
0957 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
0958 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
0959 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
0960 power-domains = <&cpg>;
0961 status = "disabled";
0962 };
0963
0964 ostm1: timer@12801400 {
0965 compatible = "renesas,r9a07g054-ostm",
0966 "renesas,ostm";
0967 reg = <0x0 0x12801400 0x0 0x400>;
0968 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
0969 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
0970 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
0971 power-domains = <&cpg>;
0972 status = "disabled";
0973 };
0974
0975 ostm2: timer@12801800 {
0976 compatible = "renesas,r9a07g054-ostm",
0977 "renesas,ostm";
0978 reg = <0x0 0x12801800 0x0 0x400>;
0979 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
0980 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
0981 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
0982 power-domains = <&cpg>;
0983 status = "disabled";
0984 };
0985 };
0986
0987 thermal-zones {
0988 cpu-thermal {
0989 polling-delay-passive = <250>;
0990 polling-delay = <1000>;
0991 thermal-sensors = <&tsu 0>;
0992 sustainable-power = <717>;
0993
0994 cooling-maps {
0995 map0 {
0996 trip = <&target>;
0997 cooling-device = <&cpu0 0 2>;
0998 contribution = <1024>;
0999 };
1000 };
1001
1002 trips {
1003 sensor_crit: sensor-crit {
1004 temperature = <125000>;
1005 hysteresis = <1000>;
1006 type = "critical";
1007 };
1008
1009 target: trip-point {
1010 temperature = <100000>;
1011 hysteresis = <1000>;
1012 type = "passive";
1013 };
1014 };
1015 };
1016 };
1017
1018 timer {
1019 compatible = "arm,armv8-timer";
1020 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1021 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1022 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1023 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1024 };
1025 };
