0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
0004 *
0005 * Copyright (C) 2021 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/r9a07g044-cpg.h>
0010
0011 / {
0012 compatible = "renesas,r9a07g044";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 audio_clk1: audio1-clk {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 /* This value must be overridden by boards that provide it */
0020 clock-frequency = <0>;
0021 };
0022
0023 audio_clk2: audio2-clk {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 /* This value must be overridden by boards that provide it */
0027 clock-frequency = <0>;
0028 };
0029
0030 /* External CAN clock - to be overridden by boards that provide it */
0031 can_clk: can-clk {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <0>;
0035 };
0036
0037 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
0038 extal_clk: extal-clk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 /* This value must be overridden by the board */
0042 clock-frequency = <0>;
0043 };
0044
0045 cluster0_opp: opp-table-0 {
0046 compatible = "operating-points-v2";
0047 opp-shared;
0048
0049 opp-150000000 {
0050 opp-hz = /bits/ 64 <150000000>;
0051 opp-microvolt = <1100000>;
0052 clock-latency-ns = <300000>;
0053 };
0054 opp-300000000 {
0055 opp-hz = /bits/ 64 <300000000>;
0056 opp-microvolt = <1100000>;
0057 clock-latency-ns = <300000>;
0058 };
0059 opp-600000000 {
0060 opp-hz = /bits/ 64 <600000000>;
0061 opp-microvolt = <1100000>;
0062 clock-latency-ns = <300000>;
0063 };
0064 opp-1200000000 {
0065 opp-hz = /bits/ 64 <1200000000>;
0066 opp-microvolt = <1100000>;
0067 clock-latency-ns = <300000>;
0068 opp-suspend;
0069 };
0070 };
0071
0072 cpus {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 cpu-map {
0077 cluster0 {
0078 core0 {
0079 cpu = <&cpu0>;
0080 };
0081 core1 {
0082 cpu = <&cpu1>;
0083 };
0084 };
0085 };
0086
0087 cpu0: cpu@0 {
0088 compatible = "arm,cortex-a55";
0089 reg = <0>;
0090 device_type = "cpu";
0091 #cooling-cells = <2>;
0092 next-level-cache = <&L3_CA55>;
0093 enable-method = "psci";
0094 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
0095 operating-points-v2 = <&cluster0_opp>;
0096 };
0097
0098 cpu1: cpu@100 {
0099 compatible = "arm,cortex-a55";
0100 reg = <0x100>;
0101 device_type = "cpu";
0102 next-level-cache = <&L3_CA55>;
0103 enable-method = "psci";
0104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
0105 operating-points-v2 = <&cluster0_opp>;
0106 };
0107
0108 L3_CA55: cache-controller-0 {
0109 compatible = "cache";
0110 cache-unified;
0111 cache-size = <0x40000>;
0112 };
0113 };
0114
0115 gpu_opp_table: opp-table-1 {
0116 compatible = "operating-points-v2";
0117
0118 opp-500000000 {
0119 opp-hz = /bits/ 64 <500000000>;
0120 opp-microvolt = <1100000>;
0121 };
0122
0123 opp-400000000 {
0124 opp-hz = /bits/ 64 <400000000>;
0125 opp-microvolt = <1100000>;
0126 };
0127
0128 opp-250000000 {
0129 opp-hz = /bits/ 64 <250000000>;
0130 opp-microvolt = <1100000>;
0131 };
0132
0133 opp-200000000 {
0134 opp-hz = /bits/ 64 <200000000>;
0135 opp-microvolt = <1100000>;
0136 };
0137
0138 opp-125000000 {
0139 opp-hz = /bits/ 64 <125000000>;
0140 opp-microvolt = <1100000>;
0141 };
0142
0143 opp-100000000 {
0144 opp-hz = /bits/ 64 <100000000>;
0145 opp-microvolt = <1100000>;
0146 };
0147
0148 opp-62500000 {
0149 opp-hz = /bits/ 64 <62500000>;
0150 opp-microvolt = <1100000>;
0151 };
0152
0153 opp-50000000 {
0154 opp-hz = /bits/ 64 <50000000>;
0155 opp-microvolt = <1100000>;
0156 };
0157 };
0158
0159 psci {
0160 compatible = "arm,psci-1.0", "arm,psci-0.2";
0161 method = "smc";
0162 };
0163
0164 soc: soc {
0165 compatible = "simple-bus";
0166 interrupt-parent = <&gic>;
0167 #address-cells = <2>;
0168 #size-cells = <2>;
0169 ranges;
0170
0171 ssi0: ssi@10049c00 {
0172 compatible = "renesas,r9a07g044-ssi",
0173 "renesas,rz-ssi";
0174 reg = <0 0x10049c00 0 0x400>;
0175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
0177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
0178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
0179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
0181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
0182 <&audio_clk1>, <&audio_clk2>;
0183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
0185 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
0186 dma-names = "tx", "rx";
0187 power-domains = <&cpg>;
0188 #sound-dai-cells = <0>;
0189 status = "disabled";
0190 };
0191
0192 ssi1: ssi@1004a000 {
0193 compatible = "renesas,r9a07g044-ssi",
0194 "renesas,rz-ssi";
0195 reg = <0 0x1004a000 0 0x400>;
0196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
0197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
0198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
0199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
0200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0201 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
0202 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
0203 <&audio_clk1>, <&audio_clk2>;
0204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0205 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
0206 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
0207 dma-names = "tx", "rx";
0208 power-domains = <&cpg>;
0209 #sound-dai-cells = <0>;
0210 status = "disabled";
0211 };
0212
0213 ssi2: ssi@1004a400 {
0214 compatible = "renesas,r9a07g044-ssi",
0215 "renesas,rz-ssi";
0216 reg = <0 0x1004a400 0 0x400>;
0217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
0219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
0220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
0221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0222 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
0223 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
0224 <&audio_clk1>, <&audio_clk2>;
0225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0226 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
0227 dmas = <&dmac 0x265f>;
0228 dma-names = "rt";
0229 power-domains = <&cpg>;
0230 #sound-dai-cells = <0>;
0231 status = "disabled";
0232 };
0233
0234 ssi3: ssi@1004a800 {
0235 compatible = "renesas,r9a07g044-ssi",
0236 "renesas,rz-ssi";
0237 reg = <0 0x1004a800 0 0x400>;
0238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
0239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
0240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
0241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
0242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0243 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
0244 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
0245 <&audio_clk1>, <&audio_clk2>;
0246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0247 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
0248 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
0249 dma-names = "tx", "rx";
0250 power-domains = <&cpg>;
0251 #sound-dai-cells = <0>;
0252 status = "disabled";
0253 };
0254
0255 spi0: spi@1004ac00 {
0256 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
0257 reg = <0 0x1004ac00 0 0x400>;
0258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
0260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
0261 interrupt-names = "error", "rx", "tx";
0262 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
0263 resets = <&cpg R9A07G044_RSPI0_RST>;
0264 power-domains = <&cpg>;
0265 num-cs = <1>;
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268 status = "disabled";
0269 };
0270
0271 spi1: spi@1004b000 {
0272 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
0273 reg = <0 0x1004b000 0 0x400>;
0274 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
0275 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
0277 interrupt-names = "error", "rx", "tx";
0278 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
0279 resets = <&cpg R9A07G044_RSPI1_RST>;
0280 power-domains = <&cpg>;
0281 num-cs = <1>;
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 status = "disabled";
0285 };
0286
0287 spi2: spi@1004b400 {
0288 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
0289 reg = <0 0x1004b400 0 0x400>;
0290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
0293 interrupt-names = "error", "rx", "tx";
0294 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
0295 resets = <&cpg R9A07G044_RSPI2_RST>;
0296 power-domains = <&cpg>;
0297 num-cs = <1>;
0298 #address-cells = <1>;
0299 #size-cells = <0>;
0300 status = "disabled";
0301 };
0302
0303 scif0: serial@1004b800 {
0304 compatible = "renesas,scif-r9a07g044";
0305 reg = <0 0x1004b800 0 0x400>;
0306 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
0307 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
0309 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
0310 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
0311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
0312 interrupt-names = "eri", "rxi", "txi",
0313 "bri", "dri", "tei";
0314 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
0315 clock-names = "fck";
0316 power-domains = <&cpg>;
0317 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
0318 status = "disabled";
0319 };
0320
0321 scif1: serial@1004bc00 {
0322 compatible = "renesas,scif-r9a07g044";
0323 reg = <0 0x1004bc00 0 0x400>;
0324 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
0325 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
0329 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
0330 interrupt-names = "eri", "rxi", "txi",
0331 "bri", "dri", "tei";
0332 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
0333 clock-names = "fck";
0334 power-domains = <&cpg>;
0335 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
0336 status = "disabled";
0337 };
0338
0339 scif2: serial@1004c000 {
0340 compatible = "renesas,scif-r9a07g044";
0341 reg = <0 0x1004c000 0 0x400>;
0342 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
0343 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
0344 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
0348 interrupt-names = "eri", "rxi", "txi",
0349 "bri", "dri", "tei";
0350 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
0351 clock-names = "fck";
0352 power-domains = <&cpg>;
0353 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
0354 status = "disabled";
0355 };
0356
0357 scif3: serial@1004c400 {
0358 compatible = "renesas,scif-r9a07g044";
0359 reg = <0 0x1004c400 0 0x400>;
0360 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
0361 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
0362 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
0363 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
0364 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
0365 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
0366 interrupt-names = "eri", "rxi", "txi",
0367 "bri", "dri", "tei";
0368 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
0369 clock-names = "fck";
0370 power-domains = <&cpg>;
0371 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
0372 status = "disabled";
0373 };
0374
0375 scif4: serial@1004c800 {
0376 compatible = "renesas,scif-r9a07g044";
0377 reg = <0 0x1004c800 0 0x400>;
0378 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
0379 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
0380 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
0381 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
0382 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
0383 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
0384 interrupt-names = "eri", "rxi", "txi",
0385 "bri", "dri", "tei";
0386 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
0387 clock-names = "fck";
0388 power-domains = <&cpg>;
0389 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
0390 status = "disabled";
0391 };
0392
0393 sci0: serial@1004d000 {
0394 compatible = "renesas,r9a07g044-sci", "renesas,sci";
0395 reg = <0 0x1004d000 0 0x400>;
0396 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
0397 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
0398 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
0399 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
0400 interrupt-names = "eri", "rxi", "txi", "tei";
0401 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
0402 clock-names = "fck";
0403 power-domains = <&cpg>;
0404 resets = <&cpg R9A07G044_SCI0_RST>;
0405 status = "disabled";
0406 };
0407
0408 sci1: serial@1004d400 {
0409 compatible = "renesas,r9a07g044-sci", "renesas,sci";
0410 reg = <0 0x1004d400 0 0x400>;
0411 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
0412 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
0413 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
0414 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
0415 interrupt-names = "eri", "rxi", "txi", "tei";
0416 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
0417 clock-names = "fck";
0418 power-domains = <&cpg>;
0419 resets = <&cpg R9A07G044_SCI1_RST>;
0420 status = "disabled";
0421 };
0422
0423 canfd: can@10050000 {
0424 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
0425 reg = <0 0x10050000 0 0x8000>;
0426 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
0427 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
0428 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
0429 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
0430 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
0431 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
0432 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
0433 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
0434 interrupt-names = "g_err", "g_recc",
0435 "ch0_err", "ch0_rec", "ch0_trx",
0436 "ch1_err", "ch1_rec", "ch1_trx";
0437 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
0438 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
0439 <&can_clk>;
0440 clock-names = "fck", "canfd", "can_clk";
0441 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
0442 assigned-clock-rates = <50000000>;
0443 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
0444 <&cpg R9A07G044_CANFD_RSTC_N>;
0445 reset-names = "rstp_n", "rstc_n";
0446 power-domains = <&cpg>;
0447 status = "disabled";
0448
0449 channel0 {
0450 status = "disabled";
0451 };
0452 channel1 {
0453 status = "disabled";
0454 };
0455 };
0456
0457 i2c0: i2c@10058000 {
0458 #address-cells = <1>;
0459 #size-cells = <0>;
0460 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
0461 reg = <0 0x10058000 0 0x400>;
0462 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
0463 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
0464 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
0465 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
0466 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
0467 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
0468 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
0469 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0470 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0471 "naki", "ali", "tmoi";
0472 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
0473 clock-frequency = <100000>;
0474 resets = <&cpg R9A07G044_I2C0_MRST>;
0475 power-domains = <&cpg>;
0476 status = "disabled";
0477 };
0478
0479 i2c1: i2c@10058400 {
0480 #address-cells = <1>;
0481 #size-cells = <0>;
0482 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
0483 reg = <0 0x10058400 0 0x400>;
0484 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
0485 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
0486 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
0487 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
0488 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
0489 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
0490 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
0491 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
0492 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0493 "naki", "ali", "tmoi";
0494 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
0495 clock-frequency = <100000>;
0496 resets = <&cpg R9A07G044_I2C1_MRST>;
0497 power-domains = <&cpg>;
0498 status = "disabled";
0499 };
0500
0501 i2c2: i2c@10058800 {
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
0505 reg = <0 0x10058800 0 0x400>;
0506 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
0507 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
0508 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
0509 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
0510 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
0511 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
0512 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
0513 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
0514 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0515 "naki", "ali", "tmoi";
0516 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
0517 clock-frequency = <100000>;
0518 resets = <&cpg R9A07G044_I2C2_MRST>;
0519 power-domains = <&cpg>;
0520 status = "disabled";
0521 };
0522
0523 i2c3: i2c@10058c00 {
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
0527 reg = <0 0x10058c00 0 0x400>;
0528 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
0529 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
0530 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
0531 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
0532 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
0533 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
0534 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
0535 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
0536 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0537 "naki", "ali", "tmoi";
0538 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
0539 clock-frequency = <100000>;
0540 resets = <&cpg R9A07G044_I2C3_MRST>;
0541 power-domains = <&cpg>;
0542 status = "disabled";
0543 };
0544
0545 adc: adc@10059000 {
0546 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
0547 reg = <0 0x10059000 0 0x400>;
0548 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
0549 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
0550 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
0551 clock-names = "adclk", "pclk";
0552 resets = <&cpg R9A07G044_ADC_PRESETN>,
0553 <&cpg R9A07G044_ADC_ADRST_N>;
0554 reset-names = "presetn", "adrst-n";
0555 power-domains = <&cpg>;
0556 status = "disabled";
0557
0558 #address-cells = <1>;
0559 #size-cells = <0>;
0560
0561 channel@0 {
0562 reg = <0>;
0563 };
0564 channel@1 {
0565 reg = <1>;
0566 };
0567 channel@2 {
0568 reg = <2>;
0569 };
0570 channel@3 {
0571 reg = <3>;
0572 };
0573 channel@4 {
0574 reg = <4>;
0575 };
0576 channel@5 {
0577 reg = <5>;
0578 };
0579 channel@6 {
0580 reg = <6>;
0581 };
0582 channel@7 {
0583 reg = <7>;
0584 };
0585 };
0586
0587 tsu: thermal@10059400 {
0588 compatible = "renesas,r9a07g044-tsu",
0589 "renesas,rzg2l-tsu";
0590 reg = <0 0x10059400 0 0x400>;
0591 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
0592 resets = <&cpg R9A07G044_TSU_PRESETN>;
0593 power-domains = <&cpg>;
0594 #thermal-sensor-cells = <1>;
0595 };
0596
0597 sbc: spi@10060000 {
0598 compatible = "renesas,r9a07g044-rpc-if",
0599 "renesas,rzg2l-rpc-if";
0600 reg = <0 0x10060000 0 0x10000>,
0601 <0 0x20000000 0 0x10000000>,
0602 <0 0x10070000 0 0x10000>;
0603 reg-names = "regs", "dirmap", "wbuf";
0604 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0605 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
0606 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
0607 resets = <&cpg R9A07G044_SPI_RST>;
0608 power-domains = <&cpg>;
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 status = "disabled";
0612 };
0613
0614 cpg: clock-controller@11010000 {
0615 compatible = "renesas,r9a07g044-cpg";
0616 reg = <0 0x11010000 0 0x10000>;
0617 clocks = <&extal_clk>;
0618 clock-names = "extal";
0619 #clock-cells = <2>;
0620 #reset-cells = <1>;
0621 #power-domain-cells = <0>;
0622 };
0623
0624 sysc: system-controller@11020000 {
0625 compatible = "renesas,r9a07g044-sysc";
0626 reg = <0 0x11020000 0 0x10000>;
0627 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0628 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0629 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0630 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0631 interrupt-names = "lpm_int", "ca55stbydone_int",
0632 "cm33stbyr_int", "ca55_deny";
0633 status = "disabled";
0634 };
0635
0636 pinctrl: pinctrl@11030000 {
0637 compatible = "renesas,r9a07g044-pinctrl";
0638 reg = <0 0x11030000 0 0x10000>;
0639 gpio-controller;
0640 #gpio-cells = <2>;
0641 gpio-ranges = <&pinctrl 0 0 392>;
0642 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
0643 power-domains = <&cpg>;
0644 resets = <&cpg R9A07G044_GPIO_RSTN>,
0645 <&cpg R9A07G044_GPIO_PORT_RESETN>,
0646 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
0647 };
0648
0649 dmac: dma-controller@11820000 {
0650 compatible = "renesas,r9a07g044-dmac",
0651 "renesas,rz-dmac";
0652 reg = <0 0x11820000 0 0x10000>,
0653 <0 0x11830000 0 0x10000>;
0654 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
0655 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
0656 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
0657 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
0658 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
0659 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
0660 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
0661 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
0662 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
0663 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
0664 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
0665 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
0666 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
0667 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
0668 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
0669 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
0670 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
0671 interrupt-names = "error",
0672 "ch0", "ch1", "ch2", "ch3",
0673 "ch4", "ch5", "ch6", "ch7",
0674 "ch8", "ch9", "ch10", "ch11",
0675 "ch12", "ch13", "ch14", "ch15";
0676 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
0677 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
0678 power-domains = <&cpg>;
0679 resets = <&cpg R9A07G044_DMAC_ARESETN>,
0680 <&cpg R9A07G044_DMAC_RST_ASYNC>;
0681 #dma-cells = <1>;
0682 dma-channels = <16>;
0683 };
0684
0685 gpu: gpu@11840000 {
0686 compatible = "renesas,r9a07g044-mali",
0687 "arm,mali-bifrost";
0688 reg = <0x0 0x11840000 0x0 0x10000>;
0689 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0690 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0691 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0692 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0693 interrupt-names = "job", "mmu", "gpu", "event";
0694 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
0695 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
0696 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
0697 clock-names = "gpu", "bus", "bus_ace";
0698 power-domains = <&cpg>;
0699 resets = <&cpg R9A07G044_GPU_RESETN>,
0700 <&cpg R9A07G044_GPU_AXI_RESETN>,
0701 <&cpg R9A07G044_GPU_ACE_RESETN>;
0702 reset-names = "rst", "axi_rst", "ace_rst";
0703 operating-points-v2 = <&gpu_opp_table>;
0704 };
0705
0706 gic: interrupt-controller@11900000 {
0707 compatible = "arm,gic-v3";
0708 #interrupt-cells = <3>;
0709 #address-cells = <0>;
0710 interrupt-controller;
0711 reg = <0x0 0x11900000 0 0x40000>,
0712 <0x0 0x11940000 0 0x60000>;
0713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
0714 };
0715
0716 sdhi0: mmc@11c00000 {
0717 compatible = "renesas,sdhi-r9a07g044",
0718 "renesas,rcar-gen3-sdhi";
0719 reg = <0x0 0x11c00000 0 0x10000>;
0720 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0721 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0722 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
0723 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
0724 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
0725 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
0726 clock-names = "core", "clkh", "cd", "aclk";
0727 resets = <&cpg R9A07G044_SDHI0_IXRST>;
0728 power-domains = <&cpg>;
0729 status = "disabled";
0730 };
0731
0732 sdhi1: mmc@11c10000 {
0733 compatible = "renesas,sdhi-r9a07g044",
0734 "renesas,rcar-gen3-sdhi";
0735 reg = <0x0 0x11c10000 0 0x10000>;
0736 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0737 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0738 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
0739 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
0740 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
0741 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
0742 clock-names = "core", "clkh", "cd", "aclk";
0743 resets = <&cpg R9A07G044_SDHI1_IXRST>;
0744 power-domains = <&cpg>;
0745 status = "disabled";
0746 };
0747
0748 eth0: ethernet@11c20000 {
0749 compatible = "renesas,r9a07g044-gbeth",
0750 "renesas,rzg2l-gbeth";
0751 reg = <0 0x11c20000 0 0x10000>;
0752 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0753 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0754 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0755 interrupt-names = "mux", "fil", "arp_ns";
0756 phy-mode = "rgmii";
0757 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
0758 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
0759 <&cpg CPG_CORE R9A07G044_CLK_HP>;
0760 clock-names = "axi", "chi", "refclk";
0761 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
0762 power-domains = <&cpg>;
0763 #address-cells = <1>;
0764 #size-cells = <0>;
0765 status = "disabled";
0766 };
0767
0768 eth1: ethernet@11c30000 {
0769 compatible = "renesas,r9a07g044-gbeth",
0770 "renesas,rzg2l-gbeth";
0771 reg = <0 0x11c30000 0 0x10000>;
0772 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0773 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0774 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0775 interrupt-names = "mux", "fil", "arp_ns";
0776 phy-mode = "rgmii";
0777 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
0778 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
0779 <&cpg CPG_CORE R9A07G044_CLK_HP>;
0780 clock-names = "axi", "chi", "refclk";
0781 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
0782 power-domains = <&cpg>;
0783 #address-cells = <1>;
0784 #size-cells = <0>;
0785 status = "disabled";
0786 };
0787
0788 phyrst: usbphy-ctrl@11c40000 {
0789 compatible = "renesas,r9a07g044-usbphy-ctrl",
0790 "renesas,rzg2l-usbphy-ctrl";
0791 reg = <0 0x11c40000 0 0x10000>;
0792 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
0793 resets = <&cpg R9A07G044_USB_PRESETN>;
0794 power-domains = <&cpg>;
0795 #reset-cells = <1>;
0796 status = "disabled";
0797 };
0798
0799 ohci0: usb@11c50000 {
0800 compatible = "generic-ohci";
0801 reg = <0 0x11c50000 0 0x100>;
0802 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0803 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0804 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
0805 resets = <&phyrst 0>,
0806 <&cpg R9A07G044_USB_U2H0_HRESETN>;
0807 phys = <&usb2_phy0 1>;
0808 phy-names = "usb";
0809 power-domains = <&cpg>;
0810 status = "disabled";
0811 };
0812
0813 ohci1: usb@11c70000 {
0814 compatible = "generic-ohci";
0815 reg = <0 0x11c70000 0 0x100>;
0816 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0817 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0818 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
0819 resets = <&phyrst 1>,
0820 <&cpg R9A07G044_USB_U2H1_HRESETN>;
0821 phys = <&usb2_phy1 1>;
0822 phy-names = "usb";
0823 power-domains = <&cpg>;
0824 status = "disabled";
0825 };
0826
0827 ehci0: usb@11c50100 {
0828 compatible = "generic-ehci";
0829 reg = <0 0x11c50100 0 0x100>;
0830 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0831 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0832 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
0833 resets = <&phyrst 0>,
0834 <&cpg R9A07G044_USB_U2H0_HRESETN>;
0835 phys = <&usb2_phy0 2>;
0836 phy-names = "usb";
0837 companion = <&ohci0>;
0838 power-domains = <&cpg>;
0839 status = "disabled";
0840 };
0841
0842 ehci1: usb@11c70100 {
0843 compatible = "generic-ehci";
0844 reg = <0 0x11c70100 0 0x100>;
0845 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0846 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0847 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
0848 resets = <&phyrst 1>,
0849 <&cpg R9A07G044_USB_U2H1_HRESETN>;
0850 phys = <&usb2_phy1 2>;
0851 phy-names = "usb";
0852 companion = <&ohci1>;
0853 power-domains = <&cpg>;
0854 status = "disabled";
0855 };
0856
0857 usb2_phy0: usb-phy@11c50200 {
0858 compatible = "renesas,usb2-phy-r9a07g044",
0859 "renesas,rzg2l-usb2-phy";
0860 reg = <0 0x11c50200 0 0x700>;
0861 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0862 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0863 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
0864 resets = <&phyrst 0>;
0865 #phy-cells = <1>;
0866 power-domains = <&cpg>;
0867 status = "disabled";
0868 };
0869
0870 usb2_phy1: usb-phy@11c70200 {
0871 compatible = "renesas,usb2-phy-r9a07g044",
0872 "renesas,rzg2l-usb2-phy";
0873 reg = <0 0x11c70200 0 0x700>;
0874 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0875 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0876 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
0877 resets = <&phyrst 1>;
0878 #phy-cells = <1>;
0879 power-domains = <&cpg>;
0880 status = "disabled";
0881 };
0882
0883 hsusb: usb@11c60000 {
0884 compatible = "renesas,usbhs-r9a07g044",
0885 "renesas,rza2-usbhs";
0886 reg = <0 0x11c60000 0 0x10000>;
0887 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
0888 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0889 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0890 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0891 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
0892 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
0893 resets = <&phyrst 0>,
0894 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
0895 renesas,buswait = <7>;
0896 phys = <&usb2_phy0 3>;
0897 phy-names = "usb";
0898 power-domains = <&cpg>;
0899 status = "disabled";
0900 };
0901
0902 wdt0: watchdog@12800800 {
0903 compatible = "renesas,r9a07g044-wdt",
0904 "renesas,rzg2l-wdt";
0905 reg = <0 0x12800800 0 0x400>;
0906 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
0907 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
0908 clock-names = "pclk", "oscclk";
0909 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0910 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0911 interrupt-names = "wdt", "perrout";
0912 resets = <&cpg R9A07G044_WDT0_PRESETN>;
0913 power-domains = <&cpg>;
0914 status = "disabled";
0915 };
0916
0917 wdt1: watchdog@12800c00 {
0918 compatible = "renesas,r9a07g044-wdt",
0919 "renesas,rzg2l-wdt";
0920 reg = <0 0x12800C00 0 0x400>;
0921 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
0922 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
0923 clock-names = "pclk", "oscclk";
0924 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0925 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0926 interrupt-names = "wdt", "perrout";
0927 resets = <&cpg R9A07G044_WDT1_PRESETN>;
0928 power-domains = <&cpg>;
0929 status = "disabled";
0930 };
0931
0932 wdt2: watchdog@12800400 {
0933 compatible = "renesas,r9a07g044-wdt",
0934 "renesas,rzg2l-wdt";
0935 reg = <0 0x12800400 0 0x400>;
0936 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
0937 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
0938 clock-names = "pclk", "oscclk";
0939 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0940 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0941 interrupt-names = "wdt", "perrout";
0942 resets = <&cpg R9A07G044_WDT2_PRESETN>;
0943 power-domains = <&cpg>;
0944 status = "disabled";
0945 };
0946
0947 ostm0: timer@12801000 {
0948 compatible = "renesas,r9a07g044-ostm",
0949 "renesas,ostm";
0950 reg = <0x0 0x12801000 0x0 0x400>;
0951 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
0952 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
0953 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
0954 power-domains = <&cpg>;
0955 status = "disabled";
0956 };
0957
0958 ostm1: timer@12801400 {
0959 compatible = "renesas,r9a07g044-ostm",
0960 "renesas,ostm";
0961 reg = <0x0 0x12801400 0x0 0x400>;
0962 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
0963 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
0964 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
0965 power-domains = <&cpg>;
0966 status = "disabled";
0967 };
0968
0969 ostm2: timer@12801800 {
0970 compatible = "renesas,r9a07g044-ostm",
0971 "renesas,ostm";
0972 reg = <0x0 0x12801800 0x0 0x400>;
0973 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
0974 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
0975 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
0976 power-domains = <&cpg>;
0977 status = "disabled";
0978 };
0979 };
0980
0981 thermal-zones {
0982 cpu-thermal {
0983 polling-delay-passive = <250>;
0984 polling-delay = <1000>;
0985 thermal-sensors = <&tsu 0>;
0986 sustainable-power = <717>;
0987
0988 cooling-maps {
0989 map0 {
0990 trip = <&target>;
0991 cooling-device = <&cpu0 0 2>;
0992 contribution = <1024>;
0993 };
0994 };
0995
0996 trips {
0997 sensor_crit: sensor-crit {
0998 temperature = <125000>;
0999 hysteresis = <1000>;
1000 type = "critical";
1001 };
1002
1003 target: trip-point {
1004 temperature = <100000>;
1005 hysteresis = <1000>;
1006 type = "passive";
1007 };
1008 };
1009 };
1010 };
1011
1012 timer {
1013 compatible = "arm,armv8-timer";
1014 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1015 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1016 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1017 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1018 };
1019 };
